RISC-V Processor Implementations

This repository contains two implementations of a RISC-V RV32I processor:

Projects

1. Single Cycle Processor

A straightforward single-cycle implementation of the RISC-V RV32I architecture. Each instruction completes in one clock cycle.

📁 Location: Single_Cycle_Processor/
📖 Documentation: Single_Cycle_Processor/README.md

Key Features:

• Simple datapath design
• One instruction per cycle
• Full RV32I support
• UART communication interface

2. Pipelined Processor

A high-performance 5-stage pipelined processor with hazard detection and control.

📁 Location: Pipelined_Processor/
📖 Documentation: Pipelined_Processor/README.md

Key Features:

• 5-stage pipeline (IF, ID, EX, MEM, WB)
• Data hazard detection
• Pipeline stalling mechanism
• Branch/jump handling
• Higher throughput than single-cycle

Architecture

Both processors implement the RISC-V 32-bit base integer instruction set (RV32I):

• Arithmetic operations (ADD, SUB, AND, OR, SLT)
• Memory operations (LW, SW)
• Control flow (BEQ, JAL)
• Immediate operations (ADDI, LUI)

Directory Structure

RISC-V-Processor/
├── Single_Cycle_Processor/
│   ├── src/
│   │   ├── single_cycle_processor/
│   │   │   ├── src/          # Core modules
│   │   │   └── sim/          # Testbenches
│   │   └── uart/
│   │       └── src/          # UART modules
│   └── README.md
│
└── Pipelined_Processor/
    ├── src/
    │   ├── pipelined_processor/
    │   │   ├── src/          # Core modules
    │   │   └── sim/          # Testbenches
    │   └── uart/
    │       └── src/          # UART modules
    └── README.md

Getting Started

Prerequisites

• Icarus Verilog (for simulation)
• GTKWave (optional, for waveform viewing)
• Quartus (optional, for FPGA synthesis)

Running Simulations

Single Cycle:

cd Single_Cycle_Processor/src/single_cycle_processor/src
iverilog -g2012 -o ../sim/test *.v ../sim/tb_riscv_core.v
cd ../sim
vvp test
gtkwave riscv_core.vcd

Pipelined:

cd Pipelined_Processor/src/pipelined_processor/src
iverilog -g2012 -o ../sim/test *.v ../sim/tb_riscv_pipeline.v
cd ../sim
vvp test
gtkwave riscv_pipeline.vcd

Implementation Comparison

Feature	Single Cycle	Pipelined
CPI	1 (fixed)	~1 (variable)
Clock Period	Long	Short
Throughput	Lower	Higher
Complexity	Simple	Complex
Hazard Handling	Not needed	Required
Best For	Learning, simple apps	Performance-critical

Design Philosophy

Both implementations prioritize:

• Clarity: Clean, readable Verilog code
• Modularity: Well-separated functional blocks
• Parameterization: Configurable data widths
• Testability: Comprehensive testbenches
• Synthesis: FPGA-ready designs

Hardware Requirements

Tested on:

• Altera DE2-115 FPGA Board
• Xilinx FPGAs (with minor modifications)

License

This project is for educational purposes.

Author

Bavan2002

Acknowledgments

Based on the RISC-V instruction set architecture specification.