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RISC-V Single Cycle Processor

A clean implementation of a single-cycle RISC-V RV32I processor with UART communication interface.

Overview

This repository contains a synthesizable Verilog implementation of a single-cycle RISC-V processor supporting the RV32I base instruction set. The design emphasizes modularity and clarity while maintaining full functionality.

Architecture

The processor implements a classic single-cycle datapath with the following components:

  • Arithmetic Unit: Configurable ALU supporting ADD, SUB, OR, AND, SLT operations
  • Register Bank: 32 general-purpose registers (x0-x31)
  • Program Counter: 16-bit counter for instruction addressing
  • Instruction Memory: ROM containing program instructions
  • Data Memory: RAM for load/store operations
  • Control Unit: Hierarchical decoder for instruction control signals
  • Immediate Generator: Supports I, S, B, U, and J-type immediate formats

Directory Structure

src/
├── single_cycle_processor/
│   ├── src/          # Core processor modules
│   └── sim/          # Testbenches
└── uart/
    └── src/          # UART communication modules

Modules

Core Processor

  • riscv_core.v - Top-level processor integration
  • arithmetic_unit.v - ALU implementation
  • register_bank.v - Register file
  • counter.v - Program counter
  • instruction_memory.v - Instruction ROM
  • data_mem.v - Data RAM
  • control_unit.v - Main control logic
  • instruction_decoder.v - Opcode decoder
  • alu_decoder.v - ALU operation decoder
  • immediate_generator.v - Immediate value extractor
  • adder_unit.v - Simple adder module

UART Interface

  • baud_generator.v - Configurable baud rate clock
  • uart_transmitter.v - Serial data transmission
  • uart_receiver.v - Serial data reception

Simulation

Requirements:

  • Icarus Verilog
  • GTKWave (optional, for waveform viewing)

To run simulation:

cd src/single_cycle_processor/src
iverilog -g2012 -o ../sim/test *.v ../sim/tb_riscv_core.v
cd ../sim
vvp test
gtkwave riscv_core.vcd

Features

  • Full RV32I instruction support (ADD, SUB, AND, OR, SLT, Load, Store, Branch, JAL, LUI)
  • Parameterized data widths for flexibility
  • Clean hierarchical design
  • Comprehensive testbench with detailed output
  • UART interface for external communication
  • Synthesizable for FPGA deployment
  • Well-documented code structure

Implementation Details

The processor operates on a single clock cycle per instruction. Control signals are generated combinationally from the instruction opcode, while the datapath executes the operation within one clock period.

Key design decisions:

  • Register 0 hardwired to zero
  • Little-endian memory organization
  • Synchronous register writes
  • Asynchronous reads for register file and memories