Electronic and Telecommunication Engineering undergraduate at the University of Moratuwa, Sri Lanka, with a strong focus on FPGA based acceleration, digital microarchitecture, and hardware/software co-design.

Currently working as a Part-time Associate Engineer at Aevocode (Pvt) Ltd, contributing to real time FPGA systems, high speed interfaces, and embedded Linux integration.

• FPGA-based hardware acceleration for performance critical workloads
• RTL design and digital microarchitecture (pipelining, FSMs, control/data paths)
• High speed interfaces and timing aware system integration
• Hardware/software co-design for real time embedded systems

Digital Design & HDL: Verilog, SystemVerilog
FPGA Tools: Vivado, Quartus
Embedded & Low-Level Software: C, C++, Linux kernel drivers
Scripting & Automation: Python, Bash, Makefiles
Verification: Cocotb

• FPGA-Based Gemma SLM Accelerator Custom FPGA accelerator for a small language model, optimizing matrix operations and attention kernels for edge deployment.
  DVCon India 2025 Design Contest – 1st Runner-up

• SIMD CNN Processor Custom FPGA-based SIMD processor for convolutional neural networks, exploiting data-level parallelism to accelerate convolution, activation, and pooling operations on resource-constrained hardware.

• Pipelined RISC-V (RV32I) Processor Five-stage pipelined processor with control hazard handling, data hazard management, and UART-based debug infrastructure.

• Lightweight Serial System Bus Custom multi-master serial bus with split transactions, FIFO buffering, and FSM-based protocol control.

FPGA systems · Hardware acceleration · Digital IC design · Low-latency architectures · Embedded systems