A high-performance Last-Level (L2) Cache Controller implementation with MESI coherence protocol in SystemVerilog. This design features an 8-way set-associative cache architecture with Pseudo-LRU (PLRU) replacement policy, comprehensive coherence management, and advanced performance monitoring capabilities.
Project Name: L2Cache-MESI
Author: Sundarbavan
Date: October 2025
Language: SystemVerilog
License: Educational Use
16 MB Cache - Large capacity L2 cache with 262,144 lines
MESI Protocol - Full implementation of Modified-Exclusive-Shared-Invalid coherence
8-Way Set Associative - High associativity for reduced conflict misses
PLRU Replacement - Efficient pseudo-LRU with binary tree structure
Comprehensive Testing - 3 testbenches with >95% coverage
Performance Monitoring - Built-in statistics and hit rate tracking
Industry Standard - Clean, well-documented, synthesizable RTL
rtl/- All synthesizable RTL design files (9 modules)tb/- All testbench files (3 comprehensive testbenches)README.md- Complete project documentation
# Compile
vlib work && vlog -sv +incdir+rtl rtl/*.sv tb/*.sv
# Run all tests
vsim -c tb_PLRU -do "run -all; quit"
vsim -c tb_L2CacheController -do "run -all; quit"
vsim -c tb_CoherenceProtocol -do "run -all; quit"- Capacity: 16 MB total cache size
- Associativity: 8-way set associative
- Sets: 32,768 sets (2^15)
- Line Size: 64 bytes
- Total Lines: 262,144 cache lines
[31:21] Tag (11 bits)
[20:6] Index (15 bits)
[5:0] Byte Offset (6 bits)
- Protocol: MESI (Modified, Exclusive, Shared, Invalid)
- Replacement Policy: Pseudo-LRU (PLRU) with 7-bit binary tree
- Snooping: Full support for bus snooping and coherence maintenance
.
├── rtl/ # RTL Design Files
│ ├── ParameterDefinitions.sv # System-wide parameters and constants
│ ├── CacheStructure.sv # Cache data structures and MESI states
│ ├── L2CacheController.sv # Main cache controller module
│ ├── PLRU_Get.sv # PLRU victim selection logic
│ ├── PLRU_Update.sv # PLRU state update logic
│ ├── GetSnoopResult.sv # Snoop result simulation
│ ├── PutSnoopResult.sv # Snoop result reporting
│ ├── BusOperation.sv # System bus operation simulation
│ └── MessageToCache.sv # L2-to-L1 communication interface
│
├── tb/ # Testbench Files
│ ├── tb_PLRU.sv # PLRU module testbench
│ ├── tb_L2CacheController.sv # Main controller testbench
│ └── tb_CoherenceProtocol.sv # Coherence protocol testbench
│
└── README.md # This file
The top-level cache controller that integrates all components.
Features:
- MESI state machine for coherence
- Tag matching and hit/miss detection
- PLRU-based replacement
- Bus operation management
- Performance counter tracking
- L1 cache communication
Interface:
- Clock and active-low reset
- Address and operation inputs
- Processor read/write requests
- Bus snoop signals
- Performance statistics outputs
Determines the least-recently-used way for eviction using a 7-bit binary tree structure.
Updates the PLRU tree state when a cache line is accessed, marking it as most recently used.
Simulates snoop responses from other processor caches (HIT, HITM, NOHIT).
Simulates system bus transactions: READ, WRITE, INVALIDATE, RWIM (Read With Intent to Modify).
Manages L2-to-L1 cache communication for line transfers, invalidations, and evictions.
PrRd/NOHIT PrWr
INVALID -----------> EXCLUSIVE ----> MODIFIED
| | |
| PrRd/HIT |
| | |
+----------> SHARED <-+ |
| |
PrWr BusRd
+--------------------> +
v
SHARED
| State | Description | Dirty | Sharers |
|---|---|---|---|
| Modified | Cache line modified, exclusive ownership | Yes | No |
| Exclusive | Cache line clean, exclusive ownership | No | No |
| Shared | Cache line clean, may be in other caches | No | Possible |
| Invalid | Cache line not present or invalidated | N/A | N/A |
- I → E: Read miss with no other sharers
- I → S: Read miss with other caches having the line
- I → M: Write miss (fetch with exclusive ownership)
- E → M: Write hit (silent upgrade, no bus transaction)
- S → M: Write hit (requires BusUpgr to invalidate copies)
- M → S: Another cache reads (flush dirty data)
- M → I: Another cache writes (flush and invalidate)
Tests the Pseudo-LRU replacement algorithm.
Tests Include:
- Initial state verification
- Sequential way access patterns
- PLRU update correctness
- Victim selection after updates
- Round-robin access patterns
- Random access stress test
- State space coverage analysis
Comprehensive testbench for the main cache controller.
Tests Include:
- Basic read/write operations
- Cache hit/miss detection
- MESI state transitions
- PLRU replacement policy
- Multiple address handling
- Coherence protocol scenarios
- Performance counter validation
- Random operation stress testing
Tests MESI coherence protocol behavior and bus operations.
Tests Include:
- Snoop result generation
- Bus operation execution
- MESI state encoding
- L2-to-L1 message passing
- State transition scenarios
- Protocol coverage analysis
The cache controller tracks the following metrics:
- stat_reads: Total number of read operations
- stat_writes: Total number of write operations
- stat_hits: Total cache hits
- stat_misses: Total cache misses
- Hit Rate: Calculated as (hits / total_operations) × 100%
The design supports three debug levels controlled by +MODE plusarg:
- SILENT: No output (default)
- NORMAL: Bus operations and L2↔L1 messages
- DEBUG: Detailed state transitions, PLRU updates, and miss information
Potential areas for expansion:
- Directory-based coherence for scalability
- Write-back buffer for improved performance
- Prefetching logic for sequential access patterns
- Power management features
- AXI/AHB bus interface for industry standard compliance
- ECC support for error correction
- Performance profiling tools
- MESI Protocol: Papamarcos, M. S., & Patel, J. H. (1984). "A low-overhead coherence solution for multiprocessors with private cache memories"
- Pseudo-LRU: "Tree-PLRU Replacement Algorithm for Set-Associative Caches"
- Cache Architecture: Hennessy & Patterson, "Computer Architecture: A Quantitative Approach"
This project is for educational purposes. Not licensed for commercial use.
Last Updated: October 16, 2025