Add Chip Design environment#407

Merged

josephdviviano merged 33 commits intomasterfrom

Apr 4, 2026

Commits on Oct 7, 2025

Commits on Oct 23, 2025

refactor
younik
committed

Commits on Oct 25, 2025

add PLC wrapper main
younik
committed

Commits on Oct 28, 2025

fixes
younik
committed
fixes, refactor & tests
younik
committed
pre-commit
younik
committed

Commits on Oct 30, 2025

fix pre-commit + add credits
younik
committed

Commits on Nov 2, 2025

add initial printing
younik
committed

Commits on Apr 3, 2026

Replace bundled binary with download script + Apptainer support

josephdviviano
and
claude
committed
Merge origin/master into chip-design

josephdviviano
and
claude
committed
Add singularity wrapper for plc_wrapper_main and fix master compat

josephdviviano
and
claude
committed
Fix CUDA/CPU device mismatch in States._compare

josephdviviano
and
claude
committed
Fix pyright type error and apply black formatting

josephdviviano
and
claude
committed
Merge origin/chip-design: integrate download script + apptainer support

josephdviviano
and
claude
committed
black
josephdviviano
committed
Restore plc_wrapper_main binary

josephdviviano
and
claude
committed
Note GCS 403 in setup_plc.sh, binary is bundled in repo

josephdviviano
and
claude
committed
Fix missing singularity_image attr in ChipDesignArgs test dataclass

josephdviviano
and
claude
committed
Apply suggestion from @Copilot

josephdviviano
and
Copilot
authored
Fix get_blockages_from_comments to handle single string input correctly

Copilot
and
josephdviviano
authored
Add close() and __del__() to ChipDesign to prevent PlacementCost subprocess leak

Copilot
and
josephdviviano
authored
Apply suggestions from code review

josephdviviano
and
Copilot
authored
Fix multi-dim batch_shape support in ChipDesign env

josephdviviano
and
claude
committed
Remove duplicate singularity_image field in ChipDesignArgs

josephdviviano
and
claude
committed
Add coordinate descent orientation optimization

josephdviviano
and
claude
committed
Add --cd_finetune flag and CD comparison to train_chip_design.py

josephdviviano
and
claude
committed
Add reward normalization (zscore/minmax) with pre-computable stats

josephdviviano
and
claude
committed
Add missing cd_finetune to ChipDesignArgs test dataclass

josephdviviano
and
claude
committed