Implement initial spilling algorithm for RISC-V

[anominos]

In this PR, we add a pass that performs register spilling within a basic block for the RISC-V dialect.

We first perform a liveness analysis on the block, maintaining a live set at each operation, and inserting custom spill and load ops where necessary. Then we convert the custom spills and loads into the corresponding RISC-V memory ops in a second pass.

This PR assumes all values are 32 bit integers and does not implement any spilling heuristics.

[codecov]

Codecov Report

❌ Patch coverage is 93.59606% with 13 lines in your changes missing coverage. Please review.
✅ Project coverage is 86.54%. Comparing base (53d9b8b) to head (363b2d3).
⚠️ Report is 21 commits behind head on main.

Files with missing lines	Patch %	Lines
...end/riscv/lowering/convert_riscv_stack_to_riscv.py	91.66%	2 Missing and 3 partials ⚠️
xdsl/dialects/riscv/stack.py	90.24%	2 Missing and 2 partials ⚠️
xdsl/backend/riscv/prologue_epilogue_insertion.py	85.71%	1 Missing and 1 partial ⚠️
xdsl/transforms/test_riscv_spilling.py	97.43%	1 Missing and 1 partial ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #5775      +/-   ##
==========================================
+ Coverage   86.39%   86.54%   +0.14%     
==========================================
  Files         421      425       +4     
  Lines       60923    61713     +790     
  Branches     6991     7081      +90     
==========================================
+ Hits        52637    53412     +775     
- Misses       6706     6711       +5     
- Partials     1580     1590      +10     

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