Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)
-
Updated
Jun 13, 2025
Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)
A set of simple example projects aimed at streamlining the development process of a complex design for Xilinx SoCs. It utilizes custom FPGA IPs with interrupts, linux kernel with real-time patch, custom kernel modules and an app taking advantage of CPU isolation.
🏄 Custom IP for vector operations
Add a description, image, and links to the custom-ip topic page so that developers can more easily learn about it.
To associate your repository with the custom-ip topic, visit your repo's landing page and select "manage topics."