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1 change: 1 addition & 0 deletions src/engine/compiler/MacroAssembler.v3
Original file line number Diff line number Diff line change
Expand Up @@ -299,6 +299,7 @@ class MacroAssembler(valuerep: Tagging, regConfig: RegConfig) {

def emit_binop_r_r(op: Opcode, reg: Reg, reg2: Reg);
def emit_binop_r_m(op: Opcode, reg: Reg, addr: MasmAddr);
def emit_binop_m_r(op: Opcode, addr: MasmAddr, reg: Reg);
def emit_binop_r_i(op: Opcode, reg: Reg, val: int);

def emit_pop_r(kind: ValueKind, reg: Reg);
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8 changes: 6 additions & 2 deletions src/engine/compiler/RegSet.v3
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,11 @@

// Architecture-independent representation of a register for use in {MacroAssembler} and portable
// parts of compilers. Kept small to keep data structures small. The name is stored in a {RegSet}.
type Reg(index: byte) #unboxed { }
type Reg(index: byte) #unboxed {
def plus(offset: int) -> MasmAddr {
return MasmAddr(this, offset);
}
}

// Describes the set of (maximum 256) registers for a target.
// By convention, register #0 is reserved for indicating an unallocated register or no register.
Expand Down Expand Up @@ -49,4 +53,4 @@ class RegPool32(regs: Array<Reg>) {
map = Array<u5>.new(max + 1);
for (i < regs.length) map[regs[i].index] = u5.!(i);
}
}
}
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