RADLoader

Production workflow for PAC52xx using time-multiplexed SWD and UART.

Layout

• bootloader/ - Bootloader source package (5s boot detect window, SWD-safe startup behavior)
• app/ - Example application source package (main.c is the file you usually edit)
• tools/ - Build scripts
• build_and_flash.bat - Single command to build both images and flash both
• monitor_uart.bat / monitor_uart.ps1 - Continuous UART monitor

Flashing Systems

1. SWD flash system (build_and_flash.bat)

• Purpose: compile + program bootloader and app.
• Transport: SWD only.
• Hardware used: STLink V2 probe + PAC52xx EVK target.
• OpenOCD board config: board/pac52xx_evk.cfg.
• COM port usage: none.

2. Runtime UART monitor (monitor_uart.bat)

• Purpose: view live app/bootloader text output.
• Transport: UART only.
• Hardware used: USB-UART bridge connected to PE1/PE2.
• Default serial port: COM40 at 115200.

3. Bootloader command channel (optional service/debug)

• Purpose: enter bootloader UART mode and exchange protocol bytes (detect 0xAA, response 0x7E).
• Transport: UART plus STLink reset orchestration (external helper script in PACFLASH/tools).
• COM port usage: same UART COM port.
• tools/uart_flash_app.ps1 default detect timeout is 32000 ms (-DetectTimeoutMs) so it spans the 20s SWD guard plus UART detect window.

Safe mode behavior

On every reset, bootloader startup now follows this sequence:

1. SWD is enabled immediately.
2. If PBTN is detected, bootloader latches into SWD hold mode and does not jump to app.
3. If PBTN is not detected, SWD-only guard window is held for SWD_GUARD_TIMEOUT_MS (default 20000 ms).
4. Bootloader enters UART detect mode for BOOTLOAD_REQUEST_TIMEOUT_MS (default 5000 ms).
5. If no bootload request arrives, control transfers to app.
6. During bootloader detect/app runtime, pressing PBTN forces SWD hold mode until next reset.

UART single-byte control commands in detect/app modes:

• 0xAA: enter bootloader command mode (bootloader responds with 0x7E).
• 0x53: enter SWD hold mode (failsafe lock for recovery).

Bootloader protocol command:

• BL_CMD_ENTER_SWD_MODE (command ID 0x06): puts target into SWD hold mode from bootloader protocol.

SWD safety policy in this repo:

• Bootloader/app now default to never disabling SWD-at-POR in firmware paths (BL_PREVENT_SWD_DISABLE=1, APP_PREVENT_SWD_DISABLE=1).
• SWD_GUARD_TIMEOUT_MS is set to 20000 ms.

Shared pin note (PD0/PD1):

• In shared mode, once app configures UART on PD0/PD1, continuous live SWD attach is not guaranteed.
• Entering SWD hold via PBTN or command now explicitly remaps PD0/PD1 back to SWD and then latches there until reset.
• UART receive polling now probes both PD0/PD1 TX/RX directions in shared mode, so command bytes can still be detected if wiring orientation is reversed.

One-command build + flash

From C:\Qorvo:

RADLoader\build_and_flash.bat

From Git Bash:

cmd.exe /c RADLoader\\build_and_flash.bat

What it does:

1. Builds bootloader binary
2. Builds app binary
3. Mass-erases device
4. Flashes bootloader at 0x00000000
5. Flashes app at 0x00001000
6. Verifies both images and starts execution

If flashing fails with unable to connect to the target, check EVK power and STLink wiring first, then retry.

PAC5285 note: this flow does not require an external SRST pin. build_and_flash.bat uses a no-SRST attach sequence by default.

Continuous UART monitor

From C:\Qorvo:

RADLoader\monitor_uart.bat

Expected example output:

app uart monitor ready
uptime = 0ms
uptime = 100ms
...

Boot startup also prints:

RADLoader V1.2
uart detect mode

Stop with Ctrl+C.

SWD recovery (hold-reset flow)

If normal flashing fails with unable to connect to the target, run:

RADLoader\recover_swd_hold_reset.bat

This script performs two recovery attempts automatically:

1. No-reset attach at very low SWD speed, then mass erase.
2. Connect-under-reset path (only if SRST is actually wired), then mass erase.

PAC5285 reset behavior: use the board PB button (hold ~4s) to trigger hardware reset before the recovery attempts.

If this script still reports RECOVERY FAILED, the issue is below the build/script layer (typically reset wiring, SWD signal integrity, or probe/target electrical state).

Automated recovery helper:

• RADLoader\tools\recover_swd_bruteforce.ps1 repeats low-speed SWD attach + mass erase attempts to catch narrow reset windows.

Typical edit loop

1. Edit app code in RADLoader\app\main.c
2. Run RADLoader\build_and_flash.bat
3. Run RADLoader\monitor_uart.bat

Optional environment overrides

Set these only if your paths/ports differ:

• RADLOADER_TOOLROOT (default: C:\ncs\toolchains\c1a76fddb2\opt\zephyr-sdk\arm-zephyr-eabi\bin)
• RADLOADER_OPENOCD (default: C:\Qorvo\OpenOCD\0.10.0-8-20180512-1921\bin\openocd.exe)
• RADLOADER_OPENOCD_SCRIPTS (default: C:\Qorvo\OpenOCD\0.10.0-8-20180512-1921\scripts)
• RADLOADER_BOARD_CFG (default: board/pac52xx_evk.cfg)
• RADLOADER_COM (default: COM40)
• RADLOADER_BAUD (default: 115200)

Notes

• Use STLink V2 for SWD operations in this flow.
• UART monitoring depends on OS COM enumeration. If COM40 is absent, replug the USB-UART adapter and rerun monitor.

Pin routing

Current default build (shared interface on PD0/PD1):

• SWD and UART share PD0/PD1 with boot-time safety gating.

Optional test override (separated interfaces):

• Set BL_UART_PIN_MODE in bootloader/src/bootloader_config.h to BL_UART_PIN_MODE_SEPARATE.
• Set APP_UART_PIN_MODE in app/main.c to APP_UART_PIN_MODE_SEPARATE.
• This routes UART to PE1 (TXD) and PE2 (RXD) while keeping SWD on PD0/PD1.