feat(pci/dwc): add DWC MSI virtualization support and deferred PCI init

Cargo.toml

@@ -64,6 +64,8 @@ ecam_pcie = [] # Standard ECAM mechanism (default for most platforms)
 dwc_pcie = [] # DesignWare PCIe Core mechanism (CFG0/CFG1, used by RK3568)
 loongarch64_pcie = [] # LoongArch PCIe mechanism (used by LoongArch platforms)
 no_pcie_bar_realloc = []
+dwc_msi = ["dwc_pcie"] # DesignWare Native MSI (used when arch doesn't provide MSI, e.g., ARM without ITS)
+pci_init_delay = ["dwc_pcie"] # Delay hvisor PCI init until guest DBI offset 0 access
 
 ############# aarch64 ##############
 # irqchip driver

platform/aarch64/imx8mp/board.rs

@@ -21,6 +21,9 @@ use crate::{
     config::*,
 };
 
+use crate::pci::vpci_dev::VpciDevType;
+use crate::pci_dev;
+
 pub const BOARD_NAME: &str = "imx8mp";
 
 pub const BOARD_NCPUS: usize = 4;
@@ -107,14 +110,23 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 8] = [
        //     virtual_start: 0x30890000,
        //     size: 0x1000,
        // }, // serial
+       // 0x32f00000
+       // HvConfigMemoryRegion {
+       //     mem_type: MEM_TYPE_IO,
+       //     physical_start: 0x32f00000,
+       //     virtual_start: 0x32f00000,
+       //     size: 0x10000,
+       // }, // pcie-phy
 ];
 
 pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20;
 pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[
     35, 36, 37, 38, 45, 52, 55, 56, 57, 59, 64, 67, 75, 96, 97, 98, 99, 100, 101, 102, 103, 104,
-    105, 135, 150, 151, 152, 162,
+    105, 135, 150, 151, 152, 162, 172, 159,
 ]);
 
+pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
+
 pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
     is_aarch32: 0,
     gic_config: GicConfig::Gicv3(Gicv3Config {
@@ -127,4 +139,37 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
     }),
 };
 
-pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
+pub const ROOT_PCI_CONFIG: &[HvPciConfig] = &[HvPciConfig {
+    ecam_base: 0x33800000,
+    ecam_size: 0x400000,
+    io_base: 0x1ff80000,
+    io_size: 0x10000,
+    pci_io_base: 0x0,
+    mem32_base: 0x1800_0000,
+    mem32_size: 0x7f0_0000,
+    pci_mem32_base: 0x1800_0000,
+    mem64_base: 0x0,
+    mem64_size: 0x0,
+    pci_mem64_base: 0x0,
+    bus_range_begin: 0x0,
+    bus_range_end: 0x1f,
+    domain: 0x0,
+}];
+
+pub const ROOT_DWC_ATU_CONFIG: &[HvDwcAtuConfig] = &[HvDwcAtuConfig {
+    ecam_base: 0x33800000,
+    dbi_base: 0x33800000,
+    dbi_size: 0x400000,
+    apb_base: 0x0,
+    apb_size: 0x0,
+    cfg_base: 0x1ff00000,
+    cfg_size: 0x80000,
+    io_cfg_atu_shared: 1,
+    io_atu_index: 1,
+    dw_msi_irq: 172,
+}];
+
+pub const ROOT_PCI_DEVS: [HvPciDevConfig; 2] = [
+    pci_dev!(0x0, 0x00, 0x0, 0x0, VpciDevType::Physical),
+    pci_dev!(0x0, 0x01, 0x0, 0x0, VpciDevType::Physical),
+];

platform/aarch64/imx8mp/cargo/features

@@ -1,2 +1,7 @@
 gicv3
 imx_uart
+pci
+dwc_pcie
+no_pcie_bar_realloc
+dwc_msi
+pci_init_delay

platform/aarch64/imx8mp/configs/zone1-linux.json

@@ -2,80 +2,148 @@
     "arch": "arm64",
     "name": "linux2",
     "zone_id": 1,
-    "cpus": [2, 3],
+    "cpus": [
+        2,
+        3
+    ],
     "memory_regions": [
         {
             "type": "ram",
             "physical_start": "0x50000000",
-            "virtual_start":  "0x50000000",
+            "virtual_start": "0x50000000",
             "size": "0x30000000"
         },
         {
             "type": "io",
             "physical_start": "0x30a60000",
-            "virtual_start":  "0x30a60000",
+            "virtual_start": "0x30a60000",
             "size": "0x10000"
         },
         {
             "type": "virtio",
             "physical_start": "0xa003c00",
-            "virtual_start":  "0xa003c00",
+            "virtual_start": "0xa003c00",
             "size": "0x200"
         },
         {
             "type": "virtio",
             "physical_start": "0xa003800",
-            "virtual_start":  "0xa003800",
+            "virtual_start": "0xa003800",
             "size": "0x200"
         },
         {
             "type": "virtio",
             "physical_start": "0xa003600",
-            "virtual_start":  "0xa003600",
+            "virtual_start": "0xa003600",
             "size": "0x200"
         },
         {
             "type": "io",
             "physical_start": "0x38000000",
-            "virtual_start":  "0x38000000",
+            "virtual_start": "0x38000000",
             "size": "0x10000"
         },
         {
             "type": "io",
             "physical_start": "0x38500000",
-            "virtual_start":  "0x38500000",
+            "virtual_start": "0x38500000",
             "size": "0x20000"
         },
         {
             "type": "io",
             "physical_start": "0x32e80000",
-            "virtual_start":  "0x32e80000",
+            "virtual_start": "0x32e80000",
             "size": "0x20000"
         },
         {
             "type": "io",
             "physical_start": "0x30c00000",
-            "virtual_start":  "0x30c00000",
+            "virtual_start": "0x30c00000",
             "size": "0x400000"
         },
         {
             "type": "io",
             "physical_start": "0x32fc0000",
-            "virtual_start":  "0x32fc0000",
+            "virtual_start": "0x32fc0000",
             "size": "0x20000"
         }
     ],
-    "interrupts": [35, 37, 38, 45, 56, 57, 61, 75, 76, 78, 135, 162],
+    "interrupts": [
+        35,
+        37,
+        38,
+        45,
+        56,
+        57,
+        61,
+        75,
+        76,
+        78,
+        135,
+        162,
+        172
+    ],
     "ivc_configs": [],
     "kernel_filepath": "./Image",
     "dtb_filepath": "./linux2.dtb",
     "kernel_load_paddr": "0x50400000",
-    "dtb_load_paddr":   "0x50000000",
-    "entry_point":      "0x50400000",
+    "dtb_load_paddr": "0x50000000",
+    "entry_point": "0x50400000",
     "arch_config": {
+        "gic_version": "v3",
         "gicd_base": "0x38800000",
         "gicd_size": "0x10000",
         "gicr_base": "0x38880000",
-        "gicr_size": "0xc0000"
-    }
+        "gicr_size": "0xc0000",
+        "is_aarch32": false
+    },
+    "pci_config": [
+        {
+            "ecam_base": "0x33800000",
+            "ecam_size": "0x400000",
+            "io_base": "0x1ff80000",
+            "io_size": "0x10000",
+            "pci_io_base": "0x0",
+            "mem32_base": "0x18000000",
+            "mem32_size": "0x7f00000",
+            "pci_mem32_base": "0x18000000",
+            "mem64_base": "0x0",
+            "mem64_size": "0x0",
+            "pci_mem64_base": "0x0",
+            "bus_range_begin": "0x0",
+            "bus_range_end": "0x1f",
+            "domain": "0x0"
+        }
+    ],
+    "dwc_atu_config": [
+        {
+            "ecam_base": "0x33800000",
+            "dbi_base": "0x33800000",
+            "dbi_size": "0x400000",
+            "apb_base": "0x0",
+            "apb_size": "0x0",
+            "cfg_base": "0x1ff00000",
+            "cfg_size": "0x10000",
+            "io_cfg_atu_shared": 1,
+            "io_atu_index": 1,
+            "dw_msi_irq": 172
+        }
+    ],
+    "num_pci_devs": 2,
+    "alloc_pci_devs": [
+        {
+            "domain": "0x0",
+            "bus": "0x0",
+            "device": "0x0",
+            "function": "0x0",
+            "dev_type": "0"
+        },
+        {
+            "domain": "0x0",
+            "bus": "0x1",
+            "device": "0x0",
+            "function": "0x1",
+            "dev_type": "0"
+        }
+    ]
 }

platform/aarch64/rk3568/board.rs

@@ -348,6 +348,8 @@ pub const ROOT_DWC_ATU_CONFIG: &[HvDwcAtuConfig] = &[HvDwcAtuConfig {
     cfg_base: 0xf2000000,
     cfg_size: 0x80000 * 2,
     io_cfg_atu_shared: 0,
+    io_atu_index: 0,
+    dw_msi_irq: 0,
 }];
 
 pub const ROOT_PCI_DEVS: [HvPciDevConfig; 2] = [

src/config.rs

@@ -257,6 +257,10 @@ pub struct HvDwcAtuConfig {
     // set 1 if io base use atu0, when hvisor need set mmio for io
     // normally, when num-viewport less than 4, io_cfg_atu_shared is 1, otherwise is 0
     pub io_cfg_atu_shared: u64,
+    // choose the atu index for io and cfg access, when io_cfg_atu_shared is 1, io and cfg use the same atu index, otherwise use different atu index
+    pub io_atu_index: u64,
+    // Shared hardware interrupt ID for this DWC RC MSI block
+    pub dw_msi_irq: u64,
 }
 
 impl HvDwcAtuConfig {
@@ -273,6 +277,8 @@ impl HvDwcAtuConfig {
             cfg_base: 0,
             cfg_size: 0,
             io_cfg_atu_shared: 0,
+            io_atu_index: 0,
+            dw_msi_irq: 0,
         }
     }
 }

src/consts.rs

@@ -88,6 +88,7 @@ pub fn hv_end() -> VirtAddr {
 pub const IPI_EVENT_CLEAR_INJECT_IRQ: usize = 4;
 pub const IPI_EVENT_UPDATE_HART_LINE: usize = 5;
 pub const IPI_EVENT_SEND_IPI: usize = 6;
+pub const IPI_EVENT_DWC_MSI_INJECT: usize = 7;
 
 extern "C" {
     /// Entry point of the hypervisor written in assembly.

src/device/irqchip/gicv3/mod.rs

@@ -44,6 +44,7 @@ use crate::hypercall::SGI_IPI_ID;
 use crate::zone::Zone;
 
 const ICH_HCR_UIE: u64 = 1 << 1;
+
 //TODO: add Distributor init
 pub fn gicc_init() {
     //TODO: add Redistributor init
@@ -109,6 +110,9 @@ pub fn gicv3_handle_irq_el1() {
             warn!("skip sgi {}", irq_id);
             deactivate_irq(irq_id);
         } else {
+            #[cfg(all(feature = "dwc_pcie", feature = "dwc_msi"))]
+            let mut is_dwc_msi_irq = false;
+
             if irq_id == 27 {
                 // virtual timer interrupt
                 TIMER_INTERRUPT_COUNTER.fetch_add(1, core::sync::atomic::Ordering::SeqCst);
@@ -127,12 +131,30 @@ pub fn gicv3_handle_irq_el1() {
             } else if irq_id > 31 {
                 //inject phy irq
                 trace!("*** get spi_irq id = {}", irq_id);
+
+                #[cfg(all(feature = "dwc_pcie", feature = "dwc_msi"))]
+                {
+                    if let Some(domain_id) =
+                        crate::pci::dwc_msi::get_domain_id_by_irq(irq_id as u32)
+                    {
+                        is_dwc_msi_irq = true;
+                        crate::pci::dwc_msi::dwc_msi_transfer_and_inject(domain_id, irq_id);
+                    }
+                }
             } else {
                 warn!("not konw irq id = {}", irq_id);
             }
+
+            #[cfg(all(feature = "dwc_pcie", feature = "dwc_msi"))]
+            if irq_id != 25 && !is_dwc_msi_irq {
+                inject_irq(irq_id, true);
+            }
+
+            #[cfg(not(all(feature = "dwc_pcie", feature = "dwc_msi")))]
             if irq_id != 25 {
                 inject_irq(irq_id, true);
             }
+
             deactivate_irq(irq_id);
         }
     }

src/device/irqchip/gicv3/vgic.rs

@@ -309,7 +309,19 @@ pub fn vgicv3_dist_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
 
     match reg {
         reg if reg_range(GICD_IROUTER, 1024, 8).contains(&reg) => {
-            vgicv3_handle_irq_ops(mmio, (reg - GICD_IROUTER) as u32 / 8)
+            let irq = (reg - GICD_IROUTER) as u32 / 8;
+
+            #[cfg(all(feature = "dwc_pcie", feature = "dwc_msi"))]
+            {
+                // For zone0, the domainmsiinfo is empty, but it will always register the intterrupt to cpu0
+                // So this remap operation is needed for other zones
+                if mmio.is_write && crate::pci::dwc_msi::is_dwc_msi_hwirq(irq) {
+                    info!("remap dwc msi hwirq {} to cpu0!", irq);
+                    mmio.value = 0;
+                }
+            }
+
+            vgicv3_handle_irq_ops(mmio, irq)
         }
         reg if reg_range(GICD_ITARGETSR, 1024, 1).contains(&reg) => {
             vgicv3_handle_irq_ops(mmio, (reg - GICD_ITARGETSR) as u32)

src/event.rs

@@ -17,7 +17,8 @@
 use crate::{
     arch::ipi::{arch_check_events, arch_prepare_send_event, arch_send_event},
     consts::{
-        IPI_EVENT_CLEAR_INJECT_IRQ, IPI_EVENT_SEND_IPI, IPI_EVENT_UPDATE_HART_LINE, MAX_CPU_NUM,
+        IPI_EVENT_CLEAR_INJECT_IRQ, IPI_EVENT_DWC_MSI_INJECT, IPI_EVENT_SEND_IPI,
+        IPI_EVENT_UPDATE_HART_LINE, MAX_CPU_NUM,
     },
     cpu_data::this_cpu_data,
     device::{irqchip::inject_irq, virtio_trampoline::handle_virtio_irq},
@@ -103,6 +104,18 @@ pub fn check_events() -> bool {
             inject_irq(IRQ_WAKEUP_VIRTIO_DEVICE, false);
             true
         }
+        Some(IPI_EVENT_DWC_MSI_INJECT) => {
+            #[cfg(all(
+                target_arch = "aarch64",
+                feature = "gicv3",
+                feature = "dwc_pcie",
+                feature = "dwc_msi"
+            ))]
+            {
+                crate::pci::dwc_msi::handle_dwc_msi_inject_event();
+            }
+            true
+        }
         Some(IPI_EVENT_CLEAR_INJECT_IRQ)
         | Some(IPI_EVENT_UPDATE_HART_LINE)
         | Some(IPI_EVENT_SEND_IPI) => {