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Enable ice emmc for kodiak/monaco#702

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kuld-sing wants to merge 15 commits intoqualcomm-linux:tech/security/icefrom
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Enable ice emmc for kodiak/monaco#702
kuld-sing wants to merge 15 commits intoqualcomm-linux:tech/security/icefrom
kuld-sing:tech/security/ice

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@kuld-sing kuld-sing commented Feb 18, 2026

Document Inline Crypto Engine (ICE) handle for SDHC and add its device-tree
node to enable it for kodiak and monaco.

How this patch was tested:

  • export ARCH=arm64
  • export CROSS_COMPILE=aarch64-linux-gnu-
  • make menuconfig
  • make defconifg
  • make DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/sdhci-msm.yaml dt_binding_check
  • make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- CHECK_DTBS=y dtbs

dmukhopa and others added 15 commits January 22, 2026 15:54
@dmukhopa @sonineerajkumar
FROMLIST: mmc: Avoid reprogram all keys to Inline Crypto Engine for M…
89fcb63 
…MC runtime suspend resume

Crypto reprogram all keys is called for each MMC runtime
suspend/resume in current upstream design. If this is implemented
as a non-interruptible call to TEE for security, the cpu core is
blocked for execution while this call executes although the crypto
engine already has the keys. For example, glitches in audio/video
streaming applications have been observed due to this. Add the flag
MMC_CAP2_CRYPTO_NO_REPROG as part of host->caps2 to control reprogramming
keys to crypto engine for socs which dont require this feature.

Link: https://lore.kernel.org/r/20250718110217.1929526-1-quic_dmukhopa@quicinc.com
Signed-off-by: Seshu Madhavi Puppala <quic_spuppala@quicinc.com>
Co-developed-by: Ram Prakash Gupta <quic_rampraka@quicinc.com>
Signed-off-by: Ram Prakash Gupta <quic_rampraka@quicinc.com>
Co-developed-by: Sarthak Garg <quic_sartgarg@quicinc.com>
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
Signed-off-by: Debraj Mukhopadhyay <quic_dmukhopa@quicinc.com>
@sonineerajkumar
mmc: host: sdhci-msm: Add support for wrapped keys
e95f0f7 
Add the wrapped key support for sdhci-msm by implementing the needed
methods in struct blk_crypto_ll_ops and setting the appropriate flag in
blk_crypto_profile::key_types_supported.

Tested on SC7280 eMMC variant.

How to test:

Use the "v1.3.0" tag from https://github.com/google/fscryptctl and build
fscryptctl that supports generating wrapped keys.

Enable the following config options:
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_QCOM_INLINE_CRYPTO_ENGINE=y
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
CONFIG_MMC_CRYPTO=y

Enable "qcom_ice.use_wrapped_keys" via kernel command line.

$ mkfs.ext4 -F -O encrypt,stable_inodes /dev/disk/by-partlabel/vm-data
$ mount /dev/disk/by-partlabel/vm-data -o inlinecrypt /mnt
$ fscryptctl generate_hw_wrapped_key /dev/disk/by-partlabel/vm-data > /mnt/key.longterm
$ fscryptctl prepare_hw_wrapped_key /dev/disk/by-partlabel/vm-data < /mnt/key.longterm > /tmp/key.ephemeral
$ KEYID=$(fscryptctl add_key --hw-wrapped-key < /tmp/key.ephemeral /mnt)
$ rm -rf /mnt/dir
$ mkdir /mnt/dir
$ fscryptctl set_policy --iv-ino-lblk-32 "$KEYID" /mnt/dir
$ dmesg > /mnt/dir/test.txt
$ sync

Reboot the board

$ mount /dev/disk/by-partlabel/vm-data -o inlinecrypt /mnt
$ ls /mnt/dir # File should be encrypted
$ fscryptctl prepare_hw_wrapped_key /dev/disk/by-partlabel/vm-data < /mnt/key.longterm > /tmp/key.ephemeral
$ KEYID=$(fscryptctl add_key --hw-wrapped-key < /tmp/key.ephemeral /mnt)
$ fscryptctl set_policy --iv-ino-lblk-32 "$KEYID" /mnt/dir
$ cat /mnt/dir/test.txt # File should now be decrypted

Tested-by: Wenjia Zhang <wenjia.zhang@oss.qualcomm.com>
Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Eric Biggers <ebiggers@kernel.org>
@harshaldev27 @sonineerajkumar
FROMLIST: dt-bindings: crypto: qcom,ice: Require power-domain and ifa…
f8afd2e 
…ce clk

Update the inline-crypto engine DT binding to reflect that power-domain and
clock-names are now mandatory. Also update the maximum number of clocks
that can be specified to two. These new fields are mandatory because ICE
needs to vote on the power domain before it attempts to vote on the core
and iface clocks to avoid clock 'stuck' issues.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-1-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: lemans: Add power-domain and iface clk fo…
c8cd148 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC
power domain and 'core' and 'iface' clocks in the ICE node for lemans.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-3-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: monaco: Add power-domain and iface clk fo…
58fb470 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node
for monaco.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-4-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: sc7180: Add power-domain and iface clk fo…
460fc01 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC
power domain and 'core' and 'iface' clocks in the ICE node for sc7180.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-5-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: kodiak: Add power-domain and iface clk fo…
1faf119 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node
for kodiak.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-6-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: sm8450: Add power-domain and iface clk fo…
657460d 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC
power domain and 'core' and 'iface' clocks in the ICE node for sm8450.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-7-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: sm8550: Add power-domain and iface clk fo…
c3b2774 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC
power domain and 'core' and 'iface' clocks in the ICE node for sm8550.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-8-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: sm8650: Add power-domain and iface clk fo…
fee54e7 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC
power domain and 'core' and 'iface' clocks in the ICE node for sm8650.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-9-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: arm64: dts: qcom: sm8750: Add power-domain and iface clk fo…
a4da184 
…r ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for it's own resources. Before accessing ICE hardware, the 'core' and
'iface' clocks must be turned on by the driver. This can only be done if
the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node
for sm8750.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-10-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@harshaldev27 @sonineerajkumar
FROMLIST: soc: qcom: ice: Add explicit power-domain and clock voting …
5c53b58 
…calls for ICE

Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver
de-coupled from the QCOM UFS driver, it should explicitly vote for it's
needed resources during probe, specifically the UFS_PHY_GDSC power-domain
and the 'core' and 'iface' clocks.
Also updated the suspend and resume callbacks to handle votes on these
resources.

Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-11-e9059776f85c@qti.qualcomm.com/
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
@kuld-sing
FROMLIST: dt-bindings: mmc: sdhci-msm: Add ICE phandle
126d327 
Starting with sc7280(kodiak), the ICE will have its own device-tree node.
So add the qcom,ice property to reference it.

To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE
register region in the SDHCI node. Older SoCs without ICE remain valid as
no additional requirement is imposed.

Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260217052526.2335759-2-neeraj.soni@oss.qualcomm.com/
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
@kuld-sing
FROMLIST: arm64: dts: qcom: kodiak: enable the inline crypto engine f…
669ef5e 
…or SDHC

Add an ICE node to kodiak SoC description and enable it by adding a
phandle to the SDHC node.

Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260217052526.2335759-3-neeraj.soni@oss.qualcomm.com/
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
@kuld-sing
FROMLIST: arm64: dts: qcom: monaco: enable the inline crypto engine f…
9160888 
…or SDHC

Add an ICE node to monaco SoC description and enable it by adding a
phandle to the SDHC node.

Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260217052526.2335759-4-neeraj.soni@oss.qualcomm.com/
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
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3 participants

@kuld-sing @dmukhopa @harshaldev27