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WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref supply #695

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WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref supply #695

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dd9d4c8
FROMLIST: dt-bindings: phy: sc8280xp-qmp-pcie: Document Glymur PCIe G…
abelvesa Dec 24, 2025
e14cf42
FROMLIST: phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen4x2 PHY
abelvesa Dec 24, 2025
4795ab1
WORKAROUND: phy: qcom: qmp-pcie: Add vdda-refgen and vdda-qref suppli…
qianyu-qcom Feb 12, 2026
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3 changes: 3 additions & 0 deletions Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
Expand Down Expand Up @@ -178,6 +179,7 @@ allOf:
compatible:
contains:
enum:
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
Expand All @@ -202,6 +204,7 @@ allOf:
compatible:
contains:
enum:
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
Expand Down
25 changes: 22 additions & 3 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
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Expand Up @@ -3226,7 +3226,7 @@ static const char * const qmp_phy_vreg_l[] = {
};

static const char * const sm8550_qmp_phy_vreg_l[] = {
"vdda-phy", "vdda-pll", "vdda-qref",
"vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", "vdda-qref","vdda-qref2",
};

/* list of resets */
Expand Down Expand Up @@ -4432,15 +4432,31 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = {

.reset_list = sdm845_pciephy_reset_l,
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.vreg_list = sm8550_qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),

.regs = pciephy_v8_50_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS_4_20,
};

static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = {
.lanes = 2,

.offsets = &qmp_pcie_offsets_v8_0,

.reset_list = sdm845_pciephy_reset_l,
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.vreg_list = sm8550_qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),

.regs = pciephy_v8_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS_4_20,
};

static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
Expand Down Expand Up @@ -5192,6 +5208,9 @@ static int qmp_pcie_probe(struct platform_device *pdev)

static const struct of_device_id qmp_pcie_of_match_table[] = {
{
.compatible = "qcom,glymur-qmp-gen4x2-pcie-phy",
.data = &glymur_qmp_gen4x2_pciephy_cfg,
}, {
.compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
.data = &glymur_qmp_gen5x4_pciephy_cfg,
}, {
Expand Down