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vcpu: Handle Intel VMX limitation for intr_shadow import #1014

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vcpu: Handle Intel VMX limitation for intr_shadow import #1014

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12 changes: 10 additions & 2 deletions lib/propolis/src/vcpu.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -971,10 +971,18 @@ pub mod migrate {

fn write(self, vcpu: &Vcpu) -> Result<()> {
vcpu.set_run_state(self.run_state, Some(self.sipi_vector))?;
vcpu.set_reg(

// Intel VMX rejects setting intr_shadow to non-zero (AMD is fine).
// This state is transient anyway, cleared after one instruction.
Comment on lines +975 to +976
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@iximeow iximeow Mar 12, 2026

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this is overly-strong, right? from the SDM:

If the VM entry is injecting, there is no blocking by STI or by MOV SS following the VM entry, regardless of the contents of the interruptability-state field.

my read is that VMX would allow the bits to be set, but they would not be heeded, hence the conservative approach of EINVAL in bhyve since the VMM will probably be (I would be for sure) surprised about the behavior in this case.

if let Err(e) = vcpu.set_reg(
vm_reg_name::VM_REG_GUEST_INTR_SHADOW,
u64::from(self.intr_shadow),
)?;
) {
if !(self.intr_shadow && e.raw_os_error() == Some(libc::EINVAL))
{
return Err(e);
}
}

let ents = [
vdi_field_entry_v1::new(
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