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    30 repositories

    • SimStm

      Public
      SimStm is a functional verification framework designed for ease of use and clear, intuitive understanding.
      VHDL
      •
      Apache License 2.0
      •2•2•6•0•Updated Apr 27, 2026Apr 27, 2026

    • livt-ram

      Public
      A small byte-addressable RAM component in Livt.
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Apr 23, 2026Apr 23, 2026

    • livt-fir-filter-migration

      Public
      This project demonstrates how to use an LLM to migrate a C/HLS design to the Livt programming language.
      C
      •
      MIT License
      •0•0•0•0•Updated Apr 23, 2026Apr 23, 2026

    • livt-uart-cli-app

      Public
      A small UART-driven command-line application in Livt.
      MIT License
      •0•0•0•0•Updated Apr 16, 2026Apr 16, 2026

    • livt-stack

      Public
      A fixed-size LIFO stack in Livt for small byte-oriented storage needs.
      MIT License
      •0•0•0•0•Updated Apr 16, 2026Apr 16, 2026

    • livt-queue

      Public
      A fixed-size FIFO queue in Livt for small byte-oriented buffering needs.
      MIT License
      •0•0•0•0•Updated Apr 13, 2026Apr 13, 2026

    • livt-uart-hello-app

      Public
      A minimal Livt application that uses the Uart package.
      MIT License
      •0•0•0•0•Updated Apr 13, 2026Apr 13, 2026

    • livt-uart

      Public
      A layered UART implementation in Livt, from low-level RX/TX blocks up to a buffered controller and a simple convenience wrapper for application code.
      MIT License
      •0•0•0•0•Updated Apr 3, 2026Apr 3, 2026

    • eccelerators-docbook

      Public
      Eccelerators docbook5 transform template
      XSLT
      •0•0•0•0•Updated Nov 18, 2025Nov 18, 2025

    • event-catcher

      Public
      EventCatcher is a reusable FPGA component that receives events from user logic and exposes them to software.
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Oct 29, 2025Oct 29, 2025

    • vhdl-eccelerators-basic-components

      Public
      Basic vhdl components for eccelerators projects
      HTML
      •
      MIT License
      •0•0•0•0•Updated Jul 15, 2025Jul 15, 2025

    • double-buffer-controller

      Public
      Double Buffer Controller is a reusable FPGA component that alternates between two buffers to provide uninterrupted data flow between hardware modules.
      MIT License
      •0•0•0•0•Updated Sep 20, 2024Sep 20, 2024

    • simple_led

      Public
      VHDL
      •0•0•0•0•Updated Aug 28, 2024Aug 28, 2024

    • vhdl-eccelerators-basic-package

      Public
      Basic eccelerators VHDLpackage
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Aug 12, 2024Aug 12, 2024

    • setup2vivado

      Public
      Transform eccelerators setup.py to vivado files
      Python
      •
      MIT License
      •0•0•0•0•Updated Apr 30, 2024Apr 30, 2024

    • setup2modelsim

      Public
      Generate ANT buildscript to run modelsim from eccelerators setup.py
      Python
      •
      MIT License
      •0•0•0•0•Updated Apr 4, 2024Apr 4, 2024

    • setup2ghdl

      Public
      Generate ANT buildscript to run ghdl from eccelerators setup.py
      Python
      •
      MIT License
      •0•0•0•0•Updated Apr 4, 2024Apr 4, 2024

    • interrupt-collector

      Public
      Interrupt Collector is a reusable FPGA component that manages multiple interrupt sources and enables parallel interrupt handling across multi-core processor sys…
      HTML
      •
      MIT License
      •0•0•0•0•Updated Apr 4, 2024Apr 4, 2024

    • interrupt-generator

      Public
      Interrupt generator as counterpart for simulation test benches and test builds of target devices
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Apr 4, 2024Apr 4, 2024

    • basic-ant-builds

      Public
      Basic ANT build.xml files
      MIT License
      •0•0•0•0•Updated Apr 4, 2024Apr 4, 2024

    • collect-fpga-build-results

      Public
      Collects junit simulation testcase and selected vivado build results as junit testcase too and merges them to a junitsuites file
      Python
      •
      MIT License
      •0•0•0•0•Updated Mar 26, 2024Mar 26, 2024

    • interrupt-dispatcher

      Public
      Dispatches consecutive interrupts to different CPU cores
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Mar 26, 2024Mar 26, 2024

    • break-docbook-program-listing

      Public
      Simple program that splits program listings in a docbook xml file.
      Python
      •
      MIT License
      •0•0•0•0•Updated Mar 26, 2024Mar 26, 2024

    • bus-join

      Public
      Join two busses to connect e.g., 2 CPUs to one bus.
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Mar 26, 2024Mar 26, 2024

    • crc-calculator

      Public
      CRC Calculator is a reusable FPGA component that computes CRC-32 checksums using the Ethernet polynomial (0x4C11DB7).
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Feb 12, 2024Feb 12, 2024

    • bus-divider

      Public
      Bus dividers as delegates generated by HxS
      JavaScript
      •
      MIT License
      •0•0•0•0•Updated Feb 2, 2024Feb 2, 2024

    • spi-controller

      Public
      SPI Controller is a reusable FPGA component that provides a Serial Peripheral Interface for communication with external SPI devices.
      VHDL
      •
      MIT License
      •0•0•0•0•Updated Feb 2, 2024Feb 2, 2024

    • usual-objects

      Public
      MIT License
      •0•0•0•0•Updated Dec 12, 2023Dec 12, 2023

    • sphinx_docbook

      Public
      Eccelerators adapted sphinx docbook builder plugin
      Python
      •0•0•0•0•Updated Jul 26, 2023Jul 26, 2023

    • sphinx-template

      Public
      Eccelerators sphinx template
      Python
      •0•0•0•0•Updated Jul 25, 2023Jul 25, 2023
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