RISC-V

Overview

This project aims to develop a microarchitecture for the RISC-V RV32I ISA and some of standard extensions for accelerating DSP and cryptography applications

Progress

• Multiplication and division units: completed
• Datapath for RV32IM: completed
• Testing: compiling correctly, errors in simulation
• Floating-Point Unit: in progress
• Vector processor implementation and cryptography cores: needs work

TODO

• Debug RV32IM datapath and controller
• Convernt multicycle design to pipelined