Open source chip verification pipeline. Learn. Verify. Tape Out.
🌐 xylonstud.io | 📖 繁體中文
demo.mp4
XylonStudio is an AI-assisted chip verification platform. Auto-generate test plans, testbenches, and coverage reports from your RTL. Open source, pluggable LLM, education-first.
Key Features:
- AI-generated verification test plans from RTL analysis
- C++ Verilator testbench generation with coverage support
- Coverage-driven iteration loop (auto-improve until target met)
- Real Verilator simulation in Docker containers
- Yosys synthesis reports (gate count, cell breakdown)
- AI Debug Assistant explains simulation failures in plain language
- Pluggable LLM (Ollama, vLLM — bring your own model)
- CLI for scripting and CI integration (
python -m agent.cli run ...) - Pipeline visualization with real-time WebSocket streaming
RTL Code
↓
Lint (Verilator)
↓
Test Plan Generation (LLM)
↓
Testbench Generation (LLM)
↓
┌─── Simulation (Verilator) ◄──┐
│ ↓ │
│ PASS? ── No ── Debug Assistant (LLM)
│ │ │
│ Yes │
│ ↓ │
│ Coverage Analysis │
│ ↓ │
│ Target met? ── No ── Improve Testbench (LLM)
│ │
│ Yes
│ ↓
├── Coverage Report
↓
Synthesis Report (Yosys, optional)
Backend:
- Python 3.11+
- FastAPI
- Async pipeline runner with step callbacks
LLM (bring your own):
- Ollama (qwen2.5-coder, deepseek-coder, etc.)
- vLLM (self-hosted)
- Any OpenAI-compatible API
EDA Tools (Docker):
- Verilator (lint, simulation, coverage)
- Yosys (synthesis)
Frontend:
- Next.js 14
- TypeScript
- Tailwind CSS
- WebSocket for real-time pipeline updates
- Python 3.11+
- Node.js 20+
- Docker (for Verilator/Yosys containers)
- Ollama or vLLM endpoint (for LLM features)
# Clone repository
git clone https://github.com/kevintseng/xylon-studio.git
cd xylon-studio
# Backend setup
cd agent
python3 -m venv venv
source venv/bin/activate
pip install -r requirements.txt
# Start API server
uvicorn agent.api.main:app --host 0.0.0.0 --port 5000
# Frontend setup (in another terminal)
cd ../web
npm install
npm run devCLI (fastest way to try it):
# Lint only
python -m agent.cli run examples/adder/adder_8bit.v
# Phase A: user-provided C++ testbench + synthesis report
python -m agent.cli run examples/adder/adder_8bit.v \
--testbench examples/adder/tb_adder_8bit.cpp \
--synthesis
# Phase B: LLM generates test plan + testbench automatically
python -m agent.cli run examples/adder/adder_8bit.v \
--llm ollama --model qwen2.5-coder:32b \
--coverage-target 0.8REST API:
# Phase A: Lint + simulate with your own testbench
curl -X POST http://localhost:5000/api/pipeline/run \
-H "Content-Type: application/json" \
-d '{
"rtl_code": "module adder(input [7:0] a, b, output [8:0] sum); assign sum = a + b; endmodule",
"testbench_code": "...",
"coverage_target": 0.80,
"synthesis_enabled": true
}'
# Phase B: LLM generates test plan + testbench automatically
curl -X POST http://localhost:5000/api/pipeline/run \
-H "Content-Type: application/json" \
-d '{
"rtl_code": "module adder(input [7:0] a, b, output [8:0] sum); assign sum = a + b; endmodule",
"coverage_target": 0.80,
"llm_config": {
"type": "ollama",
"endpoint": "http://localhost:11434",
"model": "qwen2.5-coder:32b"
}
}'| Design | Type | Tests | Line Cov | Gates (Yosys) |
|---|---|---|---|---|
| 8-bit Adder | Combinational | 25 | 100% | — |
| 8-bit Counter | Sequential | 10 | 100% | — |
| Traffic Light FSM | FSM | 9 | 79% | — |
| 16-bit Barrel Shifter | Combinational | 36 | 80% | 237 |
| RISC-V ALU | Combinational (RV32I) | 24 | 50% | 1485 |
Each example includes RTL source and a verified C++ Verilator testbench.
xylon/
├── agent/ # Backend (Python/FastAPI)
│ ├── cli.py # Command-line pipeline runner (python -m agent.cli)
│ ├── core/ # LLM provider abstraction
│ ├── pipeline/ # Pipeline runner + step functions
│ │ └── steps/ # lint, test_plan, testbench_gen, simulate, coverage,
│ │ # improve, debug_assist, synthesis
│ ├── api/ # REST + WebSocket endpoints
│ ├── sandbox/ # Docker EDA container management
│ └── tests/ # 101 unit + integration tests
├── web/ # Frontend (Next.js)
│ ├── app/ # Pages: home, design, verify, pipeline, history
│ ├── components/ # UI components
│ └── lib/ # i18n (EN + zh-TW)
├── examples/ # Example RTL designs with testbenches
└── docs/ # Design documents
cd agent
source venv/bin/activate
# Run unit tests (fast, no Docker required)
pytest agent/
# Run integration tests (requires Docker + Verilator/Yosys containers)
pytest agent/ -m integration
# Lint with ruff
ruff check agent/
# Start API server
uvicorn agent.api.main:app --reload --port 5000cd web
npm install
npm run dev| Method | Path | Description |
|---|---|---|
| POST | /api/pipeline/run |
Run verification pipeline (REST) |
| WS | /api/pipeline/ws |
Run pipeline with real-time step streaming |
| POST | /api/design/generate |
Generate RTL from description |
| POST | /api/verification/verify |
Verify RTL with testbench |
XylonStudio uses a dual-licensing model:
The core platform (this repository) is licensed under the MIT License:
- ✅ Free to use, modify, and distribute
- ✅ Commercial use allowed
- ✅ Open source with minimal requirements
See LICENSE for full terms.
Advanced enterprise features are available under a separate commercial license.
Email: hello@xylonstud.io
Contributions are welcome! Please see CONTRIBUTING.md for guidelines.
Built with: Verilator, Yosys, Ollama, FastAPI, Next.js