Added ROMDualPort's Verilog export template

[yinyue200]

1. Allow ROMDualPort components to be exported as Verilog code.
2. Optimize the Verilog export template of existing ROM components to handle the case where ROM data is 0.

[codecov-commenter]

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Codecov Report

Attention: Patch coverage is 0% with 2 lines in your changes missing coverage. Please review.

Project coverage is 56.5%. Comparing base (1204c26) to head (255c3f7).
Report is 49 commits behind head on master.

Files with missing lines	Patch %	Lines
.../main/java/de/neemann/digital/hdl/hgs/Context.java	0.0%	1 Missing and 1 partial ⚠️

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Additional details and impacted files

@@           Coverage Diff            @@
##             master   #1218   +/-   ##
========================================
  Coverage      56.5%   56.5%           
  Complexity     6579    6579           
========================================
  Files           680     680           
  Lines         35565   35567    +2     
  Branches       4802    4803    +1     
========================================
+ Hits          20113   20119    +6     
+ Misses        14242   14238    -4     
  Partials       1210    1210           

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