Draft verilog generators#122
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suarezvictor wants to merge 6 commits intoenjoy-digital:masterfrom
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ReIntegration code for simulator/Arty board here: https://github.com/suarezvictor/litex_prototypes/tree/main/gen_reintegration |
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generate verilog files for various configurations (simulation, RMII, axi-lite/wishbone), plus etherbone
NOTE: not working yet