Verilog Digital Systems — IMS & Transportation System

Two hardware modules implemented in Verilog, synthesized and tested on a Basys2 FPGA board (Xilinx toolchain).

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Part 1 — Incremental Memory System (IMS)

A memory system combining a read-only lookup memory with a writable accumulation unit, designed for applications that require continuous data updates (counters, sensor data, financial tracking).

Architecture

         systemAddr ──────────────────────┐
                                          ↓
dataIn ──────────────────────────────► [ IDS ] ──► systemOutput
                          ↑               ↑
                       romData         (CLK, mode, operation)
                          │
                     [ ROLM ]
                          ↑
                       systemAddr

Modules

ROLM — Read-Only Lookup Memory

• 8 memory locations, 8-bit values each
• 3-bit addressing (addr[2:0])
• Asynchronous — output updates immediately on address change, no clock required

IDS — Incremental Data Storage

• 8-location RAM, each 8 bits wide
• Synchronous write (triggered on positive clock edge)
• Asynchronous read
• 4 operation codes:

operation	Action
00	Increment — stores dataIn + romData
01	Decrement — stores dataIn - romData
10	Reset — clears location to 0x00
11	Preset — sets location to 0xFF

IMS — Top-level wrapper that instantiates and wires ROLM → IDS.

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Part 2 — Transportation System

A seat reservation and check-in management system for four transportation methods, implemented as a clocked FSM with priority-based warning logic.

Transportation Methods

method	Type	Total Seats	Valid Seat Range
00	Bus	16	0000–1111
01	Train	15	0000–1110
10	High-Speed Train	16	0000–1111
11	Airplane	15	0000–1110

Modes of Operation

mode	Operation	Description
00	Registration	Reserves a seat if available and not already taken
01	Check-In	Checks in a registered passenger
10	Search	Queries the current status of a specific seat

Seat State Encoding

Each seat is stored as 2 bits internally:

Bits	State
00	Empty
10	Registered
11	Checked-In

Warning Priority

When multiple conditions are met, warnings fire in this order:

Priority	Signal	Trigger
1	seatUnavailable	No seats left, or invalid seat number
2	alreadyRegistered	Seat already reserved
3	notRegistered	Seat not registered (on check-in/search)
4	alreadyCheckedIn	Passenger already checked in

FPGA Board (Basys2)

FPGA Mapping (Basys2)

Signal	Board I/O	Description
mode[1:0]	sw[1:0]	Mode selector (middle switches)
method[1:0]	sw[3:2]	Transportation method selector
seatNumber[3:0]	sw[7:4]	Seat number input
CLK	btn[0]	Clock signal (right bottom button)
seatLeft	7-seg right 2 digits	Available seats count
selectedMethod	7-seg left 2 digits	Selected transportation method
registered	led[7]	Passenger registration flag
checkInStatus	led[6]	Passenger check-in flag
alreadyRegistered	led[5]	Existing registration flag
notRegistered	led[4]	Missing registration flag
seatUnavailable	led[3]	Unavailable seats flag
alreadyCheckedIn	led[2]	Already checked-in flag

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Files

├── Lab4_1.v      ─── ROLM + IDS + Incremental_Memory_System modules
├── Lab4_2.v      ─── TransportationSystem module
├── board.webp    ─── FPGA board I/O mapping diagram
└── README.md

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Tools

• Language: Verilog (IEEE 1364)
• Simulator: Any standard Verilog simulator (ModelSim, Vivado, iVerilog)
• Synthesis: Xilinx ISE (Basys2 target)
• Timescale: 1ns / 1ps