fpga_exp0

verilog codes we made at digital lab

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
EXP0_Student		EXP0_Student
db		db
incremental_db		incremental_db
ss		ss
DE1_SOC.done		DE1_SOC.done
DE1_SOC.flow.rpt		DE1_SOC.flow.rpt
DE1_SOC.htm		DE1_SOC.htm
DE1_SOC.map.rpt		DE1_SOC.map.rpt
DE1_SOC.map.summary		DE1_SOC.map.summary
DE1_SOC.qpf		DE1_SOC.qpf
DE1_SOC.qsf		DE1_SOC.qsf
DE1_SOC.qws		DE1_SOC.qws
DE1_SOC.sdc		DE1_SOC.sdc
DE1_SOC.v		DE1_SOC.v
DE1_SOC_assignment_defaults.qdf		DE1_SOC_assignment_defaults.qdf
OurAdder.bsf		OurAdder.bsf
OurAdder.v.bak		OurAdder.v.bak
OurComplementer.bsf		OurComplementer.bsf
OurComplementer.v.bak		OurComplementer.v.bak
OurSubtractor.bdf		OurSubtractor.bdf
OurSubtractor.v.bak		OurSubtractor.v.bak
README.md		README.md
adder.pdf		adder.pdf
complement.pdf		complement.pdf
subtractor.pdf		subtractor.pdf

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