Graph UI advanced wmouse

FDP.srcs/sources_1/imports/Desktop/Mouse_Control.vhd

@@ -257,11 +257,15 @@ constant SAMPLE_RATE      : std_logic_vector(7 downto 0) := x"28";
                                                   -- (40 samples/s)
 
 -- default maximum value for the horizontal mouse position
-constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"3C0";
+--constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"3C0";
                                                       -- 1279
+constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"063";
+-- 99 MAX_X
 -- default maximum value for the vertical mouse position
-constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"280";
+--constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"280";
                                                       -- 1023
+constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"041";
+-- 65 MAX_Y
 
 -- Mouse check tick constants
 constant CHECK_PERIOD_CLOCKS   : integer := ((CHECK_PERIOD_MS*1000000)/(1000000000/SYSCLK_FREQUENCY_HZ));

FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0.xml

@@ -1536,7 +1536,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Apr 08 17:48:22 UTC 2025</spirit:value>
+            <spirit:value>Sat Apr 12 14:31:47 UTC 2025</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>

FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-// Date        : Wed Apr  9 01:48:22 2025
-// Host        : DESKTOP-DVNBCH1 running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode funcsim {C:/Uni
-//               Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v}
+// Date        : Sat Apr 12 22:31:47 2025
+// Host        : Daniel running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v
 // Design      : blk_mem_gen_0
 // Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
 //               or synthesized. This netlist cannot be used for SDF annotated simulation.

FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
--- Date        : Wed Apr  9 01:48:22 2025
--- Host        : DESKTOP-DVNBCH1 running 64-bit major release  (build 9200)
--- Command     : write_vhdl -force -mode funcsim {C:/Uni
---               Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl}
+-- Date        : Sat Apr 12 22:31:47 2025
+-- Host        : Daniel running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode funcsim
+--               C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl
 -- Design      : blk_mem_gen_0
 -- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
 --               synthesized. This netlist cannot be used for SDF annotated simulation.

FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-// Date        : Wed Apr  9 01:48:22 2025
-// Host        : DESKTOP-DVNBCH1 running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub {C:/Uni
-//               Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v}
+// Date        : Sat Apr 12 22:31:47 2025
+// Host        : Daniel running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v
 // Design      : blk_mem_gen_0
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7a35tcpg236-1

FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml

@@ -1498,11 +1498,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Apr 11 05:20:05 UTC 2025</spirit:value>
+            <spirit:value>Sat Apr 12 14:30:57 UTC 2025</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>8:1a76e1f2</spirit:value>
+            <spirit:value>8:8ad6b4c2</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1518,11 +1518,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Apr 11 05:20:05 UTC 2025</spirit:value>
+            <spirit:value>Sat Apr 12 14:30:57 UTC 2025</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>8:1a76e1f2</spirit:value>
+            <spirit:value>8:8ad6b4c2</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1536,11 +1536,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Apr 11 05:20:16 UTC 2025</spirit:value>
+            <spirit:value>Sat Apr 12 14:32:15 UTC 2025</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>8:1a76e1f2</spirit:value>
+            <spirit:value>8:8ad6b4c2</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>

FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-// Date        : Sat Mar 29 17:09:05 2025
-// Host        : DESKTOP-4JEN3JE running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode funcsim -rename_top blk_mem_gen_const -prefix
-//               blk_mem_gen_const_ blk_mem_gen_const_sim_netlist.v
+// Date        : Sat Apr 12 22:32:15 2025
+// Host        : Daniel running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v
 // Design      : blk_mem_gen_const
 // Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
 //               or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -192,6 +192,7 @@ module blk_mem_gen_const
         .web(1'b0));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) 
 module blk_mem_gen_const_blk_mem_gen_generic_cstr
    (douta,
     addra,
@@ -576,6 +577,7 @@ module blk_mem_gen_const_blk_mem_gen_generic_cstr
         .wea(wea));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_mux" *) 
 module blk_mem_gen_const_blk_mem_gen_mux
    (douta,
     p_7_out,
@@ -1412,6 +1414,7 @@ module blk_mem_gen_const_blk_mem_gen_mux
         .R(1'b0));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
 module blk_mem_gen_const_blk_mem_gen_prim_width
    (\douta[0] ,
     clka,
@@ -2263,6 +2266,7 @@ module blk_mem_gen_const_blk_mem_gen_prim_width__parameterized9
         .wea(wea));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) 
 module blk_mem_gen_const_blk_mem_gen_prim_wrapper_init
    (\douta[0] ,
     clka,
@@ -8620,6 +8624,7 @@ module blk_mem_gen_const_blk_mem_gen_prim_wrapper_init__parameterized9
         .O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_top" *) 
 module blk_mem_gen_const_blk_mem_gen_top
    (douta,
     addra,
@@ -8670,7 +8675,7 @@ endmodule
 (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) 
 (* C_WRITE_DEPTH_A = "50890" *) (* C_WRITE_DEPTH_B = "50890" *) (* C_WRITE_MODE_A = "READ_FIRST" *) 
 (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "16" *) (* C_WRITE_WIDTH_B = "16" *) 
-(* C_XDEVICEFAMILY = "artix7" *) (* downgradeipidentifiedwarnings = "yes" *) 
+(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_4_1" *) (* downgradeipidentifiedwarnings = "yes" *) 
 module blk_mem_gen_const_blk_mem_gen_v8_4_1
    (clka,
     rsta,
@@ -8904,6 +8909,7 @@ module blk_mem_gen_const_blk_mem_gen_v8_4_1
         .wea(wea));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_v8_4_1_synth" *) 
 module blk_mem_gen_const_blk_mem_gen_v8_4_1_synth
    (douta,
     addra,

FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
--- Date        : Sat Mar 29 17:09:05 2025
--- Host        : DESKTOP-4JEN3JE running 64-bit major release  (build 9200)
--- Command     : write_vhdl -force -mode funcsim -rename_top blk_mem_gen_const -prefix
---               blk_mem_gen_const_ blk_mem_gen_const_sim_netlist.vhdl
+-- Date        : Sat Apr 12 22:32:15 2025
+-- Host        : Daniel running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode funcsim
+--               C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl
 -- Design      : blk_mem_gen_const
 -- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
 --               synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -59,6 +59,8 @@ entity blk_mem_gen_const_blk_mem_gen_mux is
     \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 0 to 0 );
     \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 0 to 0 )
   );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
 end blk_mem_gen_const_blk_mem_gen_mux;
 
 architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_mux is
@@ -1005,6 +1007,8 @@ entity blk_mem_gen_const_blk_mem_gen_prim_wrapper_init is
     dina : in STD_LOGIC_VECTOR ( 0 to 0 );
     wea : in STD_LOGIC_VECTOR ( 0 to 0 )
   );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
 end blk_mem_gen_const_blk_mem_gen_prim_wrapper_init;
 
 architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_prim_wrapper_init is
@@ -7612,6 +7616,8 @@ entity blk_mem_gen_const_blk_mem_gen_prim_width is
     dina : in STD_LOGIC_VECTOR ( 0 to 0 );
     wea : in STD_LOGIC_VECTOR ( 0 to 0 )
   );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
 end blk_mem_gen_const_blk_mem_gen_prim_width;
 
 architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_prim_width is
@@ -8413,6 +8419,8 @@ entity blk_mem_gen_const_blk_mem_gen_generic_cstr is
     dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
     wea : in STD_LOGIC_VECTOR ( 0 to 0 )
   );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
 end blk_mem_gen_const_blk_mem_gen_generic_cstr;
 
 architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_generic_cstr is
@@ -9028,6 +9036,8 @@ entity blk_mem_gen_const_blk_mem_gen_top is
     dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
     wea : in STD_LOGIC_VECTOR ( 0 to 0 )
   );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_top : entity is "blk_mem_gen_top";
 end blk_mem_gen_const_blk_mem_gen_top;
 
 architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_top is
@@ -9053,6 +9063,8 @@ entity blk_mem_gen_const_blk_mem_gen_v8_4_1_synth is
     dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
     wea : in STD_LOGIC_VECTOR ( 0 to 0 )
   );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_v8_4_1_synth : entity is "blk_mem_gen_v8_4_1_synth";
 end blk_mem_gen_const_blk_mem_gen_v8_4_1_synth;
 
 architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_v8_4_1_synth is
@@ -9282,6 +9294,8 @@ entity blk_mem_gen_const_blk_mem_gen_v8_4_1 is
   attribute C_WRITE_WIDTH_B of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is 16;
   attribute C_XDEVICEFAMILY : string;
   attribute C_XDEVICEFAMILY of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "artix7";
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "blk_mem_gen_v8_4_1";
   attribute downgradeipidentifiedwarnings : string;
   attribute downgradeipidentifiedwarnings of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "yes";
 end blk_mem_gen_const_blk_mem_gen_v8_4_1;

FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-// Date        : Sat Mar 29 17:09:05 2025
-// Host        : DESKTOP-4JEN3JE running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub -rename_top blk_mem_gen_const -prefix
-//               blk_mem_gen_const_ blk_mem_gen_const_stub.v
+// Date        : Sat Apr 12 22:32:15 2025
+// Host        : Daniel running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v
 // Design      : blk_mem_gen_const
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7a35tcpg236-1

FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml

@@ -1498,11 +1498,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Apr 11 05:20:06 UTC 2025</spirit:value>
+            <spirit:value>Sat Apr 12 14:30:57 UTC 2025</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>8:2f47c7ae</spirit:value>
+            <spirit:value>8:c38ac6e6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1518,11 +1518,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Apr 11 05:20:06 UTC 2025</spirit:value>
+            <spirit:value>Sat Apr 12 14:30:57 UTC 2025</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>8:2f47c7ae</spirit:value>
+            <spirit:value>8:c38ac6e6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1536,11 +1536,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Apr 11 05:20:16 UTC 2025</spirit:value>
+            <spirit:value>Sat Apr 12 14:31:47 UTC 2025</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>8:2f47c7ae</spirit:value>
+            <spirit:value>8:c38ac6e6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>

FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-// Date        : Sat Mar 29 17:07:55 2025
-// Host        : DESKTOP-4JEN3JE running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode funcsim -rename_top blk_mem_gen_img -prefix
-//               blk_mem_gen_img_ blk_mem_gen_img_sim_netlist.v
+// Date        : Sat Apr 12 22:31:47 2025
+// Host        : Daniel running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v
 // Design      : blk_mem_gen_img
 // Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
 //               or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -198,6 +198,7 @@ module blk_mem_gen_img
         .web(1'b0));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) 
 module blk_mem_gen_img_blk_mem_gen_generic_cstr
    (doutb,
     clka,
@@ -232,6 +233,7 @@ module blk_mem_gen_img_blk_mem_gen_generic_cstr
         .wea(wea));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
 module blk_mem_gen_img_blk_mem_gen_prim_width
    (doutb,
     clka,
@@ -266,6 +268,7 @@ module blk_mem_gen_img_blk_mem_gen_prim_width
         .wea(wea));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) 
 module blk_mem_gen_img_blk_mem_gen_prim_wrapper_init
    (doutb,
     clka,
@@ -435,6 +438,7 @@ module blk_mem_gen_img_blk_mem_gen_prim_wrapper_init
         .WEBWE({1'b0,1'b0,1'b0,1'b0}));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_top" *) 
 module blk_mem_gen_img_blk_mem_gen_top
    (doutb,
     clka,
@@ -493,7 +497,7 @@ endmodule
 (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) 
 (* C_WRITE_DEPTH_A = "784" *) (* C_WRITE_DEPTH_B = "784" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) 
 (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "1" *) (* C_WRITE_WIDTH_B = "1" *) 
-(* C_XDEVICEFAMILY = "artix7" *) (* downgradeipidentifiedwarnings = "yes" *) 
+(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_4_1" *) (* downgradeipidentifiedwarnings = "yes" *) 
 module blk_mem_gen_img_blk_mem_gen_v8_4_1
    (clka,
     rsta,
@@ -689,6 +693,7 @@ module blk_mem_gen_img_blk_mem_gen_v8_4_1
         .wea(wea));
 endmodule
 
+(* ORIG_REF_NAME = "blk_mem_gen_v8_4_1_synth" *) 
 module blk_mem_gen_img_blk_mem_gen_v8_4_1_synth
    (doutb,
     clka,