GitHub - arunn2004/Arun_verilogcodes: Verilog

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
Combinational circuit		Combinational circuit
LOGIC GATES		LOGIC GATES
Sequential Circuits		Sequential Circuits
ahb_apb top bridge module.v		ahb_apb top bridge module.v
module AHB_slave_interface.v		module AHB_slave_interface.v
module APB_Controller.v		module APB_Controller.v
module SevenSegmentDisplayWithDelay.v		module SevenSegmentDisplayWithDelay.v