driver: Add network support for Xilinx boards

[DeaconescuDaniel]

Pull Request Description

Added ethernet support for xilinx boards using the XEMacPs driver, following the AMD Programming Guide.

Components:

• Standalone XEmacPs MAC driver(drivers/net/xemacps/): Includes PHY registration, autonegotiation, and init/remove, send/recv/poll functionality. Note: Zynq-7000 processors have a hardware bug that causes the RX data path to lock up under heavy traffic, requiring resets.
• LwIP integration layer(network/lwip_raw_socket/netdevs/xemacps/): Integration layer for LwIP that calls the driver code, similar to the adin1110 driver
• LwIP raw socket updates (network/lwip_raw_socket/lwip_socket.c): removed dependency on adin1110 driver, updated heap allocations, removed unused variables.
• Project examples (projects/xilinx_lwip/) : an LwIP TCP echo server and an IIO server over ethernet.
• README file detailing build commands, pre-requisites and usages

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the Coding style guidelines
• I have complied with the Submission Checklist
• I have performed a self-review of the changes
• I have commented my code, at least hard-to-understand parts
• I have build all projects affected by the changes in this PR
• I have tested in hardware affected projects, at the relevant boards
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe etc), if applies

[CiprianRegus]

Do we require 1 MB of DMA buffer memory to reach the full bandwidth of the MAC? There may be cases in which we can poll and receive data more often, so then we can decrease the size of this buffer. I think we can define a macro like this, that also allows the user to configure the buffer size at compile time.

#ifndef XEMACPS_BD_SPACE_SIZE
#define XEMACPS_BD_SPACE_SIZE 0x100000
#endif

static uint8_t bd_space[XEMACPS_BD_SPACE_SIZE] ...

[DeaconescuDaniel]

The cortex-a9 limits the Xil_SetTlbAttributes function to only work with 1MB sections, it would be a good idea for portability, if the bsp supports higher granularity, but we are forced to use 1MB for this processor.
Source: Cortex A9 BSP

/************************** Constant Definitions *****************************/
#define     ARM_AR_MEM_TTB_SECT_SIZE               1024*1024
#define     ARM_AR_MEM_TTB_SECT_SIZE_MASK          (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
/************************** Variable Definitions *****************************/

extern u32 MMUTable;

/************************** Function Prototypes ******************************/

/*****************************************************************************/
/**
* @brief	This function sets the memory attributes for a section covering 1MB
*			of memory in the translation table.
*
* @param	Addr: 32-bit address for which memory attributes need to be set.
* @param	attrib: Attribute for the given memory region. xil_mmu.h contains
*			definitions of commonly used memory attributes which can be
*			utilized for this function.
*
*
* @return	None.
*
* @note		The MMU or D-cache does not need to be disabled before changing a
*			translation table entry.
*
******************************************************************************/
void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
{
	u32 *ptr;
	u32 section;

	section = Addr / 0x100000U;

[CiprianRegus]

You can use the no_os_round_up() macro instead of manually aligning: https://github.com/analogdevicesinc/no-OS/blob/main/include/no_os_util.h#L78

[DeaconescuDaniel]

Fixed, i changed it to no_os_align, it was the same macro

[CiprianRegus]

Nitpick, but the type can be uint8_t, since you can only have 32 PHYs on an MDIO bus.

[DeaconescuDaniel]

Fixed

[CiprianRegus]

Do you need to read the status register twice?

[DeaconescuDaniel]

Usually the bmsr is a latch low register, which means we need to read twice to get the updated value, but in a loop it doesn't matter since we read again on the next iteration anyway(this section was removed in the latest commit)

[CiprianRegus]

This driver will fail if the link is not up during the xemacps_init() call, right? Having the PHY link up should't be a requirement for a MAC driver to register properly. What can be done instead is to periodically verify the status of the link (e.g Linux does this once per second) and store it somewhere in struct xemacps_desc. Since there is a poll function, I think we can verify the PHY link there. Then, frame RX/TX operation should only be done if the link state is up.

[DeaconescuDaniel]

You're right, i moved the phy polling to the poll function, this way it supports connects and disconnects and we don't busy wait for the connection

[CiprianRegus]

I think this pull request looks good. One thing we can maybe change is to convert the sample project from being specific to the Cora Z7 to an example of using the Ethernet driver for the Xilinx platform. This way, we can add support for other Xilinx boards as well.

[DeaconescuDaniel]

You're right, i moved the projects to the xilinx_lwip folder, and added support for defining the mdio address, so that for a different board we can just change the address and have it work. (I have not yet tested on other boards, but i think that's all we have to do for compatibility).
I also found a bug while doing this, if we use a non existent mdio address, the bmcr returns 0xffff, which sets the bit for 1000mbps, making the driver think there is a link when there isn't one, it worked by coincidence, but now it exits correctly.