Static CMOS Logic Gates

A collection of LTspice schematic files demonstrating fundamental static CMOS logic gate designs.

Overview

This project contains LTspice simulation files for basic CMOS logic gates implemented using static CMOS design methodology. These schematics are suitable for educational purposes, design verification, and circuit analysis.

Project Contents

File	Description
AND.asc	2-input AND gate
NAND.asc	2-input NAND gate
NOR.asc	2-input NOR gate
OR.asc	2-input OR gate
XOR.asc	2-input XOR gate
XNOR.asc	2-input XNOR gate

Requirements

• LTspice (version 17.0 or later) — Download from Analog Devices

Getting Started

1. Install LTspice on your system
2. Open LTspice
3. Navigate to this project folder and open any .asc file
4. Click the Run button (or press Ctrl+R) to simulate the circuit
5. Use the probe tool to inspect node voltages and currents

Simulation Tips

• Edit Simulation Parameters: Double-click the .tran or simulation command in the schematic to adjust runtime and step size
• View Waveforms: Click on nodes to plot voltages; right-click on component symbols to display currents
• Export Data: Use File → Export to save simulation results for external analysis

Design Notes

• These designs follow standard static CMOS topology with pull-up (PMOS) and pull-down (NMOS) networks
• Device sizing is minimal; adjust W/L ratios based on specific performance requirements (speed, power, area)
• Verify timing and power characteristics for your target technology node

Author

Shahrear Hossain Shawon Algo science Lab

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