Add beginner-friendly RTL docs and VS Code workflows

[Xuefei-Zhang]

Summary

• annotate the SystemVerilog source files to make the RTL easier for beginners to read alongside the code
• add per-module learning docs and repository analysis chapters with Mermaid diagrams
• add VS Code tasks and launch settings for module compilation, full tests, and log inspection

Test Plan

• make test_matadd
• make test_matmul