[mlir][dxsa] Add dcl_tessellator_partitioning instruction

mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td

@@ -112,6 +112,28 @@ def DXSA_OutputPrimitiveTopologyAttr :
   let assemblyFormat = "$value";
 }
 
+def DXSA_TessellatorPartitioningMode_Integer        : I32EnumAttrCase<"partitioning_integer",         1>;
+def DXSA_TessellatorPartitioningMode_Pow2           : I32EnumAttrCase<"partitioning_pow2",            2>;
+def DXSA_TessellatorPartitioningMode_FractionalOdd  : I32EnumAttrCase<"partitioning_fractional_odd",  3>;
+def DXSA_TessellatorPartitioningMode_FractionalEven : I32EnumAttrCase<"partitioning_fractional_even", 4>;
+
+def DXSA_TessellatorPartitioningMode : I32EnumAttr<
+    "TessellatorPartitioningMode", "tessellator partitioning mode", [
+      DXSA_TessellatorPartitioningMode_Integer,
+      DXSA_TessellatorPartitioningMode_Pow2,
+      DXSA_TessellatorPartitioningMode_FractionalOdd,
+      DXSA_TessellatorPartitioningMode_FractionalEven
+    ]> {
+  let cppNamespace = "::mlir::dxsa";
+  let genSpecializedAttr = 0;
+}
+
+def DXSA_TessellatorPartitioningModeAttr :
+    EnumAttr<DXSADialect, DXSA_TessellatorPartitioningMode,
+             "tessellator_partitioning_mode"> {
+  let assemblyFormat = "$value";
+}
+
 //===----------------------------------------------------------------------===//
 // DXSA op definitions
 //===----------------------------------------------------------------------===//
@@ -307,4 +329,21 @@ def DXSA_DclOutputTopology : DXSA_Op<"dcl_output_topology"> {
   let assemblyFormat = "$topology attr-dict";
 }
 
+def DXSA_DclTessellatorPartitioning
+    : DXSA_Op<"dcl_tessellator_partitioning"> {
+  let summary = "declares the tessellator partitioning mode";
+  let description = [{
+    The `dxsa.dcl_tessellator_partitioning` operation declares the
+    tessellator partitioning mode in a Hull Shader declaration section.
+
+    Example:
+
+    ```mlir
+    dxsa.dcl_tessellator_partitioning partitioning_integer
+    ```
+  }];
+  let arguments = (ins DXSA_TessellatorPartitioningModeAttr:$partitioningMode);
+  let assemblyFormat = "$partitioningMode attr-dict";
+}
+
 #endif // DXSA_OPS

mlir/lib/Target/DXSA/BinaryParser.cpp

@@ -553,6 +553,14 @@ class DXBuilder {
     return dxsa::DclOutputTopology::create(builder, loc, outputTopologyAttr);
   }
 
+  Instruction buildDclTessellatorPartitioning(
+      dxsa::TessellatorPartitioningMode partitioningMode, Location loc) {
+    auto partitioningModeAttr = dxsa::TessellatorPartitioningModeAttr::get(
+        builder.getContext(), partitioningMode);
+    return dxsa::DclTessellatorPartitioning::create(builder, loc,
+                                                    partitioningModeAttr);
+  }
+
 private:
   MLIRContext *context;
   ModuleOp module;
@@ -949,6 +957,17 @@ class Parser {
     return builder.buildDclOutputTopology(*outputTopology, loc);
   }
 
+  FailureOr<Instruction> parseDclTessellatorPartitioning(uint32_t opcodeToken,
+                                                         Location loc) {
+    auto rawPartitioningMode = DECODE_D3D11_SB_TESS_PARTITIONING(opcodeToken);
+    auto partitioningMode =
+        dxsa::symbolizeTessellatorPartitioningMode(rawPartitioningMode);
+    if (!partitioningMode)
+      return emitError(loc, "unknown tessellator partitioning mode: ")
+             << rawPartitioningMode;
+    return builder.buildDclTessellatorPartitioning(*partitioningMode, loc);
+  }
+
   OptionalParseResult parseDclInstruction(uint32_t opcodeToken, Location loc,
                                           Instruction &out) {
     FailureOr<Instruction> result;
@@ -971,6 +990,9 @@ class Parser {
     case D3D11_SB_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE:
       result = parseDclTessellatorOutputPrimitive(opcodeToken, loc);
       break;
+    case D3D11_SB_OPCODE_DCL_TESS_PARTITIONING:
+      result = parseDclTessellatorPartitioning(opcodeToken, loc);
+      break;
     case D3D10_SB_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY:
       result = parseDclOutputTopology(opcodeToken, loc);
       break;

mlir/test/Target/DXSA/dcl_tessellator_partitioning.mlir

@@ -0,0 +1,8 @@
+// RUN: mlir-translate --import-dxsa-bin %S/inputs/dcl_tessellator_partitioning.bin | FileCheck %s
+
+// CHECK:      module {
+// CHECK-NEXT:   dxsa.dcl_tessellator_partitioning partitioning_integer
+// CHECK-NEXT:   dxsa.dcl_tessellator_partitioning partitioning_pow2
+// CHECK-NEXT:   dxsa.dcl_tessellator_partitioning partitioning_fractional_odd
+// CHECK-NEXT:   dxsa.dcl_tessellator_partitioning partitioning_fractional_even
+// CHECK-NEXT: }