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RISC-V-Pipelined-Core
RISC-V-Pipelined-Core PublicA 5-stage pipelined RV32I RISC-V processor in Verilog, verified in Vivado. Features a robust hazard unit with data forwarding, load-use stalling, and pipeline flush mechanisms.
Verilog
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CMOS-Inverter-Design-using-SKY130-PDK
CMOS-Inverter-Design-using-SKY130-PDK PublicA fully custom CMOS inverter designed using SKY130 open-source PDK, covering the schematic-to-layout flow. The design uses Xschem for schematic capture, Magic VLSI for layout, and ngspice for DC, t…
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