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UVM_Machine

This repository provides a framework for generating UVM testbenches using Large Language Models (LLM). It streamlines the process of creating testbenches and enhancing test stimuli through templates and configuration - driven workflows.
Due to confidentiality agreements associated with our RTL designs, only a subset of the benchmark cases is open-sourced in this repository. For more advanced features and full capabilities, please refer to Integration.

Key Components

  1. API for LLM Interaction

    • An API is required to communicate with the LLM.
    • Note: The API key has been removed from this repository. Users must add their own API key before use.
    • Due to potential performance degradation ("model drift" or reduced reasoning quality), we strongly recommend using GPT-4o or more advanced models (i.e., stronger models) for better generation quality and stability.
  2. Core Scripts

    • main_control.sh: Primary launch script (recommended to use the two - step workflow below).
    • Two-step workflow:
      1. run initial_tb.sh to build the initial UVM testbench.
      2. run increase_seq.sh to augment test stimuli with additional sequences.
  3. Directory Structure

    • auto_xxx/: Contains Python files for generating individual components and their corresponding LLM prompts.
    • fix_component_code/: Scripts for error checking and code correction in generated components.
    • module/: Open - source benchmark suite (will be continuously updated with new designs).
    • module_info.json: Configuration file where users specify the RTL code to test and API details.
  4. About Subscriber & Reference Model

    • Subscriber and Reference Model (ref_model) generation are not included. Maybe I will present detailed generation methodology in other work.

Getting Started

  1. Confige API Key

    • Add your LLM API key to the appropriate location in the scripts (details in the component generation files).
  2. Set Up RTL Configuration

    • Edit module_info. json to include the path and details of the RTL code you want to test.
  3. Component-wise Generation

    • You can generate components step by step.
    • Please refer to:
       ./initial_tb.sh (Line 44-58)
    • These lines define the sequential generation of each UVM component. Running them individually allows better control and debugging.
  4. Try Full Generation

    • Step 1: UVM-TB Gen You can still try to generate the full testbench in one step:

       ./initial_tb.sh
      • However, if it fails, do not worry — this is usually caused by LLM hallucinations or partial generation errors. Identify the failed component(s). Re-run the failed components individually, starting from the first failed one. Example
        • Ⅰ If driver (Line 50) and scoreboard (Line 54) both fail ————You should fix and re-run driver first, then scoreboard.
        • Ⅱ After fixing components: Navigate to the simulation directory, then re-run.
           cd DUT_Name/sim/
    • Step 2: Enhance test stimuli

      ./increase_seq.sh

    Key Reminder: No need to panic — failures are expected in some cases. Always re-run components in dependency order.

Integration

This repository is aligned with the content presented in our paper. We are continuously extending this work with additional features and capabilities, which are not fully open-sourced here.
If you would like to experience the system from an end-user perspective, you are welcome to explore its integration in ChatDV as a tool:
https://www.nctieda.com/CHATDV.html

Appendix

  • This work has been accepted by ICCAD 2025. DOI: 10.1109/ICCAD66269.2025.11240679 If you find this project helpful, please consider citing our paper. We sincerely appreciate your support.

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