GitHub - Preethigrace-7/RTL-TO-GDSII-FLOW-OF-RISC_V-32-BIT-PROCESSOR: Build up myself with extendable knowledge from Fundamentals of VLSI to Chip Tapeout. Worked on RISCV 32bit processor from RTL to GDSII flow with specified Industry standard constraints using Open source tool Openlane.

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Name		Name	Last commit message	Last commit date
Latest commit History 58 Commits
Counter project.pdf		Counter project.pdf
LOL TASK.pdf		LOL TASK.pdf
PREETHI_GRACE_g3_integrated_vlsi.md		PREETHI_GRACE_g3_integrated_vlsi.md
Preethi grace_G3_integrated_VLSI_Project report .pdf		Preethi grace_G3_integrated_VLSI_Project report .pdf
TCL TASK.pdf		TCL TASK.pdf

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Build up myself with extendable knowledge from Fundamentals of VLSI to Chip Tapeout. Worked on RISCV 32bit processor from RTL to GDSII flow with specified Industry standard constraints using Open source tool Openlane.

open-source riscv32 physical-design tcl-script openlane-flow rtltogds2