ECE 260A Project: ASIC Adder Design

This repository contains the SystemVerilog implementation and analysis of various adder designs for an ASIC environment. The primary goal is to design an efficient 4-input adder that sums four consecutive values of a serial input, effectively implementing a 4-tap FIR filter structure.

Project Overview

The project explores different adder architectures to optimize for power, area, and delay. The designs are targeted for implementation on Intel (Altera) FPGAs using Quartus Prime, but the principles apply to general ASIC design.

Designs

1. Base Design (Fig 11.42)

• File: fir4c_fig11_42.sv
• Description: This module implements a 4-input Carry Save Adder (CSA) tree followed by a final Carry Propagate Adder (CPA). It is based on Figure 11.42 from the Weste & Harris "CMOS VLSI Design" textbook.
• Structure:
  • Input registers for 4 taps (ar, br, cr, dr).
  • Two stages of Carry Save Adders (csa4 and csa5).
  • Final vector addition.

2. Hybrid CSA with Brent-Kung Adder (v1 & v2)

This design replaces the generic final adder with a hybrid approach using a Brent-Kung parallel prefix adder to improve timing performance. There are two versions of this implementation:

Version 1: Optimized Hybrid (File: hybrid_csa_bk.sv)

• Strategy: Uses a 16-bit Brent-Kung adder for the lower 16 bits (the largest power of 2 fitting within the 18-bit result).
• Upper Bits: The upper 2 bits (MSBs) are calculated using discrete Full Adder logic, taking the carry-out from the Brent-Kung adder.
• Goal: Optimizes area and power by using the parallel prefix structure only where it fits naturally, handling the "overflow" bits separately.

Version 2: Full Width Extension (File: Quartus_hybrid_csa_bk_v2/hybrid_csa_bk_v2.sv)

• Strategy: Extends the 18-bit operands to the next power of 2 (32 bits) and uses a 32-bit Brent-Kung adder for the entire addition.

• Upper Bits: Handled implicitly by the larger adder structure.

• Goal: Prioritizes design regularity and simplicity by using a uniform adder structure for the entire width, at the potential cost of using a larger adder than strictly necessary (though synthesis tools may optimize unused paths).

• Helper Module: bka.sv (Brent-Kung Adder implementation).

• Schematic:

  (Note: Schematic visualization of the Hybrid CSA architecture)

3. Ripple Carry Adder (RCA)

• File: fir4rca_u.sv
• Description: A baseline implementation using simple Ripple Carry Adders for comparison.

Repository Structure

• assignment_itself/: Contains the lab assignment documents and initial template files.
• Quartus_fig11_42/: Quartus project directory for the base Fig 11.42 design.
• Quartus_hybrid_csa_bk/: Quartus project directory for the Hybrid CSA design.
• Quartus_rca/: Quartus project directory for the RCA design.
• test_benches/: Simulation testbenches (e.g., project_tb2_u.sv) to verify the correctness of the designs.
• *.sv: Root directory contains the main SystemVerilog source files for easy access.

Tools Used

• Language: SystemVerilog
• Synthesis/Implementation: Intel Quartus Prime
• Simulation: ModelSim / QuestaSim

License

See LICENSE file.