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sync: 2026/5/18 weekly documentation update#15

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@cursor cursor Bot commented May 18, 2026

Documentation Sync Update

This PR adds comprehensive documentation for recent Buckyball architecture and toolchain changes.

New Documentation

English (content/en/)

  • Architecture/Cache Hierarchy and Private Data Cache.md - New document covering the private dcache redesign, inclusive L2 cache configuration, software-managed coherency model, and cache performance considerations
  • ToolChain Guide/System Control Unit.md - New document for the global multi-hart SCU subsystem, addressing hart-based UART, exit, and barrier functionality
  • Tutorial/Embench Benchmark Suite.md - New document providing comprehensive guidance on building, running, and interpreting results from the Embench benchmark suite

Chinese (content/zh/)

  • Architecture/Cache Hierarchy and Private Data Cache.md - Chinese translation
  • ToolChain Guide/System Control Unit.md - Chinese translation
  • Tutorial/Embench Benchmark Suite.md - Chinese translation

Updates to Existing Documentation

  • Architecture/Goban Multi-Core Architecture.md (both EN and ZH) - Updated configuration variants section to document new Goban sizes (1t4c, 4t16c, 8t8c) and clarify their specifications

Buckyball Code Areas Covered

  • Cache Architecture: arch/src/main/scala/framework/system/tile/BBTile.scala (recent dcache redesign commit a368d0e)
  • SCU Subsystem: arch/src/main/scala/sims/scu/SCU.scala (multi-hart refactor commit 45d41dd)
  • Configuration System: arch/src/main/scala/examples/goban/ (new configs in commits 2cf12b9, a28f742)
  • Workload Integration: bb-tests/workloads/src/CTest/toy/embench/ (added in commit 3512a9c)

Key Knowledge Gaps Addressed

  1. Cache Coherency Model: Documented the shift from hardware-managed to software-managed coherency when private L2 caches are enabled
  2. Multi-Hart Synchronization: Explained global SCU semantics vs per-tile BarrierUnit semantics
  3. Configuration Scalability: Documented new Goban configuration sizes enabling systems up to 64 cores
  4. Workload Benchmarking: Provided complete guidance for Embench benchmark suite integration and usage

Both English and Chinese documentation versions maintained in parallel with consistent structure and coverage.

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Co-authored-by: Shiroha <whmio0115@gmail.com>
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