FW: Buffer Reset and other minor fixes

[richnou]

This PR adds a couple minor fixes and improves to FW:

• Fix FPGA FIFO Buffer can contain 4-6 "stuck" bytes after seeing "Wrong" frames #31 by adding Reset bit in Readout control register. It resets the buffer, effectively flushing all bytes. Not used by default
• During Testbeam with Desy, we noticed it would be useful while using an external trigger unit to only reset the FPGA Timestamp at the start of a measurement run, but keep the FPGA Timestamp counter update at each count instead of after each trigger input. This is done now, if the TLU Mode of the FPGA timestamp is disabled, a positive pulse on the t0 input will still reset the counter.
• Other commits are minor improvements to scripts and helpers to analyse data coming from astropix, like the force interrupt control bit which makes autoread always on (one can quickly check idle bytes counter in this mode for example).

A test bit file for CMOD is available here: https://kit-adl.web.cern.ch/astep-fw/dev_richard/releases/