VHDL Labs

This repository contains my VHDL lab codes completed during the course.
Each lab demonstrates key digital design concepts using VHDL, including simulation and implementation.

Structure

• Labs 1-4:
  VHDL source files (.txt) along with testbenches where needed.

• Labs 5 and onward:
  Full project folders created using Xilinx ISE.
  You can directly open these projects in ISE, build, simulate, and see that they work correctly without needing to set up the project manually.

License

This project is licensed under the MIT License.
Feel free to use, modify, and share it!