Add alpha support for 9.7 data processing intrinsics#428
Add alpha support for 9.7 data processing intrinsics#428rockdreamer wants to merge 8 commits intoARM-software:mainfrom
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This change adds - AdvSIMD dot intrinsics available under FEAT_F16F32DOT - SVE dot intrinsics available under either FEAT_SVE2p3 || FEAT_SME2p3
This change adds - AdvSIMD intrinsics based on FMMLA available under FEAT_F16F32MM and FEAT_F16MM - SVE intrinsics available under either FEAT_F16MM and FEAT_SVE_B16MM
This change adds support for the svluti6 operations under FEAT_SVE2p3 and FEAT_SME2p3.
This change adds support for the svaddqp, svaddsubp and svsubp operations under FEAT_SVE2p3 and FEAT_SME2p3.
This change adds support for the svcvt* operations under FEAT_SVE2p3 and FEAT_SME2p3.
This change adds support for the svaba operations under FEAT_SVE2p3 and FEAT_SME2p3.
This change adds support for new svqshrn, svqshrun operations under FEAT_SVE2p3 and FEAT_SME2p3.
| // Variants are also available for | ||
| // _s32[_s16], _s64[_s32], | ||
| // _u16[_u8], _u32[_u16], _u64[_u32]. | ||
| svint16_t svaba_s16[_s8](svint16_t zda, svint8_t zn, svint8_t zm); |
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In other widening intrinsics we include l in the intrinsic name, so this should be svabal ?
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Adding to the previous comment, the current svaba* intrinsics have the naming scheme like [_s16] or [_n_s16] and don't include the second type (same in case of svaba but for widening intrinsics the half type).
Should this follow that as well?
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@georges-arm indeed, a look at other svaba intrinsics gives me svabablb and svabalt.
There's also svcvtl from recent sme. I think the reason I used _s16[_s8] is that svcvtl is a unary conversion which does not alter the first argument, so it needs a disambiguator for the return type. On more careful thought, this is not necessary as we do pass zda.
I guess the reason I didn't go for a version with a final l is that I've been asking myself: what if we get an _s32_s8 version in the future?
We could do svint16_t svabal[_s16_s8](svint16_t zda, svint8_t zn, svint8_t zm); and that would allow us to make more combinations.
Or maybe I'm overthinking is and svint16_t svabal[_s16](svint16_t zda, svint8_t zn, svint8_t zm); is good enough and if we need more we can always make a svaball.
I'm happy either way, do you have a preference? :)
The question I might add is: do we want to add a scalar version? For example svint16_t svabal[_n_s16](svint16_t zda, svint8_t zn, int8_t zm);. The reason I can see is that it would make these intrinsics have the same "shape" as svabalb, svabalt, svmlalb etc. It would have to be synthesized, and we do this for svmlalb for example. I'm leaning towards this.
@abhishek-kaushik22 this text is lost in the vastness of acle.md "In a vector operation, the disambiguator _n indicates that the final operand is a scalar rather than a vector.".
So if we add the scalar version, you're looking at a ternary_long_opt_n in gcc shape parlance, otherwise I think you'll have to create a new shape.
…tions Add the following new clang intrinsics based on the ACLE specification ARM-software/acle#428 (Add alpha support for 9.7 data processing intrinsics) Multi-vector saturating rounding shift right narrow and interleave instructions - SQRSHRN - svint8_t svqrshrn_s8(svint16x2_t, uint64_t) / svint8_t svqrshrn_n_s8_s16_x2(svint16x2_t, uint64_t) - UQRSHRN - svuint8_t svqrshrn_u8(svuint16x2_t, uint64_t) / svuint8_t svqrshrn_n_u8_u16_x2(svuint16x2_t, uint64_t) - SQRSHRUN - svuint8_t svqrshrun_u8(svint16x2_t, uint64_t) / svuint8_t svqrshrun_n_u8_s16_x2(svint16x2_t, uint64_t) Multi-vector saturating shift right narrow and interleave - SQSHRN - svint8_t svqshrn_s8(svint16x2_t, uint64_t) / svint8_t svqshrn_n_s8_s16_x2(svint16x2_t, uint64_t) - svint16_t svqshrn_s16(svint32x2_t, uint64_t) / svint16_t svqshrn_n_s16_s32_x2(svint32x2_t, uint64_t) - UQSHRN - svuint8_t svqshrn_u8(svuint16x2_t, uint64_t) / svuint8_t svqshrn_n_u8_u16_x2(svuint16x2_t, uint64_t) - svuint16_t svqshrn_u16(svuint32x2_t, uint64_t) / svuint16_t svqshrn_n_u16_u32_x2(svuint32x2_t, uint64_t) - SQSHRUN - svuint8_t svqshrun_u8(svint16x2_t, uint64_t) / svuint8_t svqshrun_n_u8_s16_x2(svint16x2_t, uint64_t) - svuint16_t svqshrun_u16(svint32x2_t, uint64_t) / svuint16_t svqshrun_n_u16_s32_x2(svint32x2_t, uint64_t)
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name: Add alpha support for 9.7 data processing intrinsics
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This change adds intrinsics for the following architectural features:
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