In the Jetson Orin Nano, the CPU is a Cortex A78AE with a 3-level cache structure. This is the first time we have encountered this cache structure on a development board for hvisor migration. In order to achieve compatibility, we need to implement a clearing logic for caches of any level.
In the Jetson Orin Nano, the CPU is a Cortex A78AE with a 3-level cache structure. This is the first time we have encountered this cache structure on a development board for hvisor migration. In order to achieve compatibility, we need to implement a clearing logic for caches of any level.