chore: update README.md

Author: syenpark

README.md

@@ -2,50 +2,62 @@
 
 Brush up on C++ personally to be a real-time engineer in AI era. For fundamental jargon you must know, please visit [jargon.md](./docs/jargon.md).
 
-## Battlefield
+Contents
 
-```shell
-                    ┌──────────────────────────────┐
-                    │            CPU               │
-                    │                              │
-                    │  ┌──────── Core 0 ────────┐  │ Core: Executes instructions
-                    │  │ Registers (R0..Rn)     │  │    Register: Fastest storage
-                    │  │ L1 Cache (32KB)        │  │              Instructions operate
-                    │  └────────────────────────┘  │    L1 Cache: Hot variables should live here
-                    │                              │
-                    │  ┌──────── Core 1 ────────┐  │
-                    │  │ Registers (R0..Rn)     │  │
-                    │  │ L1 Cache (32KB)        │  │
-                    │  └────────────────────────┘  │
-                    │                              │
-                    │        Shared L2 Cache       │ L2 Cache: Bigger and slower than L1
-                    │          (per-core / small)  │
-                    │                              │
-                    │  ┌────────────────────────┐  │
-                    │  │        L3 Cache        │  │ L3 Cache: Shared across cores
-                    │  │   (Shared, MBs)        │  │           Bigger and slower than L2
-                    │  └────────────────────────┘  │
-                    └──────────────┬───────────────┘
-                                   │
-                          Local Memory Controller
-                                   │
-                ┌──────────────────┴──────────────────┐
-                │                                     │
-          RAM (NUMA Node 0)                     RAM (NUMA Node 1)
-           ~80ns latency                         ~150ns latency
-```
+[Battlefield](#battlefield)
+[Topics](#topics)
+[Allocators & Cache Behavior (Day 05)](#allocators--cache-behavior-day-05)
+[Practical Application](#practical-application)
 
-How latency can grow...
+## Battlefield
 
-```shell
-Instruction →
-    uses Registers →
-        if miss → L1 →
-            miss → L2 →
-                miss → L3 →
-                    miss → RAM (NUMA local?) →
-                        miss → RAM (NUMA remote)
-```
+    <details>
+    <summary> Click to expand/collapse </summary>
+
+    ```shell
+                        ┌──────────────────────────────┐
+                        │            CPU               │
+                        │                              │
+                        │  ┌──────── Core 0 ────────┐  │ Core: Executes instructions
+                        │  │ Registers (R0..Rn)     │  │    Register: Fastest storage
+                        │  │ L1 Cache (32KB)        │  │              Instructions operate
+                        │  └────────────────────────┘  │    L1 Cache: Hot variables should live here
+                        │                              │
+                        │  ┌──────── Core 1 ────────┐  │
+                        │  │ Registers (R0..Rn)     │  │
+                        │  │ L1 Cache (32KB)        │  │
+                        │  └────────────────────────┘  │
+                        │                              │
+                        │        Shared L2 Cache       │ L2 Cache: Bigger and slower than L1
+                        │          (per-core / small)  │
+                        │                              │
+                        │  ┌────────────────────────┐  │
+                        │  │        L3 Cache        │  │ L3 Cache: Shared across cores
+                        │  │   (Shared, MBs)        │  │           Bigger and slower than L2
+                        │  └────────────────────────┘  │
+                        └──────────────┬───────────────┘
+                                    │
+                            Local Memory Controller
+                                    │
+                    ┌──────────────────┴──────────────────┐
+                    │                                     │
+            RAM (NUMA Node 0)                     RAM (NUMA Node 1)
+            ~80ns latency                         ~150ns latency
+    ```
+
+    How latency can grow...
+
+    ```shell
+    Instruction →
+        uses Registers →
+            if miss → L1 →
+                miss → L2 →
+                    miss → L3 →
+                        miss → RAM (NUMA local?) →
+                            miss → RAM (NUMA remote)
+    ```
+
+    </details>
 
 ## Topics
 
@@ -96,20 +108,22 @@ If your struct is poorly laid out:
     - You evict useful data
     - Latency explodes
 
-```cpp
-struct Bad {
-    bool flag;
-    double price;
-    bool active;
-}
-```
-
-```cpp
-struct Good {
-    double price;
-    bool flag;
-    bool active;
-}
-```
+    ```cpp
+    struct Bad {
+        bool flag;
+        double price;
+        bool active;
+    }
+    ```
+
+    ```cpp
+    struct Good {
+        double price;
+        bool flag;
+        bool active;
+    }
+    ```
 
 Group hot data together.
+
+## Practical Application

src/python/_cli.py

@@ -69,4 +69,5 @@ def main(
 
         return
 
+    # Run the default simulation
     run_simulation(config_data["yolo"]["fps"])