While_Compiler/extraTest2.ass at master · sfeng96/While_Compiler · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
XOR R0,R0,R0
ADDI R37,R0,1
BEQZ R37,L2
BLTZ R37,L2
BNEZ R37,L1
L1:
WRS 0
JMP L3
L2:
WRS 5
L3:
WRS 11
ADDI R37,R0,1
BEQZ R37,L5
BLTZ R37,L5
BNEZ R37,L4
L4:
WRS 0
JMP L6
L5:
WRS 5
L6:
WRS 13
MOVIR R36,3.5
ADDI R37,R0,2
ITOR R37,R37
SUBR R15,R36,R37
ADD R37,R15,R0
BEQZR R37,L8
BLTZR R37,L8
BNEZR R37,L7
L7:
WRS 0
JMP L9
L8:
WRS 5
L9:
WRS 15
ADDI R36,R0,23
ADDI R37,R0,2
SUB R15,R36,R37
ADD R37,R15,R0
BEQZ R37,L11
BLTZ R37,L11
BNEZ R37,L10
L10:
WRS 0
JMP L12
L11:
WRS 5
L12:
WRS 17
MOVIR R36,1.1
MOVIR R37,3.5
SUBR R15,R36,R37
ADD R37,R15,R0
BEQZR R37,L14
BLTZR R37,L14
BNEZR R37,L13
L13:
WRS 0
JMP L15
L14:
WRS 5
L15:
WRS 19
ADDI R36,R0,2
MOVIR R37,3.5
ITOR R36,R36
SUBR R15,R36,R37
ITOR R16,R0
ADDR R37,R15,R16
BEQZR R37,L17
BLTZR R37,L17
BNEZR R37,L16
L16:
WRS 0
JMP L18
L17:
WRS 5
L18:
WRS 21
ADDI R36,R0,2
ADDI R37,R0,23
SUB R15,R36,R37
ADD R37,R15,R0
BEQZ R37,L20
BLTZ R37,L20
BNEZ R37,L19
L19:
WRS 0
JMP L21
L20:
WRS 5
L21:
WRS 23
MOVIR R36,3.5
MOVIR R37,1.1
SUBR R15,R36,R37
ITOR R16,R0
ADDR R37,R15,R16
BEQZR R37,L23
BLTZR R37,L23
BNEZR R37,L22
L22:
WRS 0
JMP L24
L23:
WRS 5
L24:
WRS 25
ADDI R36,R0,2
MOVIR R37,3.5
ITOR R36,R36
SUBR R15,R36,R37
ADDI R16,R0,1
ITOR R16,R16
ADDR R37,R15,R16
BEQZR R37,L26
BLTZR R37,L26
BNEZR R37,L25
L25:
WRS 0
JMP L27
L26:
WRS 5
L27:
WRS 27
ADDI R36,R0,2
ADDI R37,R0,23
SUB R15,R36,R37
ADDI R37,R15,1
BEQZ R37,L29
BLTZ R37,L29
BNEZ R37,L28
L28:
WRS 0
JMP L30
L29:
WRS 5
L30:
WRS 29
MOVIR R36,3.5
MOVIR R37,1.1
SUBR R15,R36,R37
ADDI R16,R0,1
ITOR R16,R16
ADDR R37,R15,R16
BEQZR R37,L32
BLTZR R37,L32
BNEZR R37,L31
L31:
WRS 0
JMP L33
L32:
WRS 5
L33:
WRS 31
ADDI R36,R0,2
MOVIR R37,3.5
ITOR R36,R36
SUBR R15,R36,R37
MOVIR R16,3.5
ADDI R17,R0,2
ITOR R17,R17
SUBR R16,R16,R17
MULR R37,R15,R16
ADDI R28,R0,-1
ITOR R28,R28
MULR R37,R37,R28
BEQZR R37,L35
BLTZR R37,L35
BNEZR R37,L34
L34:
WRS 0
JMP L36
L35:
WRS 5
L36:
WRS 33
ADDI R36,R0,2
ADDI R37,R0,2
SUB R15,R36,R37
ADDI R16,R0,2
ADDI R17,R0,2
SUB R16,R16,R17
MUL R37,R15,R16
MULI R37,R37,-1
BEQZ R37,L38
BLTZ R37,L38
BNEZ R37,L37
L37:
WRS 0
JMP L39
L38:
WRS 5
L39:
WRS 35
MOVIR R36,3.5
MOVIR R37,1.1
SUBR R15,R36,R37
MOVIR R16,1.1
MOVIR R17,3.5
SUBR R16,R16,R17
MULR R37,R15,R16
ADDI R34,R0,-1
ITOR R34,R34
MULR R37,R37,R34
BEQZR R37,L41
BLTZR R37,L41
BNEZR R37,L40
L40:
WRS 0
JMP L42
L41:
WRS 5
L42:
WRS 37
ADDI R37,R0,2
ADDI R36,R0,2
XOR R37,R37,R36
WR R37
WRS 39
ADDI R37,R0,2
WR R37
WRS 41
MOVIR R37,2.0
WRR R37
WRS 43
MOVIR R37,5.0
WRR R37
HALT
DATA 116
DATA 114
DATA 117
DATA 101
DATA 0
DATA 102
DATA 97
DATA 108
DATA 115
DATA 101
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0
DATA 10
DATA 0