Skip to content

VERIFICATION.md

Latest commit

 

History

History
69 lines (59 loc) · 2.82 KB

VERIFICATION.md

File metadata and controls

69 lines (59 loc) · 2.82 KB

Verification Report

Overview

This document summarizes the verification results for the Hierarchical Cache System. The design has been verified using a self-checking testbench that simulates end-to-end transactions from the CPU to Main Memory through three levels of cache.

Test Environment

  • Simulator: Icarus Verilog (v12.0)
  • Language: SystemVerilog 2012
  • Testbench: tb/tb_hierarchical_cache.sv

Test Cases Verified

1. Cold Miss Write & Read

  • Description: Accessing a memory location not present in any cache level.
  • Workflow: L1 Miss -> L2 Miss -> L3 Miss -> Memory Fetch -> L1 Allocation -> CPU Write.
  • Result: PASS

2. Read Hit

  • Description: Reading data that is already present in the L1 Data Cache.
  • Result: PASS (Zero latency response after allocation).

3. Write Hit (Write-Back)

  • Description: Updating data in the L1 Cache. The cache line is marked as dirty, and no immediate write is sent to L2.
  • Result: PASS

4. Conflict Miss & Eviction

  • Description: Filling a cache set to capacity and then accessing a new address that maps to the same set.
  • Workflow: L1 Miss -> Identify Victim Way -> Write-back Dirty Line to L2 -> Fetch New Line from L2/Mem -> Update L1.
  • Result: PASS

5. Data Integrity (L1 <-> L2 Handover)

  • Description: Verifying that data evicted from L1 to L2 is correctly stored and can be retrieved later.
  • Result: PASS

Simulation Logs

----------------------------------------------------------------
Starting Cache Verification
----------------------------------------------------------------
[CPU] Write Addr: 00000100 Data: deadbeef
[MEM] Reading Addr: 00000000
[CPU] Write Complete
[CPU] Read Addr: 00000100
[CPU] Read Return: deadbeef
PASS: Read Hit correct
[CPU] Write Addr: 00000100 Data: cafebabe
[CPU] Write Complete
[CPU] Read Addr: 00000100
[CPU] Read Return: cafebabe
PASS: Write Hit correct
----------------------------------------------------------------
Starting Eviction and Writeback Test
----------------------------------------------------------------
[TB] Filling Set 0 with 4 different addresses...
[CPU] Write Addr: 00000100 Data: 11111111
...
[TB] Writing to 5th address (0x500) to trigger eviction of 0x100...
[CPU] Write Addr: 00000500 Data: 55555555
[TB] Verifying evicted data (0x100) can be read back...
[CPU] Read Addr: 00000100
[CPU] Read Return: 11111111
PASS: Data integrity maintained through eviction and writeback
----------------------------------------------------------------
Test Complete - Hierarchical Cache is Operational
----------------------------------------------------------------

Summary

The system demonstrates correct hierarchical behavior, managing hits, misses, and write-back cycles across L1, L2, and L3 caches while ensuring data consistency with main memory.