Verilog/rep1.vcd at main · rahuldaniel/Verilog · GitHub

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$date
	Thu Mar 31 15:05:08 2022
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module testbench $end
$var wire 1 ! f $end
$var wire 1 " e $end
$var wire 1 # d $end
$var wire 1 $ c $end
$var wire 1 % b $end
$var wire 1 & a $end
$var reg 1 ' x $end
$var reg 1 ( y $end
$scope module uut $end
$var wire 1 & a $end
$var wire 1 % b $end
$var wire 1 $ c $end
$var wire 1 # d $end
$var wire 1 " e $end
$var wire 1 ! f $end
$var wire 1 ' x $end
$var wire 1 ( y $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
x(
x'
x&
x%
x$
x#
x"
x!
$end
#5
1!
1%
1#
0"
0&
0$
0(
0'
#10
0!
0%
1"
1&
1(
#15
0!
1"
0(
1'
#20
1!
0"
0#
1$
1(
#25