Computer-Architecture-Lab/transcript at master · pooyaaf/Computer-Architecture-Lab · GitHub

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# Compile of StageMem.v failed with 1 errors.
# Compile of StageMem.v failed with 1 errors.
# Compile of StageMem.v was successful.
vsim -gui work.TB
# vsim -gui work.TB
# Start time: 13:36:57 on Jan 01,2024
# Loading work.TB
# Loading work.Sram
# Loading work.Top
# Loading work.StageIF
# Loading work.MUX2to1
# Loading work.Register
# Loading work.InstructionMemory
# Loading work.Adder
# Loading work.RegIFID
# Loading work.StageId
# Loading work.ConditionCheck
# Loading work.ControlUnit
# Loading work.RegisterFile
# Loading work.RegIDEX
# Loading work.StageEx
# Loading work.Val2Generator
# Loading work.RegisterNegEdge
# Loading work.ALU
# Loading work.MUX4to1
# Loading work.RegsExMem
# Loading work.StageMem
# Loading work.SramController
# Loading work.CacheController
# Loading work.RegsMemWb
# Loading work.HazardUnit
# Loading work.ForwardingUnit
# WARNING: No extended dataflow license exists
# Trace back: Error QStructure::sort: invalid command name ""
#   <6:C:/mtitcl/vsim/qstructure.tc_:2478: ::QStructure::sort .main_pane.structure 0 ascending
#   <5:eval:1: ::QStructure::structsort .main_pane.structure 0 ascending
#   <4:eval:1: ::namespace inscope ::QStructure {structsort .main_pane.structure} 0 ascending
#   >3:proc:26: ::.main_pane.structure.interior.cs.body.struct sort 0 ascending
#   >2:proc:10: ::.main_pane.structure.interior.cs.body.struct _initializeSortColumn
#   <1:eval:1: ::namespace inscope ::vsimwidgets::Hierarchy {::.main_pane.structure.interior.cs.body.struct _initializeSortColumn}
add wave -position insertpoint  \
sim:/TB/clk \
sim:/TB/rst
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
add wave -position insertpoint  \
sim:/TB/top/Stageid/rf/regFile
add wave -position insertpoint sim:/TB/top/stageMem/cacheController/*
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34
add wave -position insertpoint  \
sim:/TB/top/IF/pc
restart
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34
add wave -position insertpoint  \
sim:/TB/top/stageMem/cacheController/way0First \
sim:/TB/top/stageMem/cacheController/way0Second \
sim:/TB/top/stageMem/cacheController/way1First \
sim:/TB/top/stageMem/cacheController/way1Second
restart
restart
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34
add wave -position insertpoint sim:/TB/top/stageMem/sramcontroller/*
restart
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34
# Compile of ARM.v was successful.
# Compile of StageIF.v was successful.
# Compile of StageID.v was successful.
# Compile of StageExec.v was successful.
# Compile of StageMem.v was successful.
# Compile of StageWriteBack.v was successful.
# Compile of RegIFID.v was successful.
# Compile of RegIDEX.v was successful.
# Compile of RegExecMem.v was successful.
# Compile of RegMemWB.v was successful.
# Compile of Adder.v was successful.
# Compile of Register.v was successful.
# Compile of MUX2to1.v was successful.
# Compile of MUX4to1.v was successful.
# Compile of InstructionMemory.v was successful.
# Compile of Top.v was successful.
# Compile of TB.v was successful.
# Compile of register_file.v was successful.
# Compile of control_unit.v was successful.
# Compile of condition_check.v was successful.
# Compile of ALU.v was successful.
# Compile of val2_generator.v was successful.
# Compile of data_memory.v was successful.
# Compile of hazard_unit.v was successful.
# Compile of forwarding_unit.v was successful.
# Compile of sram_controller.v was successful.
# Compile of sram.v was successful.
# Compile of cache_controller.v was successful.
# 28 compiles, 0 failed with no errors.
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.TB
# Loading work.Sram
# Loading work.Top
# Loading work.StageIF
# Loading work.MUX2to1
# Loading work.Register
# Loading work.InstructionMemory
# Loading work.Adder
# Loading work.RegIFID
# Loading work.StageId
# Loading work.ConditionCheck
# Loading work.ControlUnit
# Loading work.RegisterFile
# Loading work.RegIDEX
# Loading work.StageEx
# Loading work.Val2Generator
# Loading work.RegisterNegEdge
# Loading work.ALU
# Loading work.MUX4to1
# Loading work.RegsExMem
# Loading work.StageMem
# Loading work.SramController
# Loading work.CacheController
# Loading work.RegsMemWb
# Loading work.HazardUnit
# Loading work.ForwardingUnit
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34
add wave -position insertpoint sim:/TB/sram/*
restart
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34
# Compile of ARM.v was successful.
# Compile of StageIF.v was successful.
# Compile of StageID.v was successful.
# Compile of StageExec.v was successful.
# Compile of StageMem.v was successful.
# Compile of StageWriteBack.v was successful.
# Compile of RegIFID.v was successful.
# Compile of RegIDEX.v was successful.
# Compile of RegExecMem.v was successful.
# Compile of RegMemWB.v was successful.
# Compile of Adder.v was successful.
# Compile of Register.v was successful.
# Compile of MUX2to1.v was successful.
# Compile of MUX4to1.v was successful.
# Compile of InstructionMemory.v was successful.
# Compile of Top.v was successful.
# Compile of TB.v was successful.
# Compile of ARM.v was successful with warnings.
# Compile of StageIF.v was successful.
# Compile of StageID.v was successful.
# Compile of StageExec.v was successful.
# Compile of StageMem.v was successful.
# Compile of StageWriteBack.v was successful.
# Compile of RegIFID.v was successful.
# Compile of RegIDEX.v was successful.
# Compile of RegExecMem.v was successful.
# Compile of RegMemWB.v was successful.
# Compile of Adder.v was successful.
# Compile of Register.v was successful.
# Compile of MUX2to1.v was successful.
# Compile of MUX4to1.v was successful.
# Compile of InstructionMemory.v was successful.
# Compile of Top.v was successful.
# Compile of TB.v was successful.
# Compile of register_file.v was successful.
# Compile of control_unit.v was successful.
# Compile of condition_check.v was successful.
# Compile of ALU.v was successful.
# Compile of val2_generator.v was successful.
# Compile of data_memory.v was successful.
# Compile of hazard_unit.v was successful.
# Compile of forwarding_unit.v was successful.
# Compile of sram_controller.v was successful.
# Compile of sram.v was successful.
# Compile of cache_controller.v was successful.
# 28 compiles, 0 failed with no errors.
# Compile of register_file.v was successful.
# Compile of control_unit.v was successful.
# Compile of condition_check.v was successful.
# Compile of ALU.v was successful.
# Compile of val2_generator.v was successful.
# Compile of data_memory.v was successful.
# Compile of hazard_unit.v was successful.
# Compile of forwarding_unit.v was successful.
# Compile of sram_controller.v was successful.
# Compile of sram.v was successful.
# Compile of cache_controller.v was successful.
# 28 compiles, 0 failed with no errors.
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.TB
# Loading work.Sram
# Loading work.Top
# Loading work.StageIF
# Loading work.MUX2to1
# Loading work.Register
# Loading work.InstructionMemory
# Loading work.Adder
# Loading work.RegIFID
# Loading work.StageId
# Loading work.ConditionCheck
# Loading work.ControlUnit
# Loading work.RegisterFile
# Loading work.RegIDEX
# Loading work.StageEx
# Loading work.Val2Generator
# Loading work.RegisterNegEdge
# Loading work.ALU
# Loading work.MUX4to1
# Loading work.RegsExMem
# Loading work.StageMem
# Loading work.SramController
# Loading work.CacheController
# Loading work.RegsMemWb
# Loading work.HazardUnit
# Loading work.ForwardingUnit
run -all
# ** Note: $stop    : F:/University_terms/term 9/CALab/Projects/ARM/TB.v(34)
#    Time: 100100 ns  Iteration: 0  Instance: /TB
# Break in Module TB at F:/University_terms/term 9/CALab/Projects/ARM/TB.v line 34