From 1e3defb987f8a3e287fc00eb61b2b0956a52293a Mon Sep 17 00:00:00 2001 From: Ivan Boldyrev Date: Sun, 1 Mar 2026 10:06:22 +0100 Subject: [PATCH 1/3] instructions: feature flag `meta_field` --- aarchmrs-gen/src/downloads.rs | 2 +- aarchmrs-gen/src/generation.rs | 22 + aarchmrs-instructions/CHANGELOG.md | 1 + aarchmrs-instructions/Cargo.toml | 1 + aarchmrs-instructions/src/A32/brblk/b_imm.rs | 36 + .../src/A32/brblk/ldstexcept.rs | 96 + aarchmrs-instructions/src/A32/brblk/ldstm.rs | 288 + .../src/A32/cops_as/advsimdext/floatdpmac.rs | 354 ++ .../src/A32/cops_as/advsimdext/fpcsel.rs | 432 ++ .../src/A32/cops_as/advsimdext/fpcvtrnd.rs | 648 +++ .../src/A32/cops_as/advsimdext/fpextins.rs | 48 + .../src/A32/cops_as/advsimdext/fpminmaxnm.rs | 216 + .../cops_as/advsimdext/simd3reg_sameext.rs | 810 +++ .../A32/cops_as/advsimdext/simd_dotprod.rs | 360 ++ .../src/A32/cops_as/fpdp/fpdp2reg.rs | 1998 +++++++ .../src/A32/cops_as/fpdp/fpdp3reg.rs | 1638 ++++++ .../src/A32/cops_as/fpdp/fpimm.rs | 90 + .../src/A32/cops_as/svcall/svc.rs | 12 + .../src/A32/cops_as/sys_mov32/movcpgp32.rs | 84 + .../src/A32/cops_as/sys_mov32/movfpgp16.rs | 48 + .../src/A32/cops_as/sys_mov32/movfpgp32.rs | 48 + .../src/A32/cops_as/sys_mov32/movfpsr.rs | 36 + .../src/A32/cops_as/sys_mov32/movsimdgp.rs | 150 + .../src/A32/cops_as/sysldst_mov64/ldstcp.rs | 210 + .../A32/cops_as/sysldst_mov64/ldstsimdfp.rs | 702 +++ .../A32/cops_as/sysldst_mov64/movcpgp64.rs | 72 + .../cops_as/sysldst_mov64/movsimdfpgp64.rs | 120 + .../src/A32/dp/dpimm/intdp1reg_imm.rs | 72 + .../src/A32/dp/dpimm/intdp2reg_imm.rs | 492 ++ .../src/A32/dp/dpimm/log2reg_imm.rs | 168 + .../src/A32/dp/dpimm/movsr_hint_imm.rs | 96 + .../src/A32/dp/dpimm/movw.rs | 48 + .../src/A32/dp/dpmisc/blx_reg.rs | 12 + .../src/A32/dp/dpmisc/bx_reg.rs | 12 + .../src/A32/dp/dpmisc/bxj_reg.rs | 12 + .../src/A32/dp/dpmisc/clz.rs | 18 + .../src/A32/dp/dpmisc/crc32.rs | 144 + .../src/A32/dp/dpmisc/eret.rs | 6 + .../src/A32/dp/dpmisc/except.rs | 66 + .../src/A32/dp/dpmisc/intsat.rs | 96 + .../src/A32/dp/dpmisc/movsr_reg.rs | 102 + .../src/A32/dp/dpregis/intdp2reg_immsh.rs | 192 + .../src/A32/dp/dpregis/intdp3reg_immsh.rs | 1152 ++++ .../src/A32/dp/dpregis/logic3reg_immsh.rs | 432 ++ .../src/A32/dp/dpregrs/intdp2reg_regsh.rs | 120 + .../src/A32/dp/dpregrs/intdp3reg_regsh.rs | 576 ++ .../src/A32/dp/dpregrs/logic3reg_regsh.rs | 264 + aarchmrs-instructions/src/A32/dp/mul_half.rs | 444 ++ aarchmrs-instructions/src/A32/dp/mul_word.rs | 408 ++ .../src/A32/dp/sync/ldst_excl.rs | 444 ++ .../src/A32/dp/xldst/ldstximm.rs | 948 +++ .../src/A32/dp/xldst/ldstxreg.rs | 660 +++ aarchmrs-instructions/src/A32/ldstimm.rs | 552 ++ aarchmrs-instructions/src/A32/ldstreg.rs | 672 +++ aarchmrs-instructions/src/A32/media/bfi.rs | 54 + aarchmrs-instructions/src/A32/media/bfx.rs | 60 + aarchmrs-instructions/src/A32/media/extend.rs | 324 ++ aarchmrs-instructions/src/A32/media/pack.rs | 60 + .../src/A32/media/parallel.rs | 864 +++ .../src/A32/media/reverse.rs | 72 + aarchmrs-instructions/src/A32/media/sat16.rs | 48 + aarchmrs-instructions/src/A32/media/sat32.rs | 120 + .../src/A32/media/selbytes.rs | 24 + .../src/A32/media/smul_div.rs | 552 ++ aarchmrs-instructions/src/A32/media/udf.rs | 12 + aarchmrs-instructions/src/A32/media/usad.rs | 54 + .../advsimddp/a_simd_12reg/simd1reg_imm.rs | 780 +++ .../advsimddp/a_simd_12reg/simd2reg_shift.rs | 1056 ++++ .../advsimddp/a_simd_mulreg/simd2reg_dup.rs | 60 + .../advsimddp/a_simd_mulreg/simd2reg_misc.rs | 2700 +++++++++ .../a_simd_mulreg/simd2reg_scalar.rs | 894 +++ .../advsimddp/a_simd_mulreg/simd3reg_diff.rs | 732 +++ .../advsimddp/a_simd_mulreg/simd3reg_ext.rs | 84 + .../advsimddp/a_simd_mulreg/simd3reg_tbl.rs | 84 + .../A32/uncond_as/advsimddp/simd3reg_same.rs | 5118 +++++++++++++++++ .../src/A32/uncond_as/advsimdls/ldstv_ms.rs | 1644 ++++++ .../A32/uncond_as/advsimdls/ldstv_ssone.rs | 1872 ++++++ .../src/A32/uncond_as/advsimdls/ldv_ssall.rs | 438 ++ .../src/A32/uncond_as/uncondhints/barriers.rs | 18 + .../A32/uncond_as/uncondhints/preload_imm.rs | 66 + .../A32/uncond_as/uncondhints/preload_reg.rs | 144 + .../src/A32/uncond_as/uncondmisc/cps.rs | 126 + .../src/A32/uncond_as/uncondmisc/setpan.rs | 6 + .../src/A64/control/barriers.rs | 30 + .../src/A64/control/branch_imm.rs | 12 + .../src/A64/control/branch_reg.rs | 108 + .../src/A64/control/compbranch.rs | 48 + .../src/A64/control/compbranch_imm.rs | 216 + .../src/A64/control/compbranch_regs.rs | 216 + .../src/A64/control/compbranch_regs2.rs | 216 + .../src/A64/control/condbranch.rs | 24 + .../src/A64/control/exception.rs | 60 + .../src/A64/control/hints.rs | 30 + .../src/A64/control/miscbranch.rs | 12 + .../src/A64/control/pstate.rs | 18 + .../src/A64/control/syspairinstrs.rs | 30 + .../src/A64/control/systeminstrs.rs | 60 + .../src/A64/control/systeminstrswithreg.rs | 12 + .../src/A64/control/systemmove.rs | 72 + .../src/A64/control/systemmovepr.rs | 72 + .../src/A64/control/tchange_imm.rs | 36 + .../src/A64/control/tchange_reg.rs | 36 + .../src/A64/control/testbranch.rs | 48 + .../src/A64/dpimm/addsub_imm.rs | 192 + .../src/A64/dpimm/addsub_immtags.rs | 48 + .../src/A64/dpimm/bitfield.rs | 144 + .../src/A64/dpimm/dp_1src_imm.rs | 12 + .../src/A64/dpimm/extract.rs | 48 + .../src/A64/dpimm/log_imm.rs | 216 + .../src/A64/dpimm/minmax_imm.rs | 144 + .../src/A64/dpimm/movewide.rs | 108 + .../src/A64/dpimm/pcreladdr.rs | 36 + .../src/A64/dpreg/addsub_carry.rs | 144 + .../src/A64/dpreg/addsub_ext.rs | 240 + .../src/A64/dpreg/addsub_pt.rs | 48 + .../src/A64/dpreg/addsub_shift.rs | 240 + .../src/A64/dpreg/condcmp_imm.rs | 96 + .../src/A64/dpreg/condcmp_reg.rs | 96 + .../src/A64/dpreg/condsel.rs | 192 + .../src/A64/dpreg/dp_1src.rs | 372 ++ .../src/A64/dpreg/dp_2src.rs | 594 ++ .../src/A64/dpreg/dp_3src.rs | 276 + .../src/A64/dpreg/log_shift.rs | 480 ++ aarchmrs-instructions/src/A64/dpreg/rmif.rs | 18 + aarchmrs-instructions/src/A64/dpreg/setf.rs | 12 + .../src/A64/ldst/asisdlse.rs | 336 ++ .../src/A64/ldst/asisdlsep.rs | 756 +++ .../src/A64/ldst/asisdlso.rs | 948 +++ .../src/A64/ldst/asisdlsop.rs | 2040 +++++++ aarchmrs-instructions/src/A64/ldst/comswap.rs | 288 + .../src/A64/ldst/comswap_unpriv.rs | 72 + .../src/A64/ldst/comswappr.rs | 144 + .../src/A64/ldst/comswappr_unpriv.rs | 72 + .../src/A64/ldst/ldapstl_simd.rs | 180 + .../src/A64/ldst/ldapstl_unscaled.rs | 234 + .../src/A64/ldst/ldapstl_writeback.rs | 48 + .../src/A64/ldst/ldiappstilp.rs | 198 + .../src/A64/ldst/ldst_gcs.rs | 24 + .../src/A64/ldst/ldst_immpost.rs | 414 ++ .../src/A64/ldst/ldst_immpre.rs | 414 ++ .../src/A64/ldst/ldst_pac.rs | 96 + .../src/A64/ldst/ldst_pos.rs | 432 ++ .../src/A64/ldst/ldst_regoff.rs | 906 +++ .../src/A64/ldst/ldst_unpriv.rs | 234 + .../src/A64/ldst/ldst_unscaled.rs | 432 ++ .../src/A64/ldst/ldstexclp.rs | 168 + .../src/A64/ldst/ldstexclr.rs | 240 + .../src/A64/ldst/ldstexclr_unpriv.rs | 120 + .../src/A64/ldst/ldstnapair_offs.rs | 336 ++ aarchmrs-instructions/src/A64/ldst/ldstord.rs | 192 + .../src/A64/ldst/ldstpair_off.rs | 384 ++ .../src/A64/ldst/ldstpair_post.rs | 384 ++ .../src/A64/ldst/ldstpair_pre.rs | 384 ++ .../src/A64/ldst/ldsttags.rs | 270 + aarchmrs-instructions/src/A64/ldst/loadlit.rs | 84 + aarchmrs-instructions/src/A64/ldst/memcms.rs | 2880 ++++++++++ aarchmrs-instructions/src/A64/ldst/memop.rs | 5052 ++++++++++++++++ .../src/A64/ldst/memop_128.rs | 648 +++ .../src/A64/ldst/memop_unpriv.rs | 576 ++ .../src/A64/ldst/memset_go.rs | 216 + .../src/A64/ldst/rcwcomswap.rs | 144 + .../src/A64/ldst/rcwcomswappr.rs | 144 + .../src/A64/reserved/perm_undef.rs | 6 + .../src/A64/simd_dp/asimdall.rs | 288 + .../src/A64/simd_dp/asimddiff.rs | 780 +++ .../src/A64/simd_dp/asimdelem.rs | 1956 +++++++ .../src/A64/simd_dp/asimdext.rs | 30 + .../src/A64/simd_dp/asimdimm.rs | 1002 ++++ .../src/A64/simd_dp/asimdins.rs | 162 + .../src/A64/simd_dp/asimdmisc.rs | 1656 ++++++ .../src/A64/simd_dp/asimdmiscfp16.rs | 522 ++ .../src/A64/simd_dp/asimdperm.rs | 180 + .../src/A64/simd_dp/asimdsame.rs | 2448 ++++++++ .../src/A64/simd_dp/asimdsame2.rs | 636 ++ .../src/A64/simd_dp/asimdsamefp16.rs | 648 +++ .../src/A64/simd_dp/asimdshf.rs | 840 +++ .../src/A64/simd_dp/asimdtbl.rs | 294 + .../src/A64/simd_dp/asisddiff.rs | 72 + .../src/A64/simd_dp/asisdelem.rs | 606 ++ .../src/A64/simd_dp/asisdmisc.rs | 582 ++ .../src/A64/simd_dp/asisdmiscfp16.rs | 240 + .../src/A64/simd_dp/asisdone.rs | 18 + .../src/A64/simd_dp/asisdpair.rs | 162 + .../src/A64/simd_dp/asisdsame.rs | 672 +++ .../src/A64/simd_dp/asisdsame2.rs | 48 + .../src/A64/simd_dp/asisdsamefp16.rs | 162 + .../src/A64/simd_dp/asisdshf.rs | 576 ++ .../src/A64/simd_dp/crypto3_imm2.rs | 96 + .../src/A64/simd_dp/crypto3_imm6.rs | 24 + .../src/A64/simd_dp/crypto4.rs | 72 + .../src/A64/simd_dp/cryptoaes.rs | 48 + .../src/A64/simd_dp/cryptosha2.rs | 36 + .../src/A64/simd_dp/cryptosha3.rs | 126 + .../src/A64/simd_dp/cryptosha512_2.rs | 24 + .../src/A64/simd_dp/cryptosha512_3.rs | 126 + .../src/A64/simd_dp/float2fix.rs | 432 ++ .../src/A64/simd_dp/float2int.rs | 1572 +++++ .../src/A64/simd_dp/floatccmp.rs | 144 + .../src/A64/simd_dp/floatcmp.rs | 108 + .../src/A64/simd_dp/floatdp1.rs | 576 ++ .../src/A64/simd_dp/floatdp2.rs | 486 ++ .../src/A64/simd_dp/floatdp3.rs | 288 + .../src/A64/simd_dp/floatimm.rs | 36 + .../src/A64/simd_dp/floatsel.rs | 72 + .../mortlach_f64f64_prod4.rs | 144 + .../mortlach_i16i64_prod4.rs | 576 ++ .../mortlach_b16b16_prod.rs | 60 + .../mortlach_bini32_prod.rs | 60 + .../mortlach_f16f16_prod.rs | 60 + .../mortlach_f8f16_prod.rs | 30 + .../mortlach2_prod4/mortlach_b16b16_prod4.rs | 144 + .../mortlach2_prod4/mortlach_b16f32_prod4.rs | 144 + .../mortlach2_prod4/mortlach_f16f16_prod4.rs | 144 + .../mortlach2_prod4/mortlach_f16f32_prod4.rs | 144 + .../mortlach2_prod4/mortlach_f32f32_prod4.rs | 144 + .../mortlach2_prod4/mortlach_f8f16_prod4.rs | 72 + .../mortlach2_prod4/mortlach_f8f32_prod4.rs | 72 + .../mortlach2_prod4/mortlach_i16i32_prod4.rs | 288 + .../mortlach2_prod4/mortlach_i8i32_prod4.rs | 576 ++ .../mortlach_b16b16_1in2ss_prod.rs | 36 + .../mortlach_b16f32_2in4ss_prod.rs | 36 + .../mortlach_f16f16_1in2ss_prod.rs | 36 + .../mortlach_f16f32_2in4ss_prod.rs | 36 + .../mortlach_f32f32_1in2ss_prod.rs | 36 + .../mortlach_f8f16_2in4ss_prod.rs | 36 + .../mortlach_f8f32_2in4ss_prod.rs | 36 + .../mortlach_i16i32_2in4ss_prod.rs | 72 + .../mortlach_i8i32_2in4ss_prod.rs | 144 + .../mortlach_b16f32_prod.rs | 60 + .../mortlach_f16f32_prod.rs | 60 + .../mortlach_f32f32_prod.rs | 60 + .../mortlach_f8f32_prod.rs | 30 + .../mortlach_i16i32_prod.rs | 120 + .../mortlach_i8i32_prod.rs | 240 + .../mortlach_f64f64_prod.rs | 60 + .../mortlach_i16i64_prod.rs | 240 + .../sme/mortlach_ext/mortlach_extract_pred.rs | 168 + .../sme/mortlach_ext/mortlach_extract_zero.rs | 138 + .../mortlach_multi2_extract_ctg.rs | 108 + .../mortlach_multi2_extract_zero.rs | 108 + .../mortlach_multi2_za_extract_ctg.rs | 18 + .../mortlach_multi2_za_extract_zero.rs | 18 + .../mortlach_multi4_extract_ctg.rs | 102 + .../mortlach_multi4_extract_zero.rs | 102 + .../mortlach_multi4_za_extract_ctg.rs | 18 + .../mortlach_multi4_za_extract_zero.rs | 18 + .../A64/sme/mortlach_hvadd/mortlach_addhv.rs | 96 + .../sme/mortlach_ins/mortlach_insert_pred.rs | 168 + .../mortlach_multi2_insert_ctg.rs | 108 + .../mortlach_multi2_za_insert_ctg.rs | 18 + .../mortlach_multi4_insert_ctg.rs | 102 + .../mortlach_multi4_za_insert_ctg.rs | 18 + .../sme/mortlach_mem/mortlach_contig_load.rs | 162 + .../sme/mortlach_mem/mortlach_contig_qload.rs | 36 + .../mortlach_mem/mortlach_contig_qstore.rs | 36 + .../sme/mortlach_mem/mortlach_contig_store.rs | 162 + .../sme/mortlach_mem/mortlach_ctxt_ldst.rs | 36 + .../A64/sme/mortlach_mem/mortlach_zt_ldst.rs | 12 + .../mortlach_mov_zt/mortlach_extract_zt.rs | 12 + .../sme/mortlach_mov_zt/mortlach_insert_zt.rs | 12 + .../mortlach_mov_zt/mortlach_move_to_zt.rs | 12 + .../mortlach_multi1_zz_za_fma_long_sm.rs | 96 + .../mortlach_multi1_zz_za_mla_long_long_sm.rs | 144 + .../mortlach_multi1_zz_za_mla_long_sm.rs | 96 + .../mortlach_multi2_z_za_2way_dot_sm.rs | 48 + .../mortlach_multi2_z_za_4way_dot_sm.rs | 60 + .../mortlach_multi2_z_za_fpdot_sm.rs | 96 + .../mortlach_multi2_z_za_mixed_dot_sm.rs | 48 + .../mortlach_multi2_zz_za_f16_sm.rs | 96 + .../mortlach_multi2_zz_za_float_sm.rs | 60 + .../mortlach_multi2_zz_za_fma_long_sm.rs | 120 + ...tlach_multi2_zz_za_fp8_fma_long_long_sm.rs | 24 + .../mortlach_multi2_zz_za_int_sm.rs | 60 + .../mortlach_multi2_zz_za_mla_long_long_sm.rs | 168 + .../mortlach_multi2_zz_za_mla_long_sm.rs | 96 + ...tlach_multi1_zz_za_fp8_fma_long_long_sm.rs | 24 + .../mortlach_multi1_zz_za_fp8_fma_long_sm.rs | 24 + .../mortlach_multi4_z_za_2way_dot_sm.rs | 48 + .../mortlach_multi4_z_za_4way_dot_sm.rs | 60 + .../mortlach_multi4_z_za_fpdot_sm.rs | 96 + .../mortlach_multi4_z_za_mixed_dot_sm.rs | 48 + .../mortlach_multi4_zz_za_f16_sm.rs | 96 + .../mortlach_multi4_zz_za_float_sm.rs | 60 + .../mortlach_multi4_zz_za_fma_long_sm.rs | 120 + ...tlach_multi4_zz_za_fp8_fma_long_long_sm.rs | 24 + .../mortlach_multi4_zz_za_int_sm.rs | 60 + .../mortlach_multi4_zz_za_mla_long_long_sm.rs | 168 + .../mortlach_multi4_zz_za_mla_long_sm.rs | 96 + .../mortlach_multi2_z_za_2way_dot_mm.rs | 48 + .../mortlach_multi2_z_za_4way_dot_mm.rs | 60 + .../mortlach_multi2_z_za_f16_mm.rs | 72 + .../mortlach_multi2_z_za_float_mm.rs | 48 + .../mortlach_multi2_z_za_fpdot_mm.rs | 96 + .../mortlach_multi2_z_za_int_mm.rs | 48 + .../mortlach_multi2_z_za_mixed_dot_mm.rs | 24 + .../mortlach_multi2_zz_za_f16_mm.rs | 96 + .../mortlach_multi2_zz_za_float_mm.rs | 60 + .../mortlach_multi2_zz_za_fma_long_mm.rs | 96 + ...tlach_multi2_zz_za_fp8_fma_long_long_mm.rs | 24 + .../mortlach_multi2_zz_za_fp8_fma_long_mm.rs | 24 + .../mortlach_multi2_zz_za_int_mm.rs | 60 + .../mortlach_multi2_zz_za_mla_long_long_mm.rs | 144 + .../mortlach_multi2_zz_za_mla_long_mm.rs | 96 + .../mortlach_multi4_z_za_2way_dot_mm.rs | 48 + .../mortlach_multi4_z_za_4way_dot_mm.rs | 60 + .../mortlach_multi4_z_za_f16_mm.rs | 72 + .../mortlach_multi4_z_za_float_mm.rs | 48 + .../mortlach_multi4_z_za_fpdot_mm.rs | 96 + .../mortlach_multi4_z_za_int_mm.rs | 48 + .../mortlach_multi4_z_za_mixed_dot_mm.rs | 24 + .../mortlach_multi4_zz_za_f16_mm.rs | 96 + .../mortlach_multi4_zz_za_float_mm.rs | 60 + .../mortlach_multi4_zz_za_fma_long_mm.rs | 96 + ...tlach_multi4_zz_za_fp8_fma_long_long_mm.rs | 24 + .../mortlach_multi4_zz_za_fp8_fma_long_mm.rs | 24 + .../mortlach_multi4_zz_za_int_mm.rs | 60 + .../mortlach_multi4_zz_za_mla_long_long_mm.rs | 144 + .../mortlach_multi4_zz_za_mla_long_mm.rs | 96 + .../mortlach_multi1_fma_long_idx.rs | 144 + .../mortlach_multi1_fp8_fma_long_idx.rs | 42 + .../mortlach_multi1_fp8_fma_long_long_idx.rs | 36 + .../mortlach_multi1_mla_long_idx.rs | 144 + .../mortlach_multi1_mla_long_long_idx_d.rs | 144 + .../mortlach_multi1_mla_long_long_idx_s.rs | 216 + .../mortlach_multi2_fma_long_idx.rs | 144 + .../mortlach_multi2_fp8_fdot_idx.rs | 72 + .../mortlach_multi2_fp8_fma_long_idx.rs | 36 + .../mortlach_multi2_fp8_fma_long_long_idx.rs | 36 + .../mortlach_multi2_fp8_fvdot_idx_s.rs | 72 + .../mortlach_multi2_mla_long_idx.rs | 144 + .../mortlach_multi2_mla_long_long_idx_d.rs | 144 + .../mortlach_multi2_mla_long_long_idx_s.rs | 216 + .../mortlach_multi2_zza_idx_d.rs | 120 + .../mortlach_multi2_zza_idx_h.rs | 144 + .../mortlach_multi2_zza_idx_s.rs | 450 ++ .../mortlach_multi4_fma_long_idx.rs | 144 + .../mortlach_multi4_fp8_fdot_idx_h.rs | 36 + .../mortlach_multi4_fp8_fma_long_idx.rs | 36 + .../mortlach_multi4_fp8_fma_long_long_idx.rs | 36 + .../mortlach_multi4_mla_long_idx.rs | 144 + .../mortlach_multi4_mla_long_long_idx_d.rs | 144 + .../mortlach_multi4_mla_long_long_idx_s.rs | 216 + .../mortlach_multi4_zza_idx_d.rs | 180 + .../mortlach_multi4_zza_idx_h.rs | 144 + .../mortlach_multi4_zza_idx_s.rs | 450 ++ .../mortlach_multi2_cld_cldnt_si_ctg.rs | 192 + .../mortlach_multi2_cld_cldnt_ss_ctg.rs | 192 + .../mortlach_multi2_cst_cstnt_si_ctg.rs | 192 + .../mortlach_multi2_cst_cstnt_ss_ctg.rs | 192 + .../mortlach_multi4_cld_cldnt_si_ctg.rs | 192 + .../mortlach_multi4_cld_cldnt_ss_ctg.rs | 192 + .../mortlach_multi4_cst_cstnt_si_ctg.rs | 192 + .../mortlach_multi4_cst_cstnt_ss_ctg.rs | 192 + .../mortlach_multi2_cld_cldnt_si_nctg.rs | 240 + .../mortlach_multi2_cld_cldnt_ss_nctg.rs | 240 + .../mortlach_multi2_cst_cstnt_si_nctg.rs | 240 + .../mortlach_multi2_cst_cstnt_ss_nctg.rs | 240 + .../mortlach_multi4_cld_cldnt_si_nctg.rs | 240 + .../mortlach_multi4_cld_cldnt_ss_nctg.rs | 240 + .../mortlach_multi4_cst_cstnt_si_nctg.rs | 240 + .../mortlach_multi4_cst_cstnt_ss_nctg.rs | 240 + .../mortlach_multi2_select_int.rs | 30 + .../mortlach_multi4_select_int.rs | 30 + .../mortlach_multi2_z_z_add_sm.rs | 18 + .../mortlach_multi2_z_z_fminmax_sm.rs | 120 + .../mortlach_multi2_z_z_fscale_sm.rs | 30 + .../mortlach_multi2_z_z_minmax_sm.rs | 72 + .../mortlach_multi2_z_z_shift_sm.rs | 36 + .../mortlach_multi2_z_z_sqdmulh_sm.rs | 18 + .../mortlach_multi4_z_z_add_sm.rs | 18 + .../mortlach_multi4_z_z_fminmax_sm.rs | 120 + .../mortlach_multi4_z_z_fscale_sm.rs | 30 + .../mortlach_multi4_z_z_minmax_sm.rs | 72 + .../mortlach_multi4_z_z_shift_sm.rs | 36 + .../mortlach_multi4_z_z_sqdmulh_sm.rs | 18 + .../mortlach_multi2_z_z_fminmax_mm.rs | 156 + .../mortlach_multi2_z_z_fscale_mm.rs | 30 + .../mortlach_multi2_z_z_minmax_mm.rs | 72 + .../mortlach_multi2_z_z_shift_mm.rs | 36 + .../mortlach_multi2_z_z_sqdmulh_mm.rs | 18 + .../mortlach_multi4_z_z_fminmax_mm.rs | 156 + .../mortlach_multi4_z_z_fscale_mm.rs | 30 + .../mortlach_multi4_z_z_minmax_mm.rs | 72 + .../mortlach_multi4_z_z_shift_mm.rs | 36 + .../mortlach_multi4_z_z_sqdmulh_mm.rs | 18 + .../mortlach_multi2_clamp_int.rs | 48 + .../mortlach_multi2_fclamp.rs | 42 + .../mortlach_multi2_qrshr.rs | 54 + .../mortlach_multi2_z_z_long_zip.rs | 36 + .../mortlach_multi2_z_z_zip.rs | 48 + .../mortlach_multi4_clamp_int.rs | 48 + .../mortlach_multi4_fclamp.rs | 42 + .../mortlach_multi4_qrshr.rs | 144 + .../mortlach_multi2_fpint_cvrt.rs | 24 + .../mortlach_multi2_frint.rs | 48 + .../mortlach_multi2_intfp_cvrt.rs | 24 + .../mortlach_multi2_narrow_fp8_cvrt.rs | 24 + .../mortlach_multi2_narrow_fp_cvrt.rs | 48 + .../mortlach_multi2_narrow_int_cvrt.rs | 36 + .../mortlach_multi2_wide_fp8_cvrt.rs | 96 + .../mortlach_multi2_wide_fp_cvrt.rs | 24 + .../mortlach_multi2_wide_int.rs | 36 + .../mortlach_multi4_fpint_cvrt.rs | 24 + .../mortlach_multi4_frint.rs | 48 + .../mortlach_multi4_intfp_cvrt.rs | 24 + .../mortlach_multi4_narrow_fp8_cvrt.rs | 24 + .../mortlach_multi4_narrow_int_cvrt.rs | 108 + .../mortlach_multi4_wide_int.rs | 36 + .../mortlach_multi4_z_z_long_zip.rs | 24 + .../mortlach_multi4_z_z_zip.rs | 36 + .../mortlach_multi2_fmul_mm.rs | 42 + .../mortlach_multi4_fmul_mm.rs | 42 + .../mortlach_multi2_fmul_sm.rs | 42 + .../mortlach_multi4_fmul_sm.rs | 42 + .../mortlach_multi4_lut6_16_ctg.rs | 24 + .../mortlach_multi4_lut6_16_nctg.rs | 30 + .../mortlach_multizero/mortlach_multi_zero.rs | 96 + .../A64/sme/mortlach_zero/mortlach_zero.rs | 6 + .../mortlach_expand_1dst.rs | 60 + .../mortlach_expand_2dst_ctg.rs | 48 + .../mortlach_expand_4dst2src_ctg.rs | 18 + .../mortlach_expand_4dst3src_ctg.rs | 12 + .../mortlach_expand_4dst_ctg.rs | 48 + .../mortlach_expand_2dst_nctg.rs | 60 + .../mortlach_expand_4dst2src_nctg.rs | 24 + .../mortlach_expand_4dst3src_nctg.rs | 18 + .../mortlach_expand_4dst_nctg.rs | 60 + .../src/A64/sve/sve_abal/sve_abal.rs | 48 + .../A64/sve/sve_alloca/sve_int_arith_svl.rs | 36 + .../A64/sve/sve_alloca/sve_int_arith_vl.rs | 36 + .../A64/sve/sve_alloca/sve_int_read_svl_a.rs | 12 + .../A64/sve/sve_alloca/sve_int_read_vl_a.rs | 12 + .../src/A64/sve/sve_cmpgpr/sve_int_cterm.rs | 36 + .../A64/sve/sve_cmpgpr/sve_int_while_rr.rs | 240 + .../src/A64/sve/sve_cmpgpr/sve_int_whilenc.rs | 48 + .../A64/sve/sve_cmpsimm/sve_int_scmp_vi.rs | 180 + .../A64/sve/sve_cmpuimm/sve_int_ucmp_vi.rs | 120 + .../src/A64/sve/sve_cmpvec/sve_int_cmp_0.rs | 240 + .../src/A64/sve/sve_cmpvec/sve_int_cmp_1.rs | 240 + .../src/A64/sve/sve_countelt/sve_int_count.rs | 72 + .../A64/sve/sve_countelt/sve_int_countvlv0.rs | 216 + .../A64/sve/sve_countelt/sve_int_countvlv1.rs | 108 + .../sve_countelt/sve_int_pred_pattern_a.rs | 144 + .../sve_countelt/sve_int_pred_pattern_b.rs | 576 ++ .../A64/sve/sve_fp8_fma_w/sve_fp8_fma_long.rs | 36 + .../sve_fp8_fma_w/sve_fp8_fma_long_long.rs | 72 + .../sve_fp8_fma_long_by_indexed_elem.rs | 60 + .../sve_fp8_fma_long_long_by_indexed_elem.rs | 120 + .../A64/sve/sve_fp8_fmmla/sve_fp8_fmmla.rs | 36 + .../src/A64/sve/sve_fp_clamp/sve_fp_clamp.rs | 42 + .../A64/sve/sve_fp_cmpvev/sve_fp_3op_p_pd.rs | 210 + .../A64/sve/sve_fp_cmpzero/sve_fp_2op_p_pd.rs | 144 + .../sve/sve_fp_fastreduce/sve_fp_fast_red.rs | 120 + .../sve_fp_fastreduceq/sve_fp_fast_redq.rs | 120 + .../src/A64/sve/sve_fp_fcadd/sve_fp_fcadd.rs | 30 + .../src/A64/sve/sve_fp_fcmla/sve_fp_fcmla.rs | 36 + .../sve_fp_fcmla_by_indexed_elem.rs | 60 + .../src/A64/sve/sve_fp_fcvt2/sve_fp_fcvt2.rs | 108 + .../A64/sve/sve_fp_fcvt2z/sve_fp_fcvt2z.rs | 108 + .../A64/sve/sve_fp_fma/sve_fp_3op_p_zds_a.rs | 168 + .../A64/sve/sve_fp_fma/sve_fp_3op_p_zds_b.rs | 120 + .../sve_fp_fma_by_indexed_elem.rs | 216 + .../src/A64/sve/sve_fp_fma_w/sve_fp_fdot.rs | 72 + .../A64/sve/sve_fp_fma_w/sve_fp_fma_long.rs | 144 + .../sve_fp_fdot_by_indexed_elem.rs | 102 + .../sve_fp_fma_long_by_indexed_elem.rs | 240 + .../src/A64/sve/sve_fp_fmmla/sve_fp_fmmla.rs | 72 + .../sve/sve_fp_fmmla_nw/sve_fp_fmmla_nw.rs | 36 + .../sve_fp_fmul_by_indexed_elem.rs | 108 + .../sve/sve_fp_pairwise/sve_fp_pairwise.rs | 120 + .../A64/sve/sve_fp_pred/sve_fp_2op_i_p_zds.rs | 192 + .../A64/sve/sve_fp_pred/sve_fp_2op_p_zds.rs | 504 ++ .../src/A64/sve/sve_fp_pred/sve_fp_ftmad.rs | 24 + .../sve/sve_fp_slowreduce/sve_fp_2op_p_vd.rs | 24 + .../A64/sve/sve_fp_unary/sve_fp_2op_p_zd_a.rs | 168 + .../sve/sve_fp_unary/sve_fp_2op_p_zd_b_0.rs | 144 + .../sve/sve_fp_unary/sve_fp_2op_p_zd_b_1.rs | 48 + .../A64/sve/sve_fp_unary/sve_fp_2op_p_zd_c.rs | 348 ++ .../A64/sve/sve_fp_unary/sve_fp_2op_p_zd_d.rs | 276 + .../sve_fp8_fcvt_narrow.rs | 48 + .../sve_fp_unary_unpred/sve_fp8_fcvt_wide.rs | 96 + .../sve_fp_unary_unpred/sve_fp_2op_u_zd.rs | 36 + .../sve_fp_fcvtzu_narrow.rs | 36 + .../sve_fp_unary_unpred/sve_fp_ucvtf_wide.rs | 72 + .../A64/sve/sve_fp_unpred/sve_fp_3op_u_zd.rs | 198 + .../sve_fp_z2op_p_zd_a.rs | 168 + .../sve_fp_z2op_p_zd_b_0.rs | 144 + .../sve_fp_z2op_p_zd_b_1.rs | 48 + .../sve_fp_z2op_p_zd_c.rs | 348 ++ .../sve_fp_z2op_p_zd_d.rs | 276 + .../src/A64/sve/sve_index/sve_int_index_ii.rs | 24 + .../src/A64/sve/sve_index/sve_int_index_ir.rs | 24 + .../src/A64/sve/sve_index/sve_int_index_ri.rs | 24 + .../src/A64/sve/sve_index/sve_int_index_rr.rs | 24 + .../sve_int_adr/sve_int_bin_cons_misc_0_a.rs | 78 + .../sve_int_mladdsub_vvv_pred.rs | 60 + .../sve_int_mlas_vvv_pred.rs | 60 + .../sve_int_bin_pred_arit_0.rs | 108 + .../sve_int_bin_pred_arit_1.rs | 144 + .../sve_int_bin_pred_arit_2.rs | 72 + .../sve_int_pred_bin/sve_int_bin_pred_div.rs | 96 + .../sve_int_pred_bin/sve_int_bin_pred_log.rs | 96 + .../sve_int_pred_red/sve_int_movprfx_pred.rs | 30 + .../sve/sve_int_pred_red/sve_int_reduce_0.rs | 48 + .../sve/sve_int_pred_red/sve_int_reduce_0q.rs | 24 + .../sve/sve_int_pred_red/sve_int_reduce_1.rs | 96 + .../sve/sve_int_pred_red/sve_int_reduce_1q.rs | 96 + .../sve/sve_int_pred_red/sve_int_reduce_2.rs | 72 + .../sve/sve_int_pred_red/sve_int_reduce_2q.rs | 72 + .../sve_int_bin_pred_shift_0.rs | 270 + .../sve_int_bin_pred_shift_1.rs | 144 + .../sve_int_bin_pred_shift_2.rs | 72 + .../sve_int_pred_un/sve_int_un_pred_arit_0.rs | 384 ++ .../sve_int_pred_un/sve_int_un_pred_arit_1.rs | 336 ++ .../A64/sve/sve_int_select/sve_int_sel_vvv.rs | 30 + .../sve_int_bin_cons_arit_0.rs | 180 + .../sve_int_unpred_arit_b/sve_int_addqp.rs | 24 + .../sve_int_unpred_arit_b/sve_int_addsubp.rs | 24 + .../sve_int_unpred_arit_b/sve_int_mul_b.rs | 90 + .../sve_int_unpred_arit_b/sve_int_sqdmulh.rs | 48 + .../sve_int_bin_cons_log.rs | 72 + .../sve_int_rotate_imm.rs | 30 + .../sve_int_tern_log.rs | 108 + .../sve_int_bin_cons_misc_0_b.rs | 24 + .../sve_int_bin_cons_misc_0_c.rs | 18 + .../sve_int_bin_cons_misc_0_d.rs | 12 + .../sve_int_bin_cons_shift_a.rs | 72 + .../sve_int_bin_cons_shift_b.rs | 90 + .../src/A64/sve/sve_intx_acc/sve_intx_aba.rs | 48 + .../A64/sve/sve_intx_acc/sve_intx_aba_long.rs | 96 + .../A64/sve/sve_intx_acc/sve_intx_adc_long.rs | 96 + .../src/A64/sve/sve_intx_acc/sve_intx_cadd.rs | 48 + .../sve/sve_intx_acc/sve_intx_shift_insert.rs | 60 + .../src/A64/sve/sve_intx_acc/sve_intx_sra.rs | 120 + .../sve_intx_cdot_by_indexed_elem.rs | 60 + .../sve_intx_cmla_by_indexed_elem.rs | 60 + .../sve_intx_dot_by_indexed_elem.rs | 156 + .../sve_intx_mixed_dot_by_indexed_elem.rs | 48 + .../sve_intx_mla_by_indexed_elem.rs | 156 + .../sve_intx_mla_long_by_indexed_elem.rs | 480 ++ .../sve_intx_mul_by_indexed_elem.rs | 78 + .../sve_intx_mul_long_by_indexed_elem.rs | 240 + .../sve_intx_qdmla_long_by_indexed_elem.rs | 240 + .../sve_intx_qdmul_long_by_indexed_elem.rs | 120 + .../sve_intx_qdmulh_by_indexed_elem.rs | 156 + .../sve_intx_qrdcmla_by_indexed_elem.rs | 60 + .../sve_intx_qrdmlah_by_indexed_elem.rs | 156 + .../A64/sve/sve_intx_clamp/sve_intx_clamp.rs | 48 + .../sve_intx_cons_arith_long.rs | 288 + .../sve_intx_cons_arith_wide.rs | 192 + .../sve_intx_cons_mul_long.rs | 228 + .../sve_intx_constructive/sve_intx_clong.rs | 72 + .../sve_intx_constructive/sve_intx_eorx.rs | 48 + .../sve_intx_constructive/sve_intx_mmla.rs | 54 + .../sve_intx_perm_bit.rs | 72 + .../sve_intx_shift_long.rs | 120 + .../sve_crypto_binary_const.rs | 36 + .../sve_intx_crypto/sve_crypto_binary_dest.rs | 36 + .../sve_crypto_binary_multi2.rs | 72 + .../sve_crypto_binary_multi4.rs | 72 + .../sve_intx_crypto/sve_crypto_pmlal_multi.rs | 18 + .../sve_intx_crypto/sve_crypto_pmull_multi.rs | 18 + .../sve/sve_intx_crypto/sve_crypto_unary.rs | 12 + .../A64/sve/sve_intx_dot2/sve_intx_dot2.rs | 36 + .../sve_intx_dot2_by_indexed_elem.rs | 48 + .../sve/sve_intx_histcnt/sve_intx_histcnt.rs | 30 + .../sve_intx_histseg_lut/sve_intx_histseg.rs | 24 + .../sve_intx_histseg_lut/sve_intx_lut2_16.rs | 30 + .../sve_intx_histseg_lut/sve_intx_lut2_8.rs | 24 + .../sve_intx_histseg_lut/sve_intx_lut4_16.rs | 48 + .../sve_intx_histseg_lut/sve_intx_lut4_8.rs | 24 + .../sve_intx_histseg_lut/sve_intx_lut6_16.rs | 24 + .../sve_intx_histseg_lut/sve_intx_lut6_8.rs | 18 + .../sve_intx_muladd_unpred/sve_intx_cdot.rs | 30 + .../sve_intx_muladd_unpred/sve_intx_cmla.rs | 60 + .../sve_intx_muladd_unpred/sve_intx_dot.rs | 84 + .../sve_intx_mixed_dot.rs | 18 + .../sve_intx_mlal_long.rs | 192 + .../sve_intx_qdmlal_long.rs | 96 + .../sve_intx_qdmlalbt.rs | 48 + .../sve_intx_qrdmlah.rs | 48 + .../sve_intx_arith_narrow.rs | 192 + .../sve_intx_extract_narrow.rs | 144 + .../sve_intx_multi_extract_narrow.rs | 36 + .../sve_intx_multi_shift_narrow.rs | 180 + .../sve_intx_shift_narrow.rs | 480 ++ .../sve_intx_accumulate_long_pairs.rs | 48 + .../sve_intx_arith_binary_pairs.rs | 144 + .../sve_intx_bin_pred_shift_sat_round.rs | 288 + .../sve_intx_pred_arith_binary.rs | 192 + .../sve_intx_pred_arith_binary_sat.rs | 192 + .../sve_intx_pred_arith_unary.rs | 192 + .../A64/sve/sve_intx_string/sve_intx_match.rs | 60 + .../sve/sve_maskimm/sve_int_dup_mask_imm.rs | 12 + .../A64/sve/sve_maskimm/sve_int_log_imm.rs | 36 + .../src/A64/sve/sve_mem32/sve_mem_32b_fill.rs | 24 + .../A64/sve/sve_mem32/sve_mem_32b_gld_sv_a.rs | 120 + .../A64/sve/sve_mem32/sve_mem_32b_gld_sv_b.rs | 60 + .../A64/sve/sve_mem32/sve_mem_32b_gld_vi.rs | 240 + .../A64/sve/sve_mem32/sve_mem_32b_gld_vs.rs | 300 + .../A64/sve/sve_mem32/sve_mem_32b_gldnt_vs.rs | 120 + .../A64/sve/sve_mem32/sve_mem_32b_pfill.rs | 24 + .../A64/sve/sve_mem32/sve_mem_32b_prfm_sv.rs | 120 + .../A64/sve/sve_mem32/sve_mem_32b_prfm_vi.rs | 96 + .../src/A64/sve/sve_mem32/sve_mem_ld_dup.rs | 384 ++ .../src/A64/sve/sve_mem32/sve_mem_prfm_si.rs | 96 + .../src/A64/sve/sve_mem32/sve_mem_prfm_ss.rs | 96 + .../A64/sve/sve_mem64/sve_mem_64b_gld_sv.rs | 300 + .../A64/sve/sve_mem64/sve_mem_64b_gld_sv2.rs | 240 + .../A64/sve/sve_mem64/sve_mem_64b_gld_vi.rs | 336 ++ .../A64/sve/sve_mem64/sve_mem_64b_gld_vs.rs | 420 ++ .../A64/sve/sve_mem64/sve_mem_64b_gld_vs2.rs | 336 ++ .../A64/sve/sve_mem64/sve_mem_64b_gldnt_vs.rs | 168 + .../A64/sve/sve_mem64/sve_mem_64b_gldq_vs.rs | 24 + .../A64/sve/sve_mem64/sve_mem_64b_prfm_sv.rs | 120 + .../A64/sve/sve_mem64/sve_mem_64b_prfm_sv2.rs | 96 + .../A64/sve/sve_mem64/sve_mem_64b_prfm_vi.rs | 96 + .../src/A64/sve/sve_memcld/sve_mem_cld_si.rs | 384 ++ .../A64/sve/sve_memcld/sve_mem_cld_si_q.rs | 48 + .../src/A64/sve/sve_memcld/sve_mem_cld_ss.rs | 384 ++ .../A64/sve/sve_memcld/sve_mem_cld_ss_q.rs | 48 + .../A64/sve/sve_memcld/sve_mem_cldff_ss.rs | 384 ++ .../A64/sve/sve_memcld/sve_mem_cldnf_si.rs | 384 ++ .../A64/sve/sve_memcld/sve_mem_cldnt_si.rs | 96 + .../A64/sve/sve_memcld/sve_mem_cldnt_ss.rs | 96 + .../src/A64/sve/sve_memcld/sve_mem_eld_si.rs | 288 + .../src/A64/sve/sve_memcld/sve_mem_eld_ss.rs | 288 + .../src/A64/sve/sve_memcld/sve_mem_eldq_si.rs | 72 + .../src/A64/sve/sve_memcld/sve_mem_eldq_ss.rs | 72 + .../src/A64/sve/sve_memcld/sve_mem_ldqr_si.rs | 192 + .../src/A64/sve/sve_memcld/sve_mem_ldqr_ss.rs | 192 + .../A64/sve/sve_memcst_nt/sve_mem_cstnt_ss.rs | 96 + .../A64/sve/sve_memcst_nt/sve_mem_est_ss.rs | 288 + .../sve/sve_memsst_nt/sve_mem_sstnt_32b_vs.rs | 72 + .../sve/sve_memsst_nt/sve_mem_sstnt_64b_vs.rs | 96 + .../sve/sve_memsst_nt/sve_mem_sstq_64b_vs.rs | 24 + .../A64/sve/sve_memst_cs/sve_mem_cst_ss.rs | 162 + .../A64/sve/sve_memst_cs/sve_mem_estq_si.rs | 72 + .../A64/sve/sve_memst_cs/sve_mem_estq_ss.rs | 72 + .../A64/sve/sve_memst_cs/sve_mem_pspill.rs | 24 + .../src/A64/sve/sve_memst_cs/sve_mem_spill.rs | 24 + .../A64/sve/sve_memst_si/sve_mem_cst_si.rs | 162 + .../A64/sve/sve_memst_si/sve_mem_cstnt_si.rs | 96 + .../A64/sve/sve_memst_si/sve_mem_est_si.rs | 288 + .../A64/sve/sve_memst_ss/sve_mem_sst_sv_a.rs | 90 + .../A64/sve/sve_memst_ss/sve_mem_sst_sv_b.rs | 60 + .../A64/sve/sve_memst_ss/sve_mem_sst_vs_a.rs | 120 + .../A64/sve/sve_memst_ss/sve_mem_sst_vs_b.rs | 90 + .../A64/sve/sve_memst_ss2/sve_mem_sst_sv2.rs | 72 + .../A64/sve/sve_memst_ss2/sve_mem_sst_vi_a.rs | 96 + .../A64/sve/sve_memst_ss2/sve_mem_sst_vi_b.rs | 72 + .../A64/sve/sve_memst_ss2/sve_mem_sst_vs2.rs | 96 + .../sve_int_perm_extract_i.rs | 24 + .../sve_intx_perm_extract_i.rs | 24 + .../sve_int_perm_bin_perm_zz.rs | 144 + .../sve_int_perm_bin_long_perm_zz.rs | 108 + .../sve_perm_pred/sve_int_perm_clast_rz.rs | 48 + .../sve_perm_pred/sve_int_perm_clast_vz.rs | 48 + .../sve_perm_pred/sve_int_perm_clast_zz.rs | 48 + .../sve/sve_perm_pred/sve_int_perm_compact.rs | 48 + .../sve/sve_perm_pred/sve_int_perm_cpy_r.rs | 24 + .../sve/sve_perm_pred/sve_int_perm_cpy_v.rs | 24 + .../sve/sve_perm_pred/sve_int_perm_expand.rs | 24 + .../sve/sve_perm_pred/sve_int_perm_last_r.rs | 48 + .../sve/sve_perm_pred/sve_int_perm_last_v.rs | 48 + .../A64/sve/sve_perm_pred/sve_int_perm_rev.rs | 192 + .../sve/sve_perm_pred/sve_int_perm_revd.rs | 36 + .../sve/sve_perm_pred/sve_int_perm_splice.rs | 24 + .../sve/sve_perm_pred/sve_intx_perm_splice.rs | 24 + .../sve_int_perm_bin_perm_pp.rs | 144 + .../sve_perm_predicates/sve_int_perm_punpk.rs | 24 + .../sve_int_perm_reverse_p.rs | 18 + .../sve_perm_quads_a/sve_int_perm_dupq_i.rs | 24 + .../sve/sve_perm_quads_a/sve_int_perm_extq.rs | 18 + .../sve_perm_quads_b/sve_int_perm_binquads.rs | 120 + .../sve_perm_quads_c/sve_int_perm_tbxquads.rs | 24 + .../sve_perm_unpred_a/sve_int_perm_dup_i.rs | 24 + .../sve_int_perm_tbl_3src.rs | 48 + .../sve/sve_perm_unpred_c/sve_int_perm_tbl.rs | 24 + .../sve/sve_perm_unpred_d/sve_int_mov_p2v.rs | 72 + .../sve/sve_perm_unpred_d/sve_int_mov_v2p.rs | 72 + .../sve_perm_unpred_d/sve_int_perm_dup_r.rs | 18 + .../sve_perm_unpred_d/sve_int_perm_insrs.rs | 18 + .../sve_perm_unpred_d/sve_int_perm_insrv.rs | 18 + .../sve_int_perm_reverse_z.rs | 18 + .../sve_perm_unpred_d/sve_int_perm_unpk.rs | 72 + .../sve/sve_pred_count_a/sve_int_pcount_pn.rs | 24 + .../sve_pred_count_a/sve_int_pcount_pred.rs | 72 + .../sve/sve_pred_count_b/sve_int_count_r.rs | 36 + .../sve_pred_count_b/sve_int_count_r_sat.rs | 144 + .../sve/sve_pred_count_b/sve_int_count_v.rs | 36 + .../sve_pred_count_b/sve_int_count_v_sat.rs | 72 + .../A64/sve/sve_pred_dup/sve_int_pred_dup.rs | 42 + .../sve/sve_pred_gen_a/sve_int_pred_log.rs | 360 ++ .../A64/sve/sve_pred_gen_b/sve_int_brkp.rs | 96 + .../A64/sve/sve_pred_gen_c/sve_int_break.rs | 84 + .../A64/sve/sve_pred_gen_c/sve_int_brkn.rs | 36 + .../A64/sve/sve_pred_gen_d/sve_int_pfalse.rs | 6 + .../A64/sve/sve_pred_gen_d/sve_int_pfirst.rs | 12 + .../A64/sve/sve_pred_gen_d/sve_int_pnext.rs | 18 + .../A64/sve/sve_pred_gen_d/sve_int_ptest.rs | 12 + .../A64/sve/sve_pred_gen_d/sve_int_ptrue.rs | 36 + .../A64/sve/sve_pred_gen_d/sve_int_rdffr.rs | 24 + .../A64/sve/sve_pred_gen_d/sve_int_rdffr_2.rs | 6 + .../A64/sve/sve_pred_wrffr/sve_int_wrffr.rs | 6 + .../sve_ptr_muladd_unpred.rs | 36 + .../sve/sve_while_pn/sve_int_ctr_to_mask.rs | 48 + .../A64/sve/sve_while_pn/sve_int_pn_ptrue.rs | 12 + .../sve/sve_while_pn/sve_int_while_rr_pair.rs | 192 + .../sve/sve_while_pn/sve_int_while_rr_pn.rs | 240 + .../sve_int_dup_fpimm_pred.rs | 24 + .../sve_wideimm_pred/sve_int_dup_imm_pred.rs | 60 + .../sve_wideimm_unpred/sve_int_arith_imm0.rs | 168 + .../sve_wideimm_unpred/sve_int_arith_imm1.rs | 72 + .../sve_wideimm_unpred/sve_int_arith_imm2.rs | 18 + .../sve_wideimm_unpred/sve_int_dup_fpimm.rs | 18 + .../sve/sve_wideimm_unpred/sve_int_dup_imm.rs | 24 + aarchmrs-instructions/src/T32/b16.rs | 6 + aarchmrs-instructions/src/T32/n/addpcsp16.rs | 24 + .../src/T32/n/brc/bcond16.rs | 12 + .../src/T32/n/brc/except16.rs | 12 + aarchmrs-instructions/src/T32/n/dpint16_2l.rs | 192 + aarchmrs-instructions/src/T32/n/ldlit16.rs | 12 + aarchmrs-instructions/src/T32/n/ldst16_imm.rs | 72 + aarchmrs-instructions/src/T32/n/ldst16_reg.rs | 144 + aarchmrs-instructions/src/T32/n/ldst16_sp.rs | 24 + .../src/T32/n/ldsth16_imm.rs | 36 + aarchmrs-instructions/src/T32/n/ldstm16.rs | 24 + .../src/T32/n/misc16/adjsp16.rs | 12 + .../src/T32/n/misc16/bkpt16.rs | 6 + .../src/T32/n/misc16/cbznz16.rs | 36 + .../src/T32/n/misc16/cps16.rs | 42 + .../src/T32/n/misc16/ext16.rs | 48 + .../src/T32/n/misc16/hlt16.rs | 6 + .../src/T32/n/misc16/it16.rs | 12 + .../src/T32/n/misc16/pushpop16.rs | 24 + .../src/T32/n/misc16/rev16.rs | 36 + .../src/T32/n/misc16/setpan16.rs | 6 + .../src/T32/n/sftdpi/addsub16_1l_imm.rs | 48 + .../src/T32/n/sftdpi/addsub16_2l_imm.rs | 36 + .../src/T32/n/sftdpi/addsub16_3l.rs | 36 + .../src/T32/n/sftdpi/shift16_imm.rs | 24 + .../src/T32/n/spcd/addsub16_2h.rs | 72 + aarchmrs-instructions/src/T32/n/spcd/bx16.rs | 12 + aarchmrs-instructions/src/T32/w/bcrtrl/b.rs | 30 + .../src/T32/w/bcrtrl/bcond.rs | 36 + aarchmrs-instructions/src/T32/w/bcrtrl/bl.rs | 30 + aarchmrs-instructions/src/T32/w/bcrtrl/blx.rs | 36 + .../src/T32/w/bcrtrl/bx_jaz.rs | 6 + aarchmrs-instructions/src/T32/w/bcrtrl/cps.rs | 120 + .../src/T32/w/bcrtrl/eret.rs | 12 + .../src/T32/w/bcrtrl/except.rs | 30 + .../src/T32/w/bcrtrl/hints.rs | 6 + .../src/T32/w/bcrtrl/mrs_bank.rs | 24 + .../src/T32/w/bcrtrl/mrs_spec.rs | 12 + .../src/T32/w/bcrtrl/msr_bank.rs | 24 + .../src/T32/w/bcrtrl/msr_spec.rs | 18 + .../src/T32/w/bcrtrl/system.rs | 18 + .../src/T32/w/cpaf/advsimdext/fp_csel.rs | 432 ++ .../src/T32/w/cpaf/advsimdext/fp_extins.rs | 48 + .../src/T32/w/cpaf/advsimdext/fp_minmax.rs | 216 + .../src/T32/w/cpaf/advsimdext/fp_toint.rs | 648 +++ .../T32/w/cpaf/advsimdext/simd_3sameext.rs | 810 +++ .../src/T32/w/cpaf/advsimdext/tfloatdpmac.rs | 354 ++ .../T32/w/cpaf/advsimdext/tsimd_dotprod.rs | 360 ++ .../src/T32/w/cpaf/fpdp/fp_2r.rs | 1602 ++++++ .../src/T32/w/cpaf/fpdp/fp_3r.rs | 1404 +++++ .../src/T32/w/cpaf/fpdp/fp_movi.rs | 72 + .../src/T32/w/cpaf/simddp/simd_3same.rs | 5118 +++++++++++++++++ .../w/cpaf/simddp/t_simd_12reg/simd_1r_imm.rs | 780 +++ .../cpaf/simddp/t_simd_12reg/simd_2r_shift.rs | 1056 ++++ .../cpaf/simddp/t_simd_mulreg/simd_2r_misc.rs | 2700 +++++++++ .../w/cpaf/simddp/t_simd_mulreg/simd_2r_sc.rs | 894 +++ .../w/cpaf/simddp/t_simd_mulreg/simd_3diff.rs | 732 +++ .../cpaf/simddp/t_simd_mulreg/simd_dup_sc.rs | 60 + .../w/cpaf/simddp/t_simd_mulreg/simd_ext.rs | 84 + .../w/cpaf/simddp/t_simd_mulreg/simd_tbl.rs | 84 + .../src/T32/w/cpaf/sys_mov32/cp_mov32.rs | 72 + .../src/T32/w/cpaf/sys_mov32/fp_mov16.rs | 36 + .../src/T32/w/cpaf/sys_mov32/fp_mov32.rs | 36 + .../src/T32/w/cpaf/sys_mov32/fp_msr.rs | 24 + .../src/T32/w/cpaf/sys_mov32/simd_dup_el.rs | 126 + .../src/T32/w/cpaf/sysldst_mov64/cp_ldst.rs | 156 + .../src/T32/w/cpaf/sysldst_mov64/cp_mov64.rs | 60 + .../T32/w/cpaf/sysldst_mov64/simdfp_ldst.rs | 576 ++ .../T32/w/cpaf/sysldst_mov64/simdfp_mov64.rs | 96 + aarchmrs-instructions/src/T32/w/dpint_immm.rs | 888 +++ .../src/T32/w/dpint_shiftr.rs | 1644 ++++++ .../src/T32/w/dstd/ldastl.rs | 204 + .../src/T32/w/dstd/lddlit.rs | 36 + .../src/T32/w/dstd/ldstd_imm.rs | 60 + .../src/T32/w/dstd/ldstd_post.rs | 60 + .../src/T32/w/dstd/ldstd_pre.rs | 60 + .../src/T32/w/dstd/ldstex.rs | 42 + .../src/T32/w/dstd/ldstex_bhd.rs | 102 + aarchmrs-instructions/src/T32/w/dstd/tblbr.rs | 24 + .../src/T32/w/imm/dpint_imms.rs | 156 + aarchmrs-instructions/src/T32/w/imm/movw.rs | 60 + .../src/T32/w/imm/sat_bit.rs | 270 + .../src/T32/w/ldst/ldlit_signed.rs | 48 + .../src/T32/w/ldst/ldlit_unsigned.rs | 66 + .../src/T32/w/ldst/ldst_signed_nimm.rs | 48 + .../src/T32/w/ldst/ldst_signed_pimm.rs | 48 + .../src/T32/w/ldst/ldst_signed_post.rs | 48 + .../src/T32/w/ldst/ldst_signed_pre.rs | 48 + .../src/T32/w/ldst/ldst_signed_reg.rs | 66 + .../src/T32/w/ldst/ldst_signed_unpriv.rs | 36 + .../src/T32/w/ldst/ldst_unsigned_nimm.rs | 132 + .../src/T32/w/ldst/ldst_unsigned_pimm.rs | 132 + .../src/T32/w/ldst/ldst_unsigned_post.rs | 144 + .../src/T32/w/ldst/ldst_unsigned_pre.rs | 144 + .../src/T32/w/ldst/ldst_unsigned_reg.rs | 180 + .../src/T32/w/ldst/ldst_unsigned_unpriv.rs | 108 + aarchmrs-instructions/src/T32/w/ldstm.rs | 156 + .../src/T32/w/lmul_div/div.rs | 36 + .../src/T32/w/lmul_div/lmul.rs | 312 + .../src/T32/w/mul/mul_abd.rs | 660 +++ .../src/T32/w/reg/addsub_par.rs | 648 +++ .../src/T32/w/reg/dpint_2r.rs | 288 + .../src/T32/w/reg/extendr.rs | 252 + aarchmrs-instructions/src/T32/w/reg/shiftr.rs | 48 + .../src/T32/w/vldst/asimldall.rs | 438 ++ .../src/T32/w/vldst/asimldstms.rs | 1644 ++++++ .../src/T32/w/vldst/asimldstss.rs | 1872 ++++++ 824 files changed, 161923 insertions(+), 1 deletion(-) diff --git a/aarchmrs-gen/src/downloads.rs b/aarchmrs-gen/src/downloads.rs index 333e41ff..acb612fe 100644 --- a/aarchmrs-gen/src/downloads.rs +++ b/aarchmrs-gen/src/downloads.rs @@ -20,7 +20,7 @@ pub enum DownloadError { } pub(crate) fn ensure_archive(cache_dir: &Path) -> Result { - let archive_file = cache_dir.join(AARCHMRS_2025_12_FILE); + let archive_file = dbg!(cache_dir.join(AARCHMRS_2025_12_FILE)); if !is_valid_archive(&archive_file) { eprintln!("Downloading an archive file..."); download_archive(&archive_file)?; diff --git a/aarchmrs-gen/src/generation.rs b/aarchmrs-gen/src/generation.rs index 52ae5bc2..e6656596 100644 --- a/aarchmrs-gen/src/generation.rs +++ b/aarchmrs-gen/src/generation.rs @@ -28,6 +28,26 @@ pub fn gen_constructor(name: &str, desc: &[Bits], should_be_mask: u32) -> TokenS let should_be_mask: syn::LitInt = syn::parse_str(&format!("0b{:0w$b}u32", should_be_mask, w = 32)) .expect("internal error: malformed should_be_mask"); + let arg_metas = desc + .iter() + .filter_map(|bits| match bits { + Bits::Bit { .. } => None, + Bits::Field { name, range } => Some((name, range)), + }) + .map(|(name, range)| { + let name_offset = format_ident!("FIELD_{}_OFFSET", name.as_ref()); + let name_width = format_ident!("FIELD_{}_WIDTH", name.as_ref()); + let offset = range.start; + let width = range.width; + quote! { + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const #name_offset: u32 = #offset; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const #name_width: u32 = #width; + } + }); let expanded = quote! { #[cfg(feature = "meta")] pub const OPCODE_MASK: u32 = #mask; @@ -38,6 +58,8 @@ pub fn gen_constructor(name: &str, desc: &[Bits], should_be_mask: u32) -> TokenS #[cfg(feature = "meta")] pub const NAME: &str = #name; + #(#arg_metas)* + #[inline] pub const fn #fmt_name(#(#args),*) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32(#expr) diff --git a/aarchmrs-instructions/CHANGELOG.md b/aarchmrs-instructions/CHANGELOG.md index c43e5118..a081a1b5 100644 --- a/aarchmrs-instructions/CHANGELOG.md +++ b/aarchmrs-instructions/CHANGELOG.md @@ -4,6 +4,7 @@ ### Added - README.md is module docstring. +- `meta_field` feature flag that adds field offsets and size constants. ## [0.2.1] - 2025-08-10 diff --git a/aarchmrs-instructions/Cargo.toml b/aarchmrs-instructions/Cargo.toml index 77a4044d..680080f3 100644 --- a/aarchmrs-instructions/Cargo.toml +++ b/aarchmrs-instructions/Cargo.toml @@ -15,6 +15,7 @@ aarchmrs-types = { workspace = true } [features] default = ["A64"] meta = [] +meta_field = [] A64 = [] A32 = [] T32 = [] diff --git a/aarchmrs-instructions/src/A32/brblk/b_imm.rs b/aarchmrs-instructions/src/A32/brblk/b_imm.rs index 268ec709..461f101a 100644 --- a/aarchmrs-instructions/src/A32/brblk/b_imm.rs +++ b/aarchmrs-instructions/src/A32/brblk/b_imm.rs @@ -12,6 +12,18 @@ pub mod B_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "B_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_WIDTH: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn B_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -31,6 +43,18 @@ pub mod BL_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BL_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_WIDTH: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BL_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -50,6 +74,18 @@ pub mod BL_i_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BL_i_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_WIDTH: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; #[inline] pub const fn BL_i_A2( H: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/brblk/ldstexcept.rs b/aarchmrs-instructions/src/A32/brblk/ldstexcept.rs index 8b06eede..98bcd825 100644 --- a/aarchmrs-instructions/src/A32/brblk/ldstexcept.rs +++ b/aarchmrs-instructions/src/A32/brblk/ldstexcept.rs @@ -12,6 +12,18 @@ pub mod RFEDA_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "RFEDA_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn RFEDA_A1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -35,6 +47,18 @@ pub mod RFEDB_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "RFEDB_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn RFEDB_A1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -58,6 +82,18 @@ pub mod RFEIA_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "RFEIA_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn RFEIA_A1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -81,6 +117,18 @@ pub mod RFEIB_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "RFEIB_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn RFEIB_A1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -104,6 +152,18 @@ pub mod SRSDA_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111111100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSDA_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn SRSDA_A1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -126,6 +186,18 @@ pub mod SRSDB_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111111100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSDB_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn SRSDB_A1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -148,6 +220,18 @@ pub mod SRSIA_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111111100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSIA_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn SRSIA_A1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -170,6 +254,18 @@ pub mod SRSIB_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111111100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSIB_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn SRSIB_A1_AS( W: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/brblk/ldstm.rs b/aarchmrs-instructions/src/A32/brblk/ldstm.rs index d4e91ebe..41f6550f 100644 --- a/aarchmrs-instructions/src/A32/brblk/ldstm.rs +++ b/aarchmrs-instructions/src/A32/brblk/ldstm.rs @@ -12,6 +12,30 @@ pub mod STMDA_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STMDA_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STMDA_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod LDMDA_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDMDA_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDMDA_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod STM_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STM_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STM_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod LDM_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDM_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDM_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,36 @@ pub mod STM_u_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000001000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STM_u_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STM_u_A1_AS( cond: ::aarchmrs_types::BitValue<4>, @@ -144,6 +270,30 @@ pub mod STMDB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STMDB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STMDB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -170,6 +320,30 @@ pub mod LDMDB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDMDB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDMDB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -196,6 +370,36 @@ pub mod LDM_u_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000001000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDM_u_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDM_u_A1_AS( cond: ::aarchmrs_types::BitValue<4>, @@ -225,6 +429,30 @@ pub mod STMIB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STMIB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STMIB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -251,6 +479,30 @@ pub mod LDMIB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDMIB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDMIB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -277,6 +529,42 @@ pub mod LDM_e_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDM_e_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDM_e_A1_AS( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/advsimdext/floatdpmac.rs b/aarchmrs-instructions/src/A32/cops_as/advsimdext/floatdpmac.rs index bb7915fa..40e6a5dd 100644 --- a/aarchmrs-instructions/src/A32/cops_as/advsimdext/floatdpmac.rs +++ b/aarchmrs-instructions/src/A32/cops_as/advsimdext/floatdpmac.rs @@ -12,6 +12,48 @@ pub mod VCMLA_s_A1_DH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_A1_DH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_A1_DH( D: ::aarchmrs_types::BitValue<1>, @@ -46,6 +88,48 @@ pub mod VCMLA_s_A1_DS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_A1_DS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_A1_DS( D: ::aarchmrs_types::BitValue<1>, @@ -80,6 +164,48 @@ pub mod VCMLA_s_A1_QH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_A1_QH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_A1_QH( D: ::aarchmrs_types::BitValue<1>, @@ -114,6 +240,48 @@ pub mod VCMLA_s_A1_QS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_A1_QS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_A1_QS( D: ::aarchmrs_types::BitValue<1>, @@ -148,6 +316,42 @@ pub mod VFMAL_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -181,6 +385,42 @@ pub mod VFMAL_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -214,6 +454,42 @@ pub mod VFMSL_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -247,6 +523,42 @@ pub mod VFMSL_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -280,6 +592,48 @@ pub mod VFMA_bfs_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_bfs_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_bfs_A1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcsel.rs b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcsel.rs index 0fb04e06..3f1292ad 100644 --- a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcsel.rs +++ b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcsel.rs @@ -12,6 +12,42 @@ pub mod VSELEQ_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELEQ_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELEQ_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VSELEQ_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELEQ_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELEQ_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VSELEQ_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELEQ_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELEQ_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VSELGE_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGE_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGE_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VSELGE_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGE_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGE_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VSELGE_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGE_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGE_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -210,6 +426,42 @@ pub mod VSELGT_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGT_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGT_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -243,6 +495,42 @@ pub mod VSELGT_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGT_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGT_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -276,6 +564,42 @@ pub mod VSELGT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -309,6 +633,42 @@ pub mod VSELVS_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELVS_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELVS_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -342,6 +702,42 @@ pub mod VSELVS_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELVS_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELVS_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -375,6 +771,42 @@ pub mod VSELVS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELVS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELVS_A1_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcvtrnd.rs b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcvtrnd.rs index 9c8eee37..f4b73428 100644 --- a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcvtrnd.rs +++ b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpcvtrnd.rs @@ -12,6 +12,30 @@ pub mod VRINTA_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod VRINTA_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -68,6 +116,30 @@ pub mod VRINTA_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -96,6 +168,30 @@ pub mod VRINTN_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -124,6 +220,30 @@ pub mod VRINTN_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -152,6 +272,30 @@ pub mod VRINTN_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -180,6 +324,30 @@ pub mod VRINTP_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -208,6 +376,30 @@ pub mod VRINTP_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -236,6 +428,30 @@ pub mod VRINTP_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -264,6 +480,30 @@ pub mod VRINTM_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -292,6 +532,30 @@ pub mod VRINTM_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -320,6 +584,30 @@ pub mod VRINTM_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -348,6 +636,36 @@ pub mod VCVTA_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -379,6 +697,36 @@ pub mod VCVTA_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -410,6 +758,36 @@ pub mod VCVTA_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -441,6 +819,36 @@ pub mod VCVTN_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -472,6 +880,36 @@ pub mod VCVTN_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -503,6 +941,36 @@ pub mod VCVTN_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -534,6 +1002,36 @@ pub mod VCVTP_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -565,6 +1063,36 @@ pub mod VCVTP_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -596,6 +1124,36 @@ pub mod VCVTP_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -627,6 +1185,36 @@ pub mod VCVTM_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_vfp_A1_H( D: ::aarchmrs_types::BitValue<1>, @@ -658,6 +1246,36 @@ pub mod VCVTM_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_vfp_A1_S( D: ::aarchmrs_types::BitValue<1>, @@ -689,6 +1307,36 @@ pub mod VCVTM_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_vfp_A1_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpextins.rs b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpextins.rs index 8c7850a8..957bf040 100644 --- a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpextins.rs +++ b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpextins.rs @@ -12,6 +12,30 @@ pub mod VMOVX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOVX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOVX_A1( D: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod VINS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VINS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VINS_A1( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpminmaxnm.rs b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpminmaxnm.rs index 08ce4801..71a78402 100644 --- a/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpminmaxnm.rs +++ b/aarchmrs-instructions/src/A32/cops_as/advsimdext/fpminmaxnm.rs @@ -12,6 +12,42 @@ pub mod VMAXNM_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_A2_H( D: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VMAXNM_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_A2_S( D: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VMAXNM_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VMINNM_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_A2_H( D: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VMINNM_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_A2_S( D: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VMINNM_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_A2_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd3reg_sameext.rs b/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd3reg_sameext.rs index 2455cb0f..7cde7742 100644 --- a/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd3reg_sameext.rs +++ b/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd3reg_sameext.rs @@ -12,6 +12,54 @@ pub mod VCADD_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCADD_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; #[inline] pub const fn VCADD_A1_D( rot: ::aarchmrs_types::BitValue<1>, @@ -50,6 +98,54 @@ pub mod VCADD_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCADD_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; #[inline] pub const fn VCADD_A1_Q( rot: ::aarchmrs_types::BitValue<1>, @@ -88,6 +184,42 @@ pub mod VMMLA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMMLA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMMLA_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -121,6 +253,42 @@ pub mod VDOT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -154,6 +322,42 @@ pub mod VDOT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -187,6 +391,42 @@ pub mod VFMAL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -220,6 +460,42 @@ pub mod VFMAL_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -253,6 +529,42 @@ pub mod VSMMLA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSMMLA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSMMLA_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -286,6 +598,42 @@ pub mod VUMMLA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUMMLA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUMMLA_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -319,6 +667,42 @@ pub mod VSDOT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -352,6 +736,42 @@ pub mod VSDOT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -385,6 +805,42 @@ pub mod VUDOT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -418,6 +874,42 @@ pub mod VUDOT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -451,6 +943,48 @@ pub mod VFMA_bf_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_bf_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_bf_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -485,6 +1019,42 @@ pub mod VFMSL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -518,6 +1088,42 @@ pub mod VFMSL_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -551,6 +1157,42 @@ pub mod VUSMMLA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSMMLA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSMMLA_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -584,6 +1226,42 @@ pub mod VUSDOT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -617,6 +1295,42 @@ pub mod VUSDOT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -650,6 +1364,54 @@ pub mod VCMLA_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; #[inline] pub const fn VCMLA_A1_D( rot: ::aarchmrs_types::BitValue<2>, @@ -687,6 +1449,54 @@ pub mod VCMLA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; #[inline] pub const fn VCMLA_A1_Q( rot: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd_dotprod.rs b/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd_dotprod.rs index 3f93a75b..0ed2ed62 100644 --- a/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd_dotprod.rs +++ b/aarchmrs-instructions/src/A32/cops_as/advsimdext/simd_dotprod.rs @@ -12,6 +12,42 @@ pub mod VDOT_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VDOT_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VSDOT_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VSDOT_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VUDOT_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VUDOT_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -210,6 +426,42 @@ pub mod VUSDOT_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -243,6 +495,42 @@ pub mod VUSDOT_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -276,6 +564,42 @@ pub mod VSUDOT_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUDOT_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUDOT_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -309,6 +633,42 @@ pub mod VSUDOT_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUDOT_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUDOT_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp2reg.rs b/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp2reg.rs index 9c54c475..bb2708fc 100644 --- a/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp2reg.rs +++ b/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp2reg.rs @@ -12,6 +12,36 @@ pub mod VABS_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VABS_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -42,6 +72,36 @@ pub mod VABS_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VABS_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -72,6 +132,36 @@ pub mod VABS_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VABS_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -102,6 +192,36 @@ pub mod VMOV_r_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_r_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_r_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -132,6 +252,36 @@ pub mod VMOV_r_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_r_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_r_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -162,6 +312,36 @@ pub mod VNEG_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNEG_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -192,6 +372,36 @@ pub mod VNEG_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNEG_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -222,6 +432,36 @@ pub mod VNEG_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNEG_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -252,6 +492,36 @@ pub mod VSQRT_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSQRT_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSQRT_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -282,6 +552,36 @@ pub mod VSQRT_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSQRT_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSQRT_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -312,6 +612,36 @@ pub mod VSQRT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSQRT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSQRT_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -342,6 +672,36 @@ pub mod VCVTB_A1_SH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_A1_SH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTB_A1_SH( cond: ::aarchmrs_types::BitValue<4>, @@ -372,6 +732,36 @@ pub mod VCVTB_A1_DH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_A1_DH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTB_A1_DH( cond: ::aarchmrs_types::BitValue<4>, @@ -402,6 +792,36 @@ pub mod VCVTB_A1_HS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_A1_HS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTB_A1_HS( cond: ::aarchmrs_types::BitValue<4>, @@ -432,6 +852,36 @@ pub mod VCVTB_A1_HD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_A1_HD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTB_A1_HD( cond: ::aarchmrs_types::BitValue<4>, @@ -462,6 +912,36 @@ pub mod VCVTT_A1_SH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_A1_SH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTT_A1_SH( cond: ::aarchmrs_types::BitValue<4>, @@ -492,6 +972,36 @@ pub mod VCVTT_A1_DH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_A1_DH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTT_A1_DH( cond: ::aarchmrs_types::BitValue<4>, @@ -522,6 +1032,36 @@ pub mod VCVTT_A1_HS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_A1_HS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTT_A1_HS( cond: ::aarchmrs_types::BitValue<4>, @@ -552,6 +1092,36 @@ pub mod VCVTT_A1_HD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_A1_HD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTT_A1_HD( cond: ::aarchmrs_types::BitValue<4>, @@ -582,6 +1152,36 @@ pub mod VCVTB_A1_bfs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_A1_bfs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTB_A1_bfs( cond: ::aarchmrs_types::BitValue<4>, @@ -612,6 +1212,36 @@ pub mod VCVTT_A1_bfs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_A1_bfs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTT_A1_bfs( cond: ::aarchmrs_types::BitValue<4>, @@ -642,6 +1272,36 @@ pub mod VCMP_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMP_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -672,6 +1332,36 @@ pub mod VCMP_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMP_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -702,6 +1392,36 @@ pub mod VCMP_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMP_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -732,6 +1452,36 @@ pub mod VCMPE_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMPE_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -762,6 +1512,36 @@ pub mod VCMPE_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMPE_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -792,6 +1572,36 @@ pub mod VCMPE_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMPE_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -822,6 +1632,24 @@ pub mod VCMP_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMP_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -847,6 +1675,24 @@ pub mod VCMP_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMP_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -872,6 +1718,24 @@ pub mod VCMP_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMP_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -897,6 +1761,24 @@ pub mod VCMPE_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMPE_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -922,6 +1804,24 @@ pub mod VCMPE_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMPE_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -947,6 +1847,24 @@ pub mod VCMPE_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCMPE_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -972,6 +1890,36 @@ pub mod VRINTR_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTR_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTR_vfp_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1002,6 +1950,36 @@ pub mod VRINTR_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTR_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTR_vfp_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1032,6 +2010,36 @@ pub mod VRINTR_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTR_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTR_vfp_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1062,6 +2070,36 @@ pub mod VRINTZ_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTZ_vfp_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1092,6 +2130,36 @@ pub mod VRINTZ_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTZ_vfp_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1122,6 +2190,36 @@ pub mod VRINTZ_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTZ_vfp_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1152,6 +2250,36 @@ pub mod VRINTX_vfp_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_vfp_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTX_vfp_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1182,6 +2310,36 @@ pub mod VRINTX_vfp_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_vfp_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTX_vfp_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1212,6 +2370,36 @@ pub mod VRINTX_vfp_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_vfp_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VRINTX_vfp_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1242,6 +2430,36 @@ pub mod VCVT_ds_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_ds_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_ds_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -1272,6 +2490,36 @@ pub mod VCVT_sd_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_sd_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_sd_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -1302,6 +2550,42 @@ pub mod VCVT_vi_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_vi_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_vi_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1335,6 +2619,42 @@ pub mod VCVT_vi_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_vi_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_vi_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1368,6 +2688,42 @@ pub mod VCVT_vi_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_vi_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_vi_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1401,6 +2757,36 @@ pub mod VJCVT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VJCVT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VJCVT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -1431,6 +2817,48 @@ pub mod VCVT_toxv_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_toxv_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_toxv_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1466,6 +2894,48 @@ pub mod VCVT_xv_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xv_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_xv_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1501,6 +2971,48 @@ pub mod VCVT_toxv_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_toxv_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_toxv_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1536,6 +3048,48 @@ pub mod VCVT_xv_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xv_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_xv_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1571,6 +3125,48 @@ pub mod VCVT_toxv_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_toxv_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_toxv_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1606,6 +3202,48 @@ pub mod VCVT_xv_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xv_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_xv_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1641,6 +3279,36 @@ pub mod VCVTR_uiv_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_uiv_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTR_uiv_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1671,6 +3339,36 @@ pub mod VCVTR_siv_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_siv_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTR_siv_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1701,6 +3399,36 @@ pub mod VCVTR_uiv_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_uiv_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTR_uiv_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1731,6 +3459,36 @@ pub mod VCVTR_siv_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_siv_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTR_siv_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1761,6 +3519,36 @@ pub mod VCVTR_uiv_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_uiv_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTR_uiv_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1791,6 +3579,36 @@ pub mod VCVTR_siv_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_siv_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVTR_siv_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1821,6 +3639,36 @@ pub mod VCVT_uiv_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_uiv_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_uiv_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1851,6 +3699,36 @@ pub mod VCVT_siv_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_siv_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_siv_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1881,6 +3759,36 @@ pub mod VCVT_uiv_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_uiv_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_uiv_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1911,6 +3819,36 @@ pub mod VCVT_siv_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_siv_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_siv_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1941,6 +3879,36 @@ pub mod VCVT_uiv_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_uiv_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_uiv_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1971,6 +3939,36 @@ pub mod VCVT_siv_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_siv_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VCVT_siv_A1_D( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp3reg.rs b/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp3reg.rs index f621a856..935bf47d 100644 --- a/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp3reg.rs +++ b/aarchmrs-instructions/src/A32/cops_as/fpdp/fpdp3reg.rs @@ -12,6 +12,48 @@ pub mod VMLA_f_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMLA_f_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -47,6 +89,48 @@ pub mod VMLA_f_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMLA_f_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -82,6 +166,48 @@ pub mod VMLA_f_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMLA_f_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -117,6 +243,48 @@ pub mod VMLS_f_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMLS_f_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -152,6 +320,48 @@ pub mod VMLS_f_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMLS_f_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -187,6 +397,48 @@ pub mod VMLS_f_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMLS_f_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -222,6 +474,48 @@ pub mod VNMLS_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLS_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMLS_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -257,6 +551,48 @@ pub mod VNMLS_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLS_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMLS_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -292,6 +628,48 @@ pub mod VNMLS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMLS_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -327,6 +705,48 @@ pub mod VNMLA_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLA_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMLA_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -362,6 +782,48 @@ pub mod VNMLA_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLA_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMLA_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -397,6 +859,48 @@ pub mod VNMLA_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLA_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMLA_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -432,6 +936,48 @@ pub mod VMUL_f_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMUL_f_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -467,6 +1013,48 @@ pub mod VMUL_f_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMUL_f_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -502,6 +1090,48 @@ pub mod VMUL_f_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMUL_f_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -537,6 +1167,48 @@ pub mod VNMUL_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMUL_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMUL_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -572,6 +1244,48 @@ pub mod VNMUL_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMUL_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMUL_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -607,6 +1321,48 @@ pub mod VNMUL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMUL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VNMUL_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -642,6 +1398,48 @@ pub mod VADD_f_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VADD_f_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -677,6 +1475,48 @@ pub mod VADD_f_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VADD_f_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -712,6 +1552,48 @@ pub mod VADD_f_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VADD_f_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -747,6 +1629,48 @@ pub mod VSUB_f_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSUB_f_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -782,6 +1706,48 @@ pub mod VSUB_f_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSUB_f_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -817,6 +1783,48 @@ pub mod VSUB_f_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSUB_f_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -852,6 +1860,48 @@ pub mod VDIV_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDIV_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VDIV_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -887,6 +1937,48 @@ pub mod VDIV_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDIV_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VDIV_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -922,6 +2014,48 @@ pub mod VDIV_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDIV_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VDIV_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -957,6 +2091,48 @@ pub mod VFNMS_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMS_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFNMS_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -992,6 +2168,48 @@ pub mod VFNMS_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMS_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFNMS_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1027,6 +2245,48 @@ pub mod VFNMS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFNMS_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1062,6 +2322,48 @@ pub mod VFNMA_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMA_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFNMA_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1097,6 +2399,48 @@ pub mod VFNMA_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMA_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFNMA_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1132,6 +2476,48 @@ pub mod VFNMA_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMA_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFNMA_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1167,6 +2553,48 @@ pub mod VFMA_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFMA_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1202,6 +2630,48 @@ pub mod VFMA_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFMA_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1237,6 +2707,48 @@ pub mod VFMA_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFMA_A2_D( cond: ::aarchmrs_types::BitValue<4>, @@ -1272,6 +2784,48 @@ pub mod VFMS_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFMS_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -1307,6 +2861,48 @@ pub mod VFMS_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFMS_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -1342,6 +2938,48 @@ pub mod VFMS_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VFMS_A2_D( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/fpdp/fpimm.rs b/aarchmrs-instructions/src/A32/cops_as/fpdp/fpimm.rs index 0aa35848..a6fb39d7 100644 --- a/aarchmrs-instructions/src/A32/cops_as/fpdp/fpimm.rs +++ b/aarchmrs-instructions/src/A32/cops_as/fpdp/fpimm.rs @@ -12,6 +12,36 @@ pub mod VMOV_i_A2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000010100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_i_A2_H( cond: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod VMOV_i_A2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000010100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_i_A2_S( cond: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,36 @@ pub mod VMOV_i_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000010100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_i_A2_D( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/svcall/svc.rs b/aarchmrs-instructions/src/A32/cops_as/svcall/svc.rs index 7d532d50..0684fec5 100644 --- a/aarchmrs-instructions/src/A32/cops_as/svcall/svc.rs +++ b/aarchmrs-instructions/src/A32/cops_as/svcall/svc.rs @@ -12,6 +12,18 @@ pub mod SVC_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SVC_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm24_WIDTH: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SVC_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movcpgp32.rs b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movcpgp32.rs index 02e01c7d..0d8d22ca 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movcpgp32.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movcpgp32.rs @@ -12,6 +12,48 @@ pub mod MCR_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MCR_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MCR_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -46,6 +88,48 @@ pub mod MRC_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRC_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MRC_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp16.rs b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp16.rs index 9bdb2d4e..be003bb8 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp16.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp16.rs @@ -12,6 +12,30 @@ pub mod VMOV_toh_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_toh_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_toh_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod VMOV_h_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_h_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_h_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp32.rs b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp32.rs index 269f1672..c13ff410 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp32.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpgp32.rs @@ -12,6 +12,30 @@ pub mod VMOV_tos_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_tos_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_tos_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod VMOV_s_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_s_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_s_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpsr.rs b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpsr.rs index 8df6edc1..a23ffadd 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpsr.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movfpsr.rs @@ -12,6 +12,24 @@ pub mod VMSR_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000011101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMSR_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMSR_A1_AS( cond: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod VMRS_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000011101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMRS_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMRS_A1_AS( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movsimdgp.rs b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movsimdgp.rs index 4d0350c6..47fd1858 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movsimdgp.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sys_mov32/movsimdgp.rs @@ -12,6 +12,42 @@ pub mod VMOV_rs_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_rs_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_rs_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,48 @@ pub mod VMOV_sr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_sr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_sr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -78,6 +156,42 @@ pub mod VDUP_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VDUP_r_A1_Q( cond: ::aarchmrs_types::BitValue<4>, @@ -111,6 +225,42 @@ pub mod VDUP_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VDUP_r_A1_D( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstcp.rs b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstcp.rs index 36d6de42..2c26faa5 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstcp.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstcp.rs @@ -12,6 +12,36 @@ pub mod LDC_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDC_l_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,30 @@ pub mod STC_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STC_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -68,6 +122,30 @@ pub mod STC_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STC_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -95,6 +173,30 @@ pub mod STC_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STC_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -122,6 +224,24 @@ pub mod STC_A1_unind { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_A1_unind"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STC_A1_unind( cond: ::aarchmrs_types::BitValue<4>, @@ -146,6 +266,30 @@ pub mod LDC_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDC_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -173,6 +317,30 @@ pub mod LDC_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDC_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -200,6 +368,30 @@ pub mod LDC_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDC_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -227,6 +419,24 @@ pub mod LDC_i_A1_unind { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_A1_unind"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDC_i_A1_unind( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstsimdfp.rs b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstsimdfp.rs index 408e6aca..a186bc3f 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstsimdfp.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/ldstsimdfp.rs @@ -12,6 +12,36 @@ pub mod VSTMDB_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTMDB_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSTMDB_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,42 @@ pub mod VSTM_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTM_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSTM_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -72,6 +138,36 @@ pub mod VSTMDB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTMDB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSTMDB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -102,6 +198,42 @@ pub mod VSTM_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTM_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSTM_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -134,6 +266,36 @@ pub mod FSTMDBX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSTMDBX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn FSTMDBX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -164,6 +326,42 @@ pub mod FSTMIAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSTMIAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn FSTMIAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -196,6 +394,36 @@ pub mod VLDMDB_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDMDB_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDMDB_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -225,6 +453,42 @@ pub mod VLDM_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDM_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDM_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -256,6 +520,36 @@ pub mod VLDMDB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDMDB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDMDB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -286,6 +580,42 @@ pub mod VLDM_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDM_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDM_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -318,6 +648,36 @@ pub mod FLDMDBX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FLDMDBX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn FLDMDBX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -348,6 +708,42 @@ pub mod FLDMIAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FLDMIAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn FLDMIAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -380,6 +776,42 @@ pub mod VSTR_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTR_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSTR_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -411,6 +843,42 @@ pub mod VSTR_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTR_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSTR_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -442,6 +910,42 @@ pub mod VSTR_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTR_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VSTR_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -473,6 +977,42 @@ pub mod VLDR_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDR_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -504,6 +1044,42 @@ pub mod VLDR_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDR_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -535,6 +1111,42 @@ pub mod VLDR_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDR_A1_D( cond: ::aarchmrs_types::BitValue<4>, @@ -566,6 +1178,36 @@ pub mod VLDR_l_A1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_l_A1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDR_l_A1_H( cond: ::aarchmrs_types::BitValue<4>, @@ -595,6 +1237,36 @@ pub mod VLDR_l_A1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_l_A1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDR_l_A1_S( cond: ::aarchmrs_types::BitValue<4>, @@ -624,6 +1296,36 @@ pub mod VLDR_l_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_l_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VLDR_l_A1_D( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movcpgp64.rs b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movcpgp64.rs index 8221f32f..f66ff29f 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movcpgp64.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movcpgp64.rs @@ -12,6 +12,42 @@ pub mod MCRR_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MCRR_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MCRR_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -42,6 +78,42 @@ pub mod MRRC_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRRC_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MRRC_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movsimdfpgp64.rs b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movsimdfpgp64.rs index 8a9ea132..4d0e038b 100644 --- a/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movsimdfpgp64.rs +++ b/aarchmrs-instructions/src/A32/cops_as/sysldst_mov64/movsimdfpgp64.rs @@ -12,6 +12,36 @@ pub mod VMOV_toss_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_toss_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_toss_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod VMOV_ss_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_ss_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_ss_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,36 @@ pub mod VMOV_tod_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_tod_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_tod_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -99,6 +189,36 @@ pub mod VMOV_d_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_d_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_d_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpimm/intdp1reg_imm.rs b/aarchmrs-instructions/src/A32/dp/dpimm/intdp1reg_imm.rs index ef0ba786..235936ac 100644 --- a/aarchmrs-instructions/src/A32/dp/dpimm/intdp1reg_imm.rs +++ b/aarchmrs-instructions/src/A32/dp/dpimm/intdp1reg_imm.rs @@ -12,6 +12,24 @@ pub mod TST_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TST_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod TEQ_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEQ_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TEQ_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod CMP_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMP_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod CMN_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMN_i_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpimm/intdp2reg_imm.rs b/aarchmrs-instructions/src/A32/dp/dpimm/intdp2reg_imm.rs index 11689540..f5d27cea 100644 --- a/aarchmrs-instructions/src/A32/dp/dpimm/intdp2reg_imm.rs +++ b/aarchmrs-instructions/src/A32/dp/dpimm/intdp2reg_imm.rs @@ -12,6 +12,30 @@ pub mod AND_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn AND_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -37,6 +61,30 @@ pub mod ANDS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ANDS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -62,6 +110,30 @@ pub mod EOR_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EOR_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -87,6 +159,30 @@ pub mod EORS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EORS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EORS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -112,6 +208,30 @@ pub mod SUB_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -137,6 +257,30 @@ pub mod SUBS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -162,6 +306,24 @@ pub mod SUB_SP_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_SP_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -185,6 +347,24 @@ pub mod SUBS_SP_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_SP_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_SP_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -208,6 +388,24 @@ pub mod ADR_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADR_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADR_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -231,6 +429,30 @@ pub mod RSB_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSB_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -256,6 +478,30 @@ pub mod RSBS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSBS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSBS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -281,6 +527,30 @@ pub mod ADD_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -306,6 +576,30 @@ pub mod ADDS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -331,6 +625,24 @@ pub mod ADD_SP_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_SP_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -354,6 +666,24 @@ pub mod ADDS_SP_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_SP_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_SP_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -377,6 +707,24 @@ pub mod ADR_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADR_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADR_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -400,6 +748,30 @@ pub mod ADC_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADC_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -425,6 +797,30 @@ pub mod ADCS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADCS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -450,6 +846,30 @@ pub mod SBC_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBC_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -475,6 +895,30 @@ pub mod SBCS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBCS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -500,6 +944,30 @@ pub mod RSC_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSC_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSC_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -525,6 +993,30 @@ pub mod RSCS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSCS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSCS_i_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpimm/log2reg_imm.rs b/aarchmrs-instructions/src/A32/dp/dpimm/log2reg_imm.rs index 203e2e70..bd8803a8 100644 --- a/aarchmrs-instructions/src/A32/dp/dpimm/log2reg_imm.rs +++ b/aarchmrs-instructions/src/A32/dp/dpimm/log2reg_imm.rs @@ -12,6 +12,30 @@ pub mod ORR_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORR_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -37,6 +61,30 @@ pub mod ORRS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORRS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORRS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -62,6 +110,24 @@ pub mod MOV_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOV_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -85,6 +151,24 @@ pub mod MOVS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOVS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -108,6 +192,30 @@ pub mod BIC_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BIC_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -133,6 +241,30 @@ pub mod BICS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BICS_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -158,6 +290,24 @@ pub mod MVN_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVN_i_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -181,6 +331,24 @@ pub mod MVNS_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNS_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVNS_i_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpimm/movsr_hint_imm.rs b/aarchmrs-instructions/src/A32/dp/dpimm/movsr_hint_imm.rs index eaa2661a..9a6f8a40 100644 --- a/aarchmrs-instructions/src/A32/dp/dpimm/movsr_hint_imm.rs +++ b/aarchmrs-instructions/src/A32/dp/dpimm/movsr_hint_imm.rs @@ -12,6 +12,30 @@ pub mod MSR_i_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSR_i_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MSR_i_A1_AS( cond: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,12 @@ pub mod NOP_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "NOP_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn NOP_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -55,6 +85,12 @@ pub mod YIELD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "YIELD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn YIELD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -73,6 +109,12 @@ pub mod WFE_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "WFE_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn WFE_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -89,6 +131,12 @@ pub mod WFI_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "WFI_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn WFI_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -105,6 +153,12 @@ pub mod SEV_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SEV_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SEV_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -121,6 +175,12 @@ pub mod SEVL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SEVL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SEVL_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -137,6 +197,12 @@ pub mod ESB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ESB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ESB_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -153,6 +219,12 @@ pub mod TSB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TSB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TSB_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -169,6 +241,12 @@ pub mod CSDB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSDB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CSDB_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -185,6 +263,12 @@ pub mod CLRBHB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLRBHB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CLRBHB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -203,6 +287,18 @@ pub mod DBG_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DBG_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn DBG_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpimm/movw.rs b/aarchmrs-instructions/src/A32/dp/dpimm/movw.rs index ec51ec59..7550725f 100644 --- a/aarchmrs-instructions/src/A32/dp/dpimm/movw.rs +++ b/aarchmrs-instructions/src/A32/dp/dpimm/movw.rs @@ -12,6 +12,30 @@ pub mod MOV_i_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_i_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOV_i_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -37,6 +61,30 @@ pub mod MOVT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOVT_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/blx_reg.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/blx_reg.rs index acd421ed..108f9599 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/blx_reg.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/blx_reg.rs @@ -12,6 +12,18 @@ pub mod BLX_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BLX_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BLX_r_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/bx_reg.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/bx_reg.rs index 02d0e96d..34c548a7 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/bx_reg.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/bx_reg.rs @@ -12,6 +12,18 @@ pub mod BX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BX_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/bxj_reg.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/bxj_reg.rs index 8d76255d..21cec5dc 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/bxj_reg.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/bxj_reg.rs @@ -12,6 +12,18 @@ pub mod BXJ_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BXJ_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BXJ_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/clz.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/clz.rs index f6206b16..a3991409 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/clz.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/clz.rs @@ -12,6 +12,24 @@ pub mod CLZ_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLZ_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CLZ_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/crc32.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/crc32.rs index 998a581f..e91e8f6f 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/crc32.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/crc32.rs @@ -12,6 +12,30 @@ pub mod CRC32B_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32B_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32B_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod CRC32H_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32H_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32H_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod CRC32W_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32W_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32W_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod CRC32CB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32CB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod CRC32CH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32CH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod CRC32CW_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CW_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32CW_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/eret.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/eret.rs index 842b14b3..9d48f9d4 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/eret.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/eret.rs @@ -12,6 +12,12 @@ pub mod ERET_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "ERET_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ERET_A1(cond: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/except.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/except.rs index 66743d53..7002ec2b 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/except.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/except.rs @@ -12,6 +12,24 @@ pub mod HLT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "HLT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn HLT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod BKPT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BKPT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BKPT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod HVC_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "HVC_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn HVC_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,18 @@ pub mod SMC_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMC_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMC_A1_AS( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/intsat.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/intsat.rs index 3e948a43..95884517 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/intsat.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/intsat.rs @@ -12,6 +12,30 @@ pub mod QADD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QADD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QADD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod QSUB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSUB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QSUB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod QDADD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QDADD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QDADD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod QDSUB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QDSUB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QDSUB_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpmisc/movsr_reg.rs b/aarchmrs-instructions/src/A32/dp/dpmisc/movsr_reg.rs index 4d7956f9..8af3340c 100644 --- a/aarchmrs-instructions/src/A32/dp/dpmisc/movsr_reg.rs +++ b/aarchmrs-instructions/src/A32/dp/dpmisc/movsr_reg.rs @@ -12,6 +12,24 @@ pub mod MRS_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000110100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRS_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MRS_A1_AS( cond: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,36 @@ pub mod MRS_br_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRS_br_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MRS_br_A1_AS( cond: ::aarchmrs_types::BitValue<4>, @@ -67,6 +115,30 @@ pub mod MSR_r_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111110100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSR_r_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MSR_r_A1_AS( cond: ::aarchmrs_types::BitValue<4>, @@ -94,6 +166,36 @@ pub mod MSR_br_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSR_br_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MSR_br_A1_AS( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpregis/intdp2reg_immsh.rs b/aarchmrs-instructions/src/A32/dp/dpregis/intdp2reg_immsh.rs index 4a378d41..e8a16b30 100644 --- a/aarchmrs-instructions/src/A32/dp/dpregis/intdp2reg_immsh.rs +++ b/aarchmrs-instructions/src/A32/dp/dpregis/intdp2reg_immsh.rs @@ -12,6 +12,24 @@ pub mod TST_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TST_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,36 @@ pub mod TST_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TST_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -65,6 +113,24 @@ pub mod TEQ_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEQ_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TEQ_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -89,6 +155,36 @@ pub mod TEQ_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEQ_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TEQ_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -118,6 +214,24 @@ pub mod CMP_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMP_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -142,6 +256,36 @@ pub mod CMP_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMP_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -171,6 +315,24 @@ pub mod CMN_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMN_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -195,6 +357,36 @@ pub mod CMN_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMN_r_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpregis/intdp3reg_immsh.rs b/aarchmrs-instructions/src/A32/dp/dpregis/intdp3reg_immsh.rs index b3ec03f4..bf8e67dc 100644 --- a/aarchmrs-instructions/src/A32/dp/dpregis/intdp3reg_immsh.rs +++ b/aarchmrs-instructions/src/A32/dp/dpregis/intdp3reg_immsh.rs @@ -12,6 +12,30 @@ pub mod AND_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn AND_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,42 @@ pub mod AND_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn AND_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -68,6 +128,30 @@ pub mod ANDS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ANDS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -94,6 +178,42 @@ pub mod ANDS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ANDS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -124,6 +244,30 @@ pub mod EOR_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EOR_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -150,6 +294,42 @@ pub mod EOR_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EOR_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -180,6 +360,30 @@ pub mod EORS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EORS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EORS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -206,6 +410,42 @@ pub mod EORS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EORS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EORS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -236,6 +476,30 @@ pub mod SUB_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -262,6 +526,42 @@ pub mod SUB_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -292,6 +592,30 @@ pub mod SUBS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -318,6 +642,42 @@ pub mod SUBS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -348,6 +708,24 @@ pub mod SUB_SP_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_SP_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -372,6 +750,36 @@ pub mod SUB_SP_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_SP_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -400,6 +808,24 @@ pub mod SUBS_SP_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_SP_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_SP_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -424,6 +850,36 @@ pub mod SUBS_SP_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_SP_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_SP_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -452,6 +908,30 @@ pub mod RSB_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSB_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -478,6 +958,42 @@ pub mod RSB_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSB_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -508,6 +1024,30 @@ pub mod RSBS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSBS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSBS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -534,6 +1074,42 @@ pub mod RSBS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSBS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSBS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -564,6 +1140,30 @@ pub mod ADD_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -590,6 +1190,42 @@ pub mod ADD_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -620,6 +1256,30 @@ pub mod ADDS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -646,6 +1306,42 @@ pub mod ADDS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -676,6 +1372,24 @@ pub mod ADD_SP_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_SP_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -700,6 +1414,36 @@ pub mod ADD_SP_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_SP_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -728,6 +1472,24 @@ pub mod ADDS_SP_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_SP_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_SP_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -752,6 +1514,36 @@ pub mod ADDS_SP_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_SP_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_SP_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -780,6 +1572,30 @@ pub mod ADC_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADC_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -806,6 +1622,42 @@ pub mod ADC_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADC_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -836,6 +1688,30 @@ pub mod ADCS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADCS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -862,6 +1738,42 @@ pub mod ADCS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADCS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -892,6 +1804,30 @@ pub mod SBC_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBC_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -918,6 +1854,42 @@ pub mod SBC_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBC_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -948,6 +1920,30 @@ pub mod SBCS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBCS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -974,6 +1970,42 @@ pub mod SBCS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBCS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -1004,6 +2036,30 @@ pub mod RSC_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSC_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSC_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -1030,6 +2086,42 @@ pub mod RSC_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSC_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSC_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -1060,6 +2152,30 @@ pub mod RSCS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSCS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSCS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -1086,6 +2202,42 @@ pub mod RSCS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSCS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSCS_r_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpregis/logic3reg_immsh.rs b/aarchmrs-instructions/src/A32/dp/dpregis/logic3reg_immsh.rs index afafe5aa..a28bdd5c 100644 --- a/aarchmrs-instructions/src/A32/dp/dpregis/logic3reg_immsh.rs +++ b/aarchmrs-instructions/src/A32/dp/dpregis/logic3reg_immsh.rs @@ -12,6 +12,30 @@ pub mod ORR_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORR_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,42 @@ pub mod ORR_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORR_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -68,6 +128,30 @@ pub mod ORRS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORRS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORRS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -94,6 +178,42 @@ pub mod ORRS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORRS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORRS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -124,6 +244,24 @@ pub mod MOV_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOV_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -148,6 +286,36 @@ pub mod MOV_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOV_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -176,6 +344,24 @@ pub mod MOVS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOVS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -200,6 +386,36 @@ pub mod MOVS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOVS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -228,6 +444,30 @@ pub mod BIC_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BIC_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -254,6 +494,42 @@ pub mod BIC_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BIC_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -284,6 +560,30 @@ pub mod BICS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BICS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -310,6 +610,42 @@ pub mod BICS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BICS_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -340,6 +676,24 @@ pub mod MVN_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVN_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -364,6 +718,36 @@ pub mod MVN_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVN_r_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -392,6 +776,24 @@ pub mod MVNS_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNS_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVNS_r_A1_RRX( cond: ::aarchmrs_types::BitValue<4>, @@ -416,6 +818,36 @@ pub mod MVNS_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNS_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVNS_r_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpregrs/intdp2reg_regsh.rs b/aarchmrs-instructions/src/A32/dp/dpregrs/intdp2reg_regsh.rs index 6bcbf820..b2b917ce 100644 --- a/aarchmrs-instructions/src/A32/dp/dpregrs/intdp2reg_regsh.rs +++ b/aarchmrs-instructions/src/A32/dp/dpregrs/intdp2reg_regsh.rs @@ -12,6 +12,36 @@ pub mod TST_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TST_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -42,6 +72,36 @@ pub mod TEQ_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEQ_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn TEQ_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -72,6 +132,36 @@ pub mod CMP_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMP_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -102,6 +192,36 @@ pub mod CMN_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn CMN_rr_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpregrs/intdp3reg_regsh.rs b/aarchmrs-instructions/src/A32/dp/dpregrs/intdp3reg_regsh.rs index aa283087..489c5784 100644 --- a/aarchmrs-instructions/src/A32/dp/dpregrs/intdp3reg_regsh.rs +++ b/aarchmrs-instructions/src/A32/dp/dpregrs/intdp3reg_regsh.rs @@ -12,6 +12,42 @@ pub mod ANDS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ANDS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -43,6 +79,42 @@ pub mod AND_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn AND_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -74,6 +146,42 @@ pub mod EORS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EORS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EORS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -105,6 +213,42 @@ pub mod EOR_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn EOR_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -136,6 +280,42 @@ pub mod SUBS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -167,6 +347,42 @@ pub mod SUB_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -198,6 +414,42 @@ pub mod RSBS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSBS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSBS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -229,6 +481,42 @@ pub mod RSB_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSB_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -260,6 +548,42 @@ pub mod ADDS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -291,6 +615,42 @@ pub mod ADD_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -322,6 +682,42 @@ pub mod ADCS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADCS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -353,6 +749,42 @@ pub mod ADC_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ADC_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -384,6 +816,42 @@ pub mod SBCS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBCS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -415,6 +883,42 @@ pub mod SBC_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBC_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -446,6 +950,42 @@ pub mod RSCS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSCS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSCS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -477,6 +1017,42 @@ pub mod RSC_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSC_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RSC_rr_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/dpregrs/logic3reg_regsh.rs b/aarchmrs-instructions/src/A32/dp/dpregrs/logic3reg_regsh.rs index b17c466d..f95b2c45 100644 --- a/aarchmrs-instructions/src/A32/dp/dpregrs/logic3reg_regsh.rs +++ b/aarchmrs-instructions/src/A32/dp/dpregrs/logic3reg_regsh.rs @@ -12,6 +12,42 @@ pub mod ORRS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORRS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORRS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -43,6 +79,42 @@ pub mod ORR_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn ORR_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -74,6 +146,36 @@ pub mod MOVS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOVS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -103,6 +205,36 @@ pub mod MOV_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MOV_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -132,6 +264,42 @@ pub mod BICS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BICS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -163,6 +331,42 @@ pub mod BIC_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BIC_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -194,6 +398,36 @@ pub mod MVNS_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNS_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVNS_rr_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -223,6 +457,36 @@ pub mod MVN_rr_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_rr_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MVN_rr_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/mul_half.rs b/aarchmrs-instructions/src/A32/dp/mul_half.rs index 7a0f5752..d38cd046 100644 --- a/aarchmrs-instructions/src/A32/dp/mul_half.rs +++ b/aarchmrs-instructions/src/A32/dp/mul_half.rs @@ -12,6 +12,36 @@ pub mod SMLABB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLABB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLABB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,36 @@ pub mod SMLABT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLABT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLABT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -68,6 +128,36 @@ pub mod SMLATB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLATB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLATB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -96,6 +186,36 @@ pub mod SMLATT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLATT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLATT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -124,6 +244,36 @@ pub mod SMLAWB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAWB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAWB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -152,6 +302,36 @@ pub mod SMLAWT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAWT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAWT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -180,6 +360,30 @@ pub mod SMULWB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULWB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULWB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -207,6 +411,30 @@ pub mod SMULWT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULWT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULWT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -234,6 +462,36 @@ pub mod SMLALBB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALBB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALBB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -262,6 +520,36 @@ pub mod SMLALBT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALBT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALBT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -290,6 +578,36 @@ pub mod SMLALTB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALTB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALTB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -318,6 +636,36 @@ pub mod SMLALTT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALTT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALTT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -346,6 +694,30 @@ pub mod SMULBB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULBB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULBB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -373,6 +745,30 @@ pub mod SMULBT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULBT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULBT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -400,6 +796,30 @@ pub mod SMULTB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULTB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULTB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -427,6 +847,30 @@ pub mod SMULTT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULTT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULTT_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/mul_word.rs b/aarchmrs-instructions/src/A32/dp/mul_word.rs index cb712cd1..9008730f 100644 --- a/aarchmrs-instructions/src/A32/dp/mul_word.rs +++ b/aarchmrs-instructions/src/A32/dp/mul_word.rs @@ -12,6 +12,30 @@ pub mod MULS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MULS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MULS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod MUL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MUL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MUL_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,36 @@ pub mod MLAS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLAS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MLAS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -94,6 +172,36 @@ pub mod MLA_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLA_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MLA_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -122,6 +230,36 @@ pub mod UMAAL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAAL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UMAAL_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -150,6 +288,36 @@ pub mod MLS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn MLS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -178,6 +346,36 @@ pub mod UMULLS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMULLS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UMULLS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -206,6 +404,36 @@ pub mod UMULL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMULL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UMULL_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -234,6 +462,36 @@ pub mod UMLALS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMLALS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UMLALS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -262,6 +520,36 @@ pub mod UMLAL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMLAL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UMLAL_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -290,6 +578,36 @@ pub mod SMULLS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULLS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULLS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -318,6 +636,36 @@ pub mod SMULL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMULL_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -346,6 +694,36 @@ pub mod SMLALS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -374,6 +752,36 @@ pub mod SMLAL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAL_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/sync/ldst_excl.rs b/aarchmrs-instructions/src/A32/dp/sync/ldst_excl.rs index aa05e581..0e77d1cb 100644 --- a/aarchmrs-instructions/src/A32/dp/sync/ldst_excl.rs +++ b/aarchmrs-instructions/src/A32/dp/sync/ldst_excl.rs @@ -12,6 +12,24 @@ pub mod STL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STL_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,30 @@ pub mod STLEX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STLEX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -62,6 +104,30 @@ pub mod STREX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STREX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -88,6 +154,24 @@ pub mod LDA_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDA_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDA_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -112,6 +196,24 @@ pub mod LDAEX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -136,6 +238,24 @@ pub mod LDREX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDREX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -160,6 +280,30 @@ pub mod STLEXD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEXD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STLEXD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -186,6 +330,30 @@ pub mod STREXD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREXD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STREXD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -212,6 +380,24 @@ pub mod LDAEXD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEXD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEXD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -236,6 +422,24 @@ pub mod LDREXD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREXD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDREXD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -260,6 +464,24 @@ pub mod STLB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STLB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -284,6 +506,30 @@ pub mod STLEXB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEXB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STLEXB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -310,6 +556,30 @@ pub mod STREXB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREXB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STREXB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -336,6 +606,24 @@ pub mod LDAB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDAB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -360,6 +648,24 @@ pub mod LDAEXB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEXB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEXB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -384,6 +690,24 @@ pub mod LDREXB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREXB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDREXB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -408,6 +732,24 @@ pub mod STLH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STLH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -432,6 +774,30 @@ pub mod STLEXH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEXH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STLEXH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -458,6 +824,30 @@ pub mod STREXH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREXH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STREXH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -484,6 +874,24 @@ pub mod LDAH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDAH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -508,6 +916,24 @@ pub mod LDAEXH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEXH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEXH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -532,6 +958,24 @@ pub mod LDREXH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000110000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREXH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDREXH_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/xldst/ldstximm.rs b/aarchmrs-instructions/src/A32/dp/xldst/ldstximm.rs index 2c9e7850..90d496f1 100644 --- a/aarchmrs-instructions/src/A32/dp/xldst/ldstximm.rs +++ b/aarchmrs-instructions/src/A32/dp/xldst/ldstximm.rs @@ -12,6 +12,36 @@ pub mod LDRD_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000001001000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRD_l_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,48 @@ pub mod LDRH_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_l_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -75,6 +147,48 @@ pub mod LDRSB_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_l_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -109,6 +223,48 @@ pub mod LDRSH_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_l_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -143,6 +299,42 @@ pub mod LDRD_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRD_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -174,6 +366,42 @@ pub mod LDRD_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRD_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -205,6 +433,42 @@ pub mod LDRD_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRD_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -236,6 +500,42 @@ pub mod STRH_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -267,6 +567,42 @@ pub mod STRH_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -298,6 +634,42 @@ pub mod STRH_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -329,6 +701,42 @@ pub mod STRD_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRD_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -360,6 +768,42 @@ pub mod STRD_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRD_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -391,6 +835,42 @@ pub mod STRD_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRD_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -422,6 +902,42 @@ pub mod LDRH_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -453,6 +969,42 @@ pub mod LDRH_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -484,6 +1036,42 @@ pub mod LDRH_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -515,6 +1103,42 @@ pub mod LDRSB_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -546,6 +1170,42 @@ pub mod LDRSB_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -577,6 +1237,42 @@ pub mod LDRSB_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -608,6 +1304,42 @@ pub mod LDRSH_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -639,6 +1371,42 @@ pub mod LDRSH_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -670,6 +1438,42 @@ pub mod LDRSH_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -701,6 +1505,42 @@ pub mod STRHT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRHT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRHT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -732,6 +1572,42 @@ pub mod LDRHT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRHT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRHT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -763,6 +1639,42 @@ pub mod LDRSBT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSBT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSBT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -794,6 +1706,42 @@ pub mod LDRSHT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSHT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSHT_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/dp/xldst/ldstxreg.rs b/aarchmrs-instructions/src/A32/dp/xldst/ldstxreg.rs index 58c8c640..f4a5f1b9 100644 --- a/aarchmrs-instructions/src/A32/dp/xldst/ldstxreg.rs +++ b/aarchmrs-instructions/src/A32/dp/xldst/ldstxreg.rs @@ -12,6 +12,36 @@ pub mod STRH_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod STRH_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,36 @@ pub mod STRH_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -99,6 +189,36 @@ pub mod LDRD_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRD_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -128,6 +248,36 @@ pub mod LDRD_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRD_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -157,6 +307,36 @@ pub mod LDRD_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRD_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -186,6 +366,36 @@ pub mod STRD_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRD_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -215,6 +425,36 @@ pub mod STRD_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRD_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -244,6 +484,36 @@ pub mod STRD_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRD_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -273,6 +543,36 @@ pub mod LDRH_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -302,6 +602,36 @@ pub mod LDRH_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -331,6 +661,36 @@ pub mod LDRH_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -360,6 +720,36 @@ pub mod LDRSB_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -389,6 +779,36 @@ pub mod LDRSB_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -418,6 +838,36 @@ pub mod LDRSB_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -447,6 +897,36 @@ pub mod LDRSH_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -476,6 +956,36 @@ pub mod LDRSH_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -505,6 +1015,36 @@ pub mod LDRSH_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -534,6 +1074,36 @@ pub mod STRHT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRHT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRHT_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -563,6 +1133,36 @@ pub mod LDRHT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRHT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRHT_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -592,6 +1192,36 @@ pub mod LDRSBT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSBT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSBT_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -621,6 +1251,36 @@ pub mod LDRSHT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSHT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSHT_A2( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/ldstimm.rs b/aarchmrs-instructions/src/A32/ldstimm.rs index 727edd45..92e1729d 100644 --- a/aarchmrs-instructions/src/A32/ldstimm.rs +++ b/aarchmrs-instructions/src/A32/ldstimm.rs @@ -12,6 +12,42 @@ pub mod LDR_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_l_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -43,6 +79,42 @@ pub mod LDRB_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_l_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -74,6 +146,36 @@ pub mod STR_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STR_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -102,6 +204,36 @@ pub mod STR_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STR_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -130,6 +262,36 @@ pub mod STR_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STR_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -158,6 +320,36 @@ pub mod LDR_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -186,6 +378,36 @@ pub mod LDR_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -214,6 +436,36 @@ pub mod LDR_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -242,6 +494,36 @@ pub mod STRB_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -270,6 +552,36 @@ pub mod STRB_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -298,6 +610,36 @@ pub mod STRB_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -326,6 +668,36 @@ pub mod LDRB_i_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_i_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -354,6 +726,36 @@ pub mod LDRB_i_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_i_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -382,6 +784,36 @@ pub mod LDRB_i_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_i_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -410,6 +842,36 @@ pub mod STRT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -438,6 +900,36 @@ pub mod LDRT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -466,6 +958,36 @@ pub mod STRBT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRBT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRBT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -494,6 +1016,36 @@ pub mod LDRBT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRBT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRBT_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/ldstreg.rs b/aarchmrs-instructions/src/A32/ldstreg.rs index d1fae40c..bf590434 100644 --- a/aarchmrs-instructions/src/A32/ldstreg.rs +++ b/aarchmrs-instructions/src/A32/ldstreg.rs @@ -12,6 +12,48 @@ pub mod STR_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STR_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -45,6 +87,48 @@ pub mod STR_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STR_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -78,6 +162,48 @@ pub mod STR_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STR_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -111,6 +237,48 @@ pub mod LDR_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -144,6 +312,48 @@ pub mod LDR_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -177,6 +387,48 @@ pub mod LDR_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -210,6 +462,48 @@ pub mod STRT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRT_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -243,6 +537,48 @@ pub mod LDRT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRT_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -276,6 +612,48 @@ pub mod STRB_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -309,6 +687,48 @@ pub mod STRB_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -342,6 +762,48 @@ pub mod STRB_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -375,6 +837,48 @@ pub mod LDRB_r_A1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_r_A1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_r_A1_off( cond: ::aarchmrs_types::BitValue<4>, @@ -408,6 +912,48 @@ pub mod LDRB_r_A1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_r_A1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_r_A1_post( cond: ::aarchmrs_types::BitValue<4>, @@ -441,6 +987,48 @@ pub mod LDRB_r_A1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_r_A1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_r_A1_pre( cond: ::aarchmrs_types::BitValue<4>, @@ -474,6 +1062,48 @@ pub mod STRBT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRBT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn STRBT_A2( cond: ::aarchmrs_types::BitValue<4>, @@ -507,6 +1137,48 @@ pub mod LDRBT_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRBT_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn LDRBT_A2( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/bfi.rs b/aarchmrs-instructions/src/A32/media/bfi.rs index bd3b7677..c0d590ef 100644 --- a/aarchmrs-instructions/src/A32/media/bfi.rs +++ b/aarchmrs-instructions/src/A32/media/bfi.rs @@ -12,6 +12,36 @@ pub mod BFI_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFI_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BFI_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,30 @@ pub mod BFC_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFC_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn BFC_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/bfx.rs b/aarchmrs-instructions/src/A32/media/bfx.rs index 112e84cd..1448abf2 100644 --- a/aarchmrs-instructions/src/A32/media/bfx.rs +++ b/aarchmrs-instructions/src/A32/media/bfx.rs @@ -12,6 +12,36 @@ pub mod SBFX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBFX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SBFX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,36 @@ pub mod UBFX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UBFX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_lsb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UBFX_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/extend.rs b/aarchmrs-instructions/src/A32/media/extend.rs index d53f5d3c..86eff3b7 100644 --- a/aarchmrs-instructions/src/A32/media/extend.rs +++ b/aarchmrs-instructions/src/A32/media/extend.rs @@ -12,6 +12,36 @@ pub mod SXTAB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTAB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SXTAB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,30 @@ pub mod SXTB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SXTB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -66,6 +120,36 @@ pub mod SXTAB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTAB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SXTAB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -94,6 +178,30 @@ pub mod SXTB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SXTB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -120,6 +228,36 @@ pub mod SXTAH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTAH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SXTAH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -148,6 +286,30 @@ pub mod SXTH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SXTH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -174,6 +336,36 @@ pub mod UXTAB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTAB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UXTAB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -202,6 +394,30 @@ pub mod UXTB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UXTB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -228,6 +444,36 @@ pub mod UXTAB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTAB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UXTAB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -256,6 +502,30 @@ pub mod UXTB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UXTB_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -282,6 +552,36 @@ pub mod UXTAH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTAH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UXTAH_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -310,6 +610,30 @@ pub mod UXTH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000001100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UXTH_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/pack.rs b/aarchmrs-instructions/src/A32/media/pack.rs index dc6092a4..637e09a6 100644 --- a/aarchmrs-instructions/src/A32/media/pack.rs +++ b/aarchmrs-instructions/src/A32/media/pack.rs @@ -12,6 +12,36 @@ pub mod PKHBT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PKHBT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn PKHBT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,36 @@ pub mod PKHTB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PKHTB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn PKHTB_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/parallel.rs b/aarchmrs-instructions/src/A32/media/parallel.rs index ef98200a..e5514f54 100644 --- a/aarchmrs-instructions/src/A32/media/parallel.rs +++ b/aarchmrs-instructions/src/A32/media/parallel.rs @@ -12,6 +12,30 @@ pub mod SADD16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADD16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SADD16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod SASX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SASX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SASX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod SSAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SSAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod SSUB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSUB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SSUB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod SADD8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADD8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SADD8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod SSUB8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSUB8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SSUB8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod QADD16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QADD16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QADD16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod QASX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QASX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QASX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -220,6 +412,30 @@ pub mod QSAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QSAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -246,6 +462,30 @@ pub mod QSUB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSUB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QSUB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -272,6 +512,30 @@ pub mod QADD8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QADD8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QADD8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -298,6 +562,30 @@ pub mod QSUB8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSUB8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn QSUB8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -324,6 +612,30 @@ pub mod SHADD16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHADD16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SHADD16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -350,6 +662,30 @@ pub mod SHASX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHASX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SHASX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -376,6 +712,30 @@ pub mod SHSAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHSAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SHSAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -402,6 +762,30 @@ pub mod SHSUB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHSUB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SHSUB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -428,6 +812,30 @@ pub mod SHADD8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHADD8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SHADD8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -454,6 +862,30 @@ pub mod SHSUB8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHSUB8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SHSUB8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -480,6 +912,30 @@ pub mod UADD16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADD16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UADD16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -506,6 +962,30 @@ pub mod UASX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UASX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UASX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -532,6 +1012,30 @@ pub mod USAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -558,6 +1062,30 @@ pub mod USUB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USUB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USUB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -584,6 +1112,30 @@ pub mod UADD8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADD8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UADD8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -610,6 +1162,30 @@ pub mod USUB8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USUB8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USUB8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -636,6 +1212,30 @@ pub mod UQADD16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQADD16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UQADD16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -662,6 +1262,30 @@ pub mod UQASX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQASX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UQASX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -688,6 +1312,30 @@ pub mod UQSAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UQSAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -714,6 +1362,30 @@ pub mod UQSUB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSUB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UQSUB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -740,6 +1412,30 @@ pub mod UQADD8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQADD8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UQADD8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -766,6 +1462,30 @@ pub mod UQSUB8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSUB8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UQSUB8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -792,6 +1512,30 @@ pub mod UHADD16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHADD16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UHADD16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -818,6 +1562,30 @@ pub mod UHASX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHASX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UHASX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -844,6 +1612,30 @@ pub mod UHSAX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHSAX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UHSAX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -870,6 +1662,30 @@ pub mod UHSUB16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHSUB16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UHSUB16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -896,6 +1712,30 @@ pub mod UHADD8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHADD8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UHADD8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -922,6 +1762,30 @@ pub mod UHSUB8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHSUB8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UHSUB8_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/reverse.rs b/aarchmrs-instructions/src/A32/media/reverse.rs index fdf33ec4..a51fb419 100644 --- a/aarchmrs-instructions/src/A32/media/reverse.rs +++ b/aarchmrs-instructions/src/A32/media/reverse.rs @@ -12,6 +12,24 @@ pub mod REV_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn REV_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod REV16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn REV16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod RBIT_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RBIT_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn RBIT_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod REVSH_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REVSH_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn REVSH_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/sat16.rs b/aarchmrs-instructions/src/A32/media/sat16.rs index 56a78645..738bc3c2 100644 --- a/aarchmrs-instructions/src/A32/media/sat16.rs +++ b/aarchmrs-instructions/src/A32/media/sat16.rs @@ -12,6 +12,30 @@ pub mod SSAT16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAT16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SSAT16_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod USAT16_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAT16_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USAT16_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/sat32.rs b/aarchmrs-instructions/src/A32/media/sat32.rs index 1496d428..53a83b72 100644 --- a/aarchmrs-instructions/src/A32/media/sat32.rs +++ b/aarchmrs-instructions/src/A32/media/sat32.rs @@ -12,6 +12,36 @@ pub mod SSAT_A1_ASR { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAT_A1_ASR"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SSAT_A1_ASR( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,36 @@ pub mod SSAT_A1_LSL { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAT_A1_LSL"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SSAT_A1_LSL( cond: ::aarchmrs_types::BitValue<4>, @@ -68,6 +128,36 @@ pub mod USAT_A1_ASR { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAT_A1_ASR"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USAT_A1_ASR( cond: ::aarchmrs_types::BitValue<4>, @@ -96,6 +186,36 @@ pub mod USAT_A1_LSL { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAT_A1_LSL"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USAT_A1_LSL( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/selbytes.rs b/aarchmrs-instructions/src/A32/media/selbytes.rs index cd729741..02080168 100644 --- a/aarchmrs-instructions/src/A32/media/selbytes.rs +++ b/aarchmrs-instructions/src/A32/media/selbytes.rs @@ -12,6 +12,30 @@ pub mod SEL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SEL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SEL_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/smul_div.rs b/aarchmrs-instructions/src/A32/media/smul_div.rs index 1c59df46..6204bca6 100644 --- a/aarchmrs-instructions/src/A32/media/smul_div.rs +++ b/aarchmrs-instructions/src/A32/media/smul_div.rs @@ -12,6 +12,36 @@ pub mod SMLAD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,36 @@ pub mod SMLADX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLADX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLADX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -68,6 +128,36 @@ pub mod SMLSD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -96,6 +186,36 @@ pub mod SMLSDX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSDX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSDX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -124,6 +244,30 @@ pub mod SMUAD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUAD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMUAD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -151,6 +295,30 @@ pub mod SMUADX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUADX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMUADX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -178,6 +346,30 @@ pub mod SMUSD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUSD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMUSD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -205,6 +397,30 @@ pub mod SMUSDX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUSDX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMUSDX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -232,6 +448,30 @@ pub mod SDIV_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SDIV_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SDIV_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -259,6 +499,30 @@ pub mod UDIV_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDIV_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn UDIV_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -286,6 +550,36 @@ pub mod SMLALD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -314,6 +608,36 @@ pub mod SMLALDX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALDX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALDX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -342,6 +666,36 @@ pub mod SMLSLD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSLD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSLD_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -370,6 +724,36 @@ pub mod SMLSLDX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSLDX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSLDX_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -398,6 +782,36 @@ pub mod SMMLA_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLA_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLA_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -426,6 +840,36 @@ pub mod SMMLAR_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLAR_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLAR_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -454,6 +898,36 @@ pub mod SMMLS_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLS_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLS_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -482,6 +956,36 @@ pub mod SMMLSR_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLSR_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLSR_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -510,6 +1014,30 @@ pub mod SMMUL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMUL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMMUL_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -537,6 +1065,30 @@ pub mod SMMULR_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMULR_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn SMMULR_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/media/udf.rs b/aarchmrs-instructions/src/A32/media/udf.rs index 3feed52c..70c2d62f 100644 --- a/aarchmrs-instructions/src/A32/media/udf.rs +++ b/aarchmrs-instructions/src/A32/media/udf.rs @@ -12,6 +12,18 @@ pub mod UDF_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDF_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn UDF_A1( imm12: ::aarchmrs_types::BitValue<12>, diff --git a/aarchmrs-instructions/src/A32/media/usad.rs b/aarchmrs-instructions/src/A32/media/usad.rs index 82e872f2..1e5867d1 100644 --- a/aarchmrs-instructions/src/A32/media/usad.rs +++ b/aarchmrs-instructions/src/A32/media/usad.rs @@ -12,6 +12,36 @@ pub mod USADA8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USADA8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USADA8_A1( cond: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,30 @@ pub mod USAD8_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAD8_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn USAD8_A1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd1reg_imm.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd1reg_imm.rs index cb36afdf..45fe75ab 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd1reg_imm.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd1reg_imm.rs @@ -12,6 +12,42 @@ pub mod VMOV_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A1_D( i: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VMOV_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VMVN_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_A1_D( i: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VMVN_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_A1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VORR_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_A1_D( i: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VORR_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_A1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -210,6 +426,42 @@ pub mod VBIC_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_A1_D( i: ::aarchmrs_types::BitValue<1>, @@ -243,6 +495,42 @@ pub mod VBIC_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_A1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -276,6 +564,42 @@ pub mod VMOV_i_A3_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A3_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A3_D( i: ::aarchmrs_types::BitValue<1>, @@ -309,6 +633,42 @@ pub mod VMOV_i_A3_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A3_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A3_Q( i: ::aarchmrs_types::BitValue<1>, @@ -342,6 +702,42 @@ pub mod VMVN_i_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_A2_D( i: ::aarchmrs_types::BitValue<1>, @@ -375,6 +771,42 @@ pub mod VMVN_i_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_A2_Q( i: ::aarchmrs_types::BitValue<1>, @@ -408,6 +840,42 @@ pub mod VORR_i_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_A2_D( i: ::aarchmrs_types::BitValue<1>, @@ -441,6 +909,42 @@ pub mod VORR_i_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_A2_Q( i: ::aarchmrs_types::BitValue<1>, @@ -474,6 +978,42 @@ pub mod VBIC_i_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_A2_D( i: ::aarchmrs_types::BitValue<1>, @@ -507,6 +1047,42 @@ pub mod VBIC_i_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_A2_Q( i: ::aarchmrs_types::BitValue<1>, @@ -540,6 +1116,42 @@ pub mod VMOV_i_A4_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A4_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A4_D( i: ::aarchmrs_types::BitValue<1>, @@ -573,6 +1185,42 @@ pub mod VMOV_i_A4_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A4_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A4_Q( i: ::aarchmrs_types::BitValue<1>, @@ -606,6 +1254,42 @@ pub mod VMVN_i_A3_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_A3_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_A3_D( i: ::aarchmrs_types::BitValue<1>, @@ -639,6 +1323,42 @@ pub mod VMVN_i_A3_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_A3_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_A3_Q( i: ::aarchmrs_types::BitValue<1>, @@ -672,6 +1392,36 @@ pub mod VMOV_i_A5_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A5_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A5_D( i: ::aarchmrs_types::BitValue<1>, @@ -702,6 +1452,36 @@ pub mod VMOV_i_A5_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_A5_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_A5_Q( i: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd2reg_shift.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd2reg_shift.rs index 32ae6a14..928528d5 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd2reg_shift.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_12reg/simd2reg_shift.rs @@ -12,6 +12,48 @@ pub mod VSHR_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHR_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHR_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -47,6 +89,48 @@ pub mod VSHR_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHR_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHR_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -82,6 +166,48 @@ pub mod VSRA_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRA_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSRA_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -117,6 +243,48 @@ pub mod VSRA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSRA_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -152,6 +320,42 @@ pub mod VMOVL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOVL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3H_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3H_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMOVL_A1( U: ::aarchmrs_types::BitValue<1>, @@ -185,6 +389,48 @@ pub mod VRSHR_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHR_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHR_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -220,6 +466,48 @@ pub mod VRSHR_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHR_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHR_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -255,6 +543,48 @@ pub mod VRSRA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSRA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSRA_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -290,6 +620,48 @@ pub mod VRSRA_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSRA_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSRA_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -325,6 +697,48 @@ pub mod VQSHL_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_i_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -360,6 +774,42 @@ pub mod VQSHLU_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHLU_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHLU_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -392,6 +842,48 @@ pub mod VQSHL_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_i_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -427,6 +919,42 @@ pub mod VQSHLU_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHLU_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHLU_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -459,6 +987,42 @@ pub mod VQSHRN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHRN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHRN_A1( U: ::aarchmrs_types::BitValue<1>, @@ -491,6 +1055,36 @@ pub mod VQSHRUN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHRUN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHRUN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -520,6 +1114,42 @@ pub mod VQRSHRN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHRN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHRN_A1( U: ::aarchmrs_types::BitValue<1>, @@ -552,6 +1182,36 @@ pub mod VQRSHRUN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHRUN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHRUN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -581,6 +1241,42 @@ pub mod VSHLL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHLL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHLL_A1( U: ::aarchmrs_types::BitValue<1>, @@ -613,6 +1309,48 @@ pub mod VCVT_xs_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xs_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_xs_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -648,6 +1386,48 @@ pub mod VCVT_xs_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xs_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_xs_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -683,6 +1463,42 @@ pub mod VSHL_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -715,6 +1531,42 @@ pub mod VSHL_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -747,6 +1599,36 @@ pub mod VSHRN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHRN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHRN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -776,6 +1658,36 @@ pub mod VRSHRN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHRN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHRN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -805,6 +1717,42 @@ pub mod VSRI_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRI_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSRI_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -837,6 +1785,42 @@ pub mod VSRI_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRI_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSRI_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -869,6 +1853,42 @@ pub mod VSLI_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSLI_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSLI_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -901,6 +1921,42 @@ pub mod VSLI_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSLI_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSLI_A1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_dup.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_dup.rs index 6a3645ca..7c2fe061 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_dup.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_dup.rs @@ -12,6 +12,36 @@ pub mod VDUP_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDUP_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,36 @@ pub mod VDUP_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDUP_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_misc.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_misc.rs index af9e676e..0e55bbd3 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_misc.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_misc.rs @@ -12,6 +12,36 @@ pub mod VREV64_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV64_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV64_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod VREV64_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV64_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV64_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -74,6 +134,36 @@ pub mod VREV32_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV32_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV32_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -105,6 +195,36 @@ pub mod VREV32_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV32_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV32_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -136,6 +256,36 @@ pub mod VREV16_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV16_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV16_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -167,6 +317,36 @@ pub mod VREV16_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV16_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV16_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -198,6 +378,42 @@ pub mod VPADDL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADDL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADDL_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -232,6 +448,42 @@ pub mod VPADDL_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADDL_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADDL_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -266,6 +518,36 @@ pub mod AESE_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESE_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESE_A1( D: ::aarchmrs_types::BitValue<1>, @@ -297,6 +579,36 @@ pub mod AESD_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESD_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESD_A1( D: ::aarchmrs_types::BitValue<1>, @@ -328,6 +640,36 @@ pub mod AESMC_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESMC_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESMC_A1( D: ::aarchmrs_types::BitValue<1>, @@ -359,6 +701,36 @@ pub mod AESIMC_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESIMC_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESIMC_A1( D: ::aarchmrs_types::BitValue<1>, @@ -390,6 +762,36 @@ pub mod VCLS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLS_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -421,6 +823,36 @@ pub mod VCLS_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLS_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLS_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -452,6 +884,30 @@ pub mod VSWP_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSWP_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSWP_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -480,6 +936,30 @@ pub mod VSWP_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSWP_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSWP_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -508,6 +988,36 @@ pub mod VCLZ_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLZ_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLZ_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -539,6 +1049,36 @@ pub mod VCLZ_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLZ_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLZ_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -570,6 +1110,36 @@ pub mod VCNT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCNT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCNT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -601,6 +1171,36 @@ pub mod VCNT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCNT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCNT_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -632,6 +1232,36 @@ pub mod VMVN_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_r_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -663,6 +1293,36 @@ pub mod VMVN_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_r_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -694,6 +1354,42 @@ pub mod VPADAL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADAL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADAL_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -728,6 +1424,42 @@ pub mod VPADAL_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADAL_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADAL_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -762,6 +1494,36 @@ pub mod VQABS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQABS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQABS_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -793,6 +1555,36 @@ pub mod VQABS_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQABS_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQABS_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -824,6 +1616,36 @@ pub mod VQNEG_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQNEG_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQNEG_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -855,6 +1677,36 @@ pub mod VQNEG_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQNEG_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQNEG_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -886,6 +1738,42 @@ pub mod VCGT_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -920,6 +1808,42 @@ pub mod VCGT_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -954,6 +1878,42 @@ pub mod VCGE_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -988,6 +1948,42 @@ pub mod VCGE_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1022,6 +2018,42 @@ pub mod VCEQ_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1056,6 +2088,42 @@ pub mod VCEQ_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1090,6 +2158,42 @@ pub mod VCLE_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLE_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLE_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1124,6 +2228,42 @@ pub mod VCLE_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLE_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLE_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1158,6 +2298,42 @@ pub mod VCLT_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLT_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLT_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1192,6 +2368,42 @@ pub mod VCLT_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLT_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLT_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1226,6 +2438,42 @@ pub mod VABS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABS_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1260,6 +2508,42 @@ pub mod VABS_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABS_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1294,6 +2578,42 @@ pub mod VNEG_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNEG_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1328,6 +2648,42 @@ pub mod VNEG_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNEG_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1362,6 +2718,36 @@ pub mod SHA1H_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1H_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1H_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1393,6 +2779,30 @@ pub mod VCVT_bfs_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_bfs_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_bfs_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1421,6 +2831,36 @@ pub mod VTRN_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTRN_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTRN_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1452,6 +2892,36 @@ pub mod VTRN_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTRN_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTRN_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1483,6 +2953,36 @@ pub mod VUZP_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUZP_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUZP_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1514,6 +3014,36 @@ pub mod VUZP_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUZP_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUZP_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1545,6 +3075,36 @@ pub mod VZIP_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VZIP_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VZIP_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1576,6 +3136,36 @@ pub mod VZIP_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VZIP_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VZIP_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1607,6 +3197,36 @@ pub mod VMOVN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOVN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOVN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1638,6 +3258,42 @@ pub mod VQMOVN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQMOVN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQMOVN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1671,6 +3327,36 @@ pub mod VQMOVUN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQMOVUN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQMOVUN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1702,6 +3388,36 @@ pub mod VSHLL_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHLL_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHLL_A2( D: ::aarchmrs_types::BitValue<1>, @@ -1733,6 +3449,36 @@ pub mod SHA1SU1_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1SU1_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1SU1_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1764,6 +3510,36 @@ pub mod SHA256SU0_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256SU0_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256SU0_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1795,6 +3571,36 @@ pub mod VRINTN_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1826,6 +3632,36 @@ pub mod VRINTN_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1857,6 +3693,36 @@ pub mod VRINTX_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTX_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1888,6 +3754,36 @@ pub mod VRINTX_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTX_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1919,6 +3815,36 @@ pub mod VRINTA_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1950,6 +3876,36 @@ pub mod VRINTA_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1981,6 +3937,36 @@ pub mod VRINTZ_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTZ_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2012,6 +3998,36 @@ pub mod VRINTZ_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTZ_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2043,6 +4059,36 @@ pub mod VCVT_sh_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_sh_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_sh_A1( D: ::aarchmrs_types::BitValue<1>, @@ -2074,6 +4120,36 @@ pub mod VCVT_hs_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_hs_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_hs_A1( D: ::aarchmrs_types::BitValue<1>, @@ -2105,6 +4181,36 @@ pub mod VRINTM_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2136,6 +4242,36 @@ pub mod VRINTM_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2167,6 +4303,36 @@ pub mod VRINTP_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2198,6 +4364,36 @@ pub mod VRINTP_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2229,6 +4425,42 @@ pub mod VCVTA_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2263,6 +4495,42 @@ pub mod VCVTA_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2297,6 +4565,42 @@ pub mod VCVTN_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2331,6 +4635,42 @@ pub mod VCVTN_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2365,6 +4705,42 @@ pub mod VCVTP_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2399,6 +4775,42 @@ pub mod VCVTP_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2433,6 +4845,42 @@ pub mod VCVTM_asimd_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_asimd_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_asimd_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2467,6 +4915,42 @@ pub mod VCVTM_asimd_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_asimd_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_asimd_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2501,6 +4985,42 @@ pub mod VRECPE_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPE_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPE_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2535,6 +5055,42 @@ pub mod VRECPE_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPE_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPE_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2569,6 +5125,42 @@ pub mod VRSQRTE_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTE_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTE_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2603,6 +5195,42 @@ pub mod VRSQRTE_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTE_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTE_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2637,6 +5265,42 @@ pub mod VCVT_is_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_is_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_is_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2671,6 +5335,42 @@ pub mod VCVT_is_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_is_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_is_A1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_scalar.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_scalar.rs index f0dbb526..90ef4603 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_scalar.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd2reg_scalar.rs @@ -12,6 +12,54 @@ pub mod VMLA_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -48,6 +96,54 @@ pub mod VMLA_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -84,6 +180,48 @@ pub mod VQDMLAL_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLAL_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLAL_A2( D: ::aarchmrs_types::BitValue<1>, @@ -118,6 +256,54 @@ pub mod VMLAL_s_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLAL_s_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLAL_s_A1( U: ::aarchmrs_types::BitValue<1>, @@ -155,6 +341,48 @@ pub mod VQDMLSL_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLSL_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLSL_A2( D: ::aarchmrs_types::BitValue<1>, @@ -189,6 +417,54 @@ pub mod VMLS_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -225,6 +501,54 @@ pub mod VMLS_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -261,6 +585,48 @@ pub mod VQDMULL_A2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULL_A2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULL_A2( D: ::aarchmrs_types::BitValue<1>, @@ -295,6 +661,54 @@ pub mod VMLSL_s_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLSL_s_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLSL_s_A1( U: ::aarchmrs_types::BitValue<1>, @@ -332,6 +746,54 @@ pub mod VMUL_s_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_s_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_s_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -368,6 +830,54 @@ pub mod VMUL_s_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_s_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_s_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -404,6 +914,54 @@ pub mod VMULL_s_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMULL_s_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMULL_s_A1( U: ::aarchmrs_types::BitValue<1>, @@ -441,6 +999,48 @@ pub mod VQDMULH_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -475,6 +1075,48 @@ pub mod VQDMULH_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_A2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -509,6 +1151,48 @@ pub mod VQRDMULH_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -543,6 +1227,48 @@ pub mod VQRDMULH_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_A2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -577,6 +1303,48 @@ pub mod VQRDMLAH_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -611,6 +1379,48 @@ pub mod VQRDMLAH_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_A2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -645,6 +1455,48 @@ pub mod VQRDMLSH_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -679,6 +1531,48 @@ pub mod VQRDMLSH_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_A2_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_diff.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_diff.rs index 6554b1a2..8415874a 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_diff.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_diff.rs @@ -12,6 +12,54 @@ pub mod VADDL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADDL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VADDL_A1( U: ::aarchmrs_types::BitValue<1>, @@ -49,6 +97,54 @@ pub mod VADDW_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADDW_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VADDW_A1( U: ::aarchmrs_types::BitValue<1>, @@ -86,6 +182,54 @@ pub mod VSUBL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUBL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSUBL_A1( U: ::aarchmrs_types::BitValue<1>, @@ -123,6 +267,48 @@ pub mod VADDHN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADDHN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADDHN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -157,6 +343,54 @@ pub mod VSUBW_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUBW_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSUBW_A1( U: ::aarchmrs_types::BitValue<1>, @@ -194,6 +428,48 @@ pub mod VSUBHN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUBHN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUBHN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -228,6 +504,48 @@ pub mod VQDMLAL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLAL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLAL_A1( D: ::aarchmrs_types::BitValue<1>, @@ -262,6 +580,54 @@ pub mod VABAL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABAL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABAL_A1( U: ::aarchmrs_types::BitValue<1>, @@ -299,6 +665,48 @@ pub mod VQDMLSL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLSL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLSL_A1( D: ::aarchmrs_types::BitValue<1>, @@ -333,6 +741,48 @@ pub mod VQDMULL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULL_A1( D: ::aarchmrs_types::BitValue<1>, @@ -367,6 +817,54 @@ pub mod VABDL_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABDL_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABDL_i_A1( U: ::aarchmrs_types::BitValue<1>, @@ -404,6 +902,54 @@ pub mod VMLAL_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLAL_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLAL_i_A1( U: ::aarchmrs_types::BitValue<1>, @@ -441,6 +987,54 @@ pub mod VMLSL_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLSL_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLSL_i_A1( U: ::aarchmrs_types::BitValue<1>, @@ -478,6 +1072,48 @@ pub mod VRADDHN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRADDHN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRADDHN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -512,6 +1148,48 @@ pub mod VRSUBHN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSUBHN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSUBHN_A1( D: ::aarchmrs_types::BitValue<1>, @@ -546,6 +1224,60 @@ pub mod VMULL_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMULL_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMULL_i_A1( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_ext.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_ext.rs index a6025ca4..c2220834 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_ext.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_ext.rs @@ -12,6 +12,48 @@ pub mod VEXT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEXT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEXT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -46,6 +88,48 @@ pub mod VEXT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEXT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEXT_A1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_tbl.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_tbl.rs index 906949d7..fc3cf5c2 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_tbl.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/a_simd_mulreg/simd3reg_tbl.rs @@ -12,6 +12,48 @@ pub mod VTBL_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTBL_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTBL_A1( D: ::aarchmrs_types::BitValue<1>, @@ -47,6 +89,48 @@ pub mod VTBX_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTBX_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTBX_A1( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/simd3reg_same.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/simd3reg_same.rs index 38a70482..b0788c66 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimddp/simd3reg_same.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimddp/simd3reg_same.rs @@ -12,6 +12,48 @@ pub mod VFMA_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -47,6 +89,48 @@ pub mod VFMA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -82,6 +166,48 @@ pub mod VADD_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -117,6 +243,48 @@ pub mod VADD_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -152,6 +320,48 @@ pub mod VMLA_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -187,6 +397,48 @@ pub mod VMLA_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -222,6 +474,48 @@ pub mod VCEQ_r_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -257,6 +551,48 @@ pub mod VCEQ_r_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_A2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -292,6 +628,48 @@ pub mod VMAX_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -327,6 +705,48 @@ pub mod VMAX_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -362,6 +782,48 @@ pub mod VRECPS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPS_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -397,6 +859,48 @@ pub mod VRECPS_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPS_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPS_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -432,6 +936,54 @@ pub mod VHADD_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHADD_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHADD_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -469,6 +1021,54 @@ pub mod VHADD_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHADD_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHADD_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -506,6 +1106,42 @@ pub mod VAND_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VAND_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VAND_r_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -539,6 +1175,42 @@ pub mod VAND_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VAND_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VAND_r_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -572,6 +1244,54 @@ pub mod VQADD_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQADD_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQADD_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -609,6 +1329,54 @@ pub mod VQADD_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQADD_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQADD_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -646,6 +1414,54 @@ pub mod VRHADD_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRHADD_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRHADD_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -683,6 +1499,54 @@ pub mod VRHADD_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRHADD_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRHADD_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -720,6 +1584,48 @@ pub mod SHA1C_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1C_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1C_A1( D: ::aarchmrs_types::BitValue<1>, @@ -754,6 +1660,54 @@ pub mod VHSUB_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHSUB_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHSUB_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -791,6 +1745,54 @@ pub mod VHSUB_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHSUB_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHSUB_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -828,6 +1830,42 @@ pub mod VBIC_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_r_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -861,6 +1899,42 @@ pub mod VBIC_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_r_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -894,6 +1968,54 @@ pub mod VQSUB_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSUB_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSUB_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -931,6 +2053,54 @@ pub mod VQSUB_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSUB_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSUB_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -968,6 +2138,54 @@ pub mod VCGT_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1005,6 +2223,54 @@ pub mod VCGT_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1042,6 +2308,54 @@ pub mod VCGE_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1079,6 +2393,54 @@ pub mod VCGE_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1116,6 +2478,48 @@ pub mod SHA1P_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1P_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1P_A1( D: ::aarchmrs_types::BitValue<1>, @@ -1150,6 +2554,48 @@ pub mod VFMS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMS_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1185,6 +2631,48 @@ pub mod VFMS_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMS_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1220,6 +2708,48 @@ pub mod VSUB_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1255,6 +2785,48 @@ pub mod VSUB_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1290,6 +2862,48 @@ pub mod VMLS_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1325,6 +2939,48 @@ pub mod VMLS_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1360,6 +3016,48 @@ pub mod VMIN_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1395,6 +3093,48 @@ pub mod VMIN_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1430,6 +3170,48 @@ pub mod VRSQRTS_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTS_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTS_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1465,6 +3247,48 @@ pub mod VRSQRTS_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTS_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTS_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1500,6 +3324,54 @@ pub mod VSHL_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_r_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1537,6 +3409,54 @@ pub mod VSHL_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_r_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1574,6 +3494,48 @@ pub mod VADD_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1608,6 +3570,48 @@ pub mod VADD_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1642,6 +3646,42 @@ pub mod VORR_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_r_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1675,6 +3715,42 @@ pub mod VORR_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_r_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1708,6 +3784,48 @@ pub mod VTST_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTST_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTST_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1742,6 +3860,48 @@ pub mod VTST_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTST_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTST_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1776,6 +3936,54 @@ pub mod VQSHL_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_r_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1813,6 +4021,54 @@ pub mod VQSHL_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_r_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1850,6 +4106,48 @@ pub mod VMLA_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1884,6 +4182,48 @@ pub mod VMLA_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1918,6 +4258,54 @@ pub mod VRSHL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHL_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1955,6 +4343,54 @@ pub mod VRSHL_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHL_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHL_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1992,6 +4428,54 @@ pub mod VQRSHL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHL_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2029,6 +4513,54 @@ pub mod VQRSHL_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHL_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHL_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2066,6 +4598,48 @@ pub mod VQDMULH_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2100,6 +4674,48 @@ pub mod VQDMULH_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2134,6 +4750,48 @@ pub mod SHA1M_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1M_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1M_A1( D: ::aarchmrs_types::BitValue<1>, @@ -2168,6 +4826,54 @@ pub mod VPADD_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADD_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADD_i_A1( D: ::aarchmrs_types::BitValue<1>, @@ -2203,6 +4909,54 @@ pub mod VMAX_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_i_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2240,6 +4994,54 @@ pub mod VMAX_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_i_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2277,6 +5079,42 @@ pub mod VORN_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORN_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORN_r_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2310,6 +5148,42 @@ pub mod VORN_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORN_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORN_r_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2343,6 +5217,54 @@ pub mod VMIN_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_i_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2380,6 +5302,54 @@ pub mod VMIN_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_i_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2417,6 +5387,54 @@ pub mod VABD_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_i_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2454,6 +5472,54 @@ pub mod VABD_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_i_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2491,6 +5557,54 @@ pub mod VABA_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABA_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABA_A1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2528,6 +5642,54 @@ pub mod VABA_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABA_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABA_A1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2565,6 +5727,48 @@ pub mod SHA1SU0_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1SU0_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1SU0_A1( D: ::aarchmrs_types::BitValue<1>, @@ -2599,6 +5803,54 @@ pub mod VPADD_f_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADD_f_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADD_f_A1( D: ::aarchmrs_types::BitValue<1>, @@ -2635,6 +5887,48 @@ pub mod VMUL_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2670,6 +5964,48 @@ pub mod VMUL_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2705,6 +6041,48 @@ pub mod VCGE_r_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -2740,6 +6118,48 @@ pub mod VCGE_r_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_A2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2775,6 +6195,48 @@ pub mod VACGE_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGE_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGE_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2810,6 +6272,48 @@ pub mod VACGE_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGE_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGE_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2845,6 +6349,48 @@ pub mod VPMAX_f_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMAX_f_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPMAX_f_A1( D: ::aarchmrs_types::BitValue<1>, @@ -2880,6 +6426,48 @@ pub mod VMAXNM_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2915,6 +6503,48 @@ pub mod VMAXNM_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2950,6 +6580,42 @@ pub mod VEOR_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEOR_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEOR_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2983,6 +6649,42 @@ pub mod VEOR_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEOR_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEOR_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3016,6 +6718,54 @@ pub mod VMUL_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_i_A1_D( op: ::aarchmrs_types::BitValue<1>, @@ -3053,6 +6803,54 @@ pub mod VMUL_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_i_A1_Q( op: ::aarchmrs_types::BitValue<1>, @@ -3090,6 +6888,48 @@ pub mod SHA256H_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256H_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256H_A1( D: ::aarchmrs_types::BitValue<1>, @@ -3124,6 +6964,54 @@ pub mod VPMAX_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMAX_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VPMAX_i_A1( U: ::aarchmrs_types::BitValue<1>, @@ -3161,6 +7049,42 @@ pub mod VBSL_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBSL_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBSL_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3194,6 +7118,42 @@ pub mod VBSL_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBSL_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBSL_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3227,6 +7187,54 @@ pub mod VPMIN_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMIN_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VPMIN_i_A1( U: ::aarchmrs_types::BitValue<1>, @@ -3264,6 +7272,48 @@ pub mod SHA256H2_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256H2_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256H2_A1( D: ::aarchmrs_types::BitValue<1>, @@ -3298,6 +7348,48 @@ pub mod VABD_f_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_f_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_f_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3333,6 +7425,48 @@ pub mod VABD_f_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_f_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_f_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3368,6 +7502,48 @@ pub mod VCGT_r_A2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_A2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_A2_D( D: ::aarchmrs_types::BitValue<1>, @@ -3403,6 +7579,48 @@ pub mod VCGT_r_A2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_A2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_A2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3438,6 +7656,48 @@ pub mod VACGT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3473,6 +7733,48 @@ pub mod VACGT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGT_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3508,6 +7810,48 @@ pub mod VPMIN_f_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMIN_f_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPMIN_f_A1( D: ::aarchmrs_types::BitValue<1>, @@ -3543,6 +7887,48 @@ pub mod VMINNM_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3578,6 +7964,48 @@ pub mod VMINNM_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3613,6 +8041,48 @@ pub mod VSUB_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3647,6 +8117,48 @@ pub mod VSUB_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3681,6 +8193,42 @@ pub mod VBIT_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIT_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIT_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3714,6 +8262,42 @@ pub mod VBIT_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIT_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIT_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3747,6 +8331,48 @@ pub mod VCEQ_r_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3781,6 +8407,48 @@ pub mod VCEQ_r_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3815,6 +8483,48 @@ pub mod VMLS_i_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_i_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_i_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3849,6 +8559,48 @@ pub mod VMLS_i_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_i_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_i_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3883,6 +8635,48 @@ pub mod VQRDMULH_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3917,6 +8711,48 @@ pub mod VQRDMULH_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3951,6 +8787,48 @@ pub mod SHA256SU1_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256SU1_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256SU1_A1( D: ::aarchmrs_types::BitValue<1>, @@ -3985,6 +8863,48 @@ pub mod VQRDMLAH_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -4019,6 +8939,48 @@ pub mod VQRDMLAH_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -4053,6 +9015,42 @@ pub mod VBIF_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIF_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIF_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -4086,6 +9084,42 @@ pub mod VBIF_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIF_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIF_A1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -4119,6 +9153,48 @@ pub mod VQRDMLSH_A1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_A1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_A1_D( D: ::aarchmrs_types::BitValue<1>, @@ -4153,6 +9229,48 @@ pub mod VQRDMLSH_A1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_A1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_A1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ms.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ms.rs index bca6565f..626c2cb8 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ms.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ms.rs @@ -12,6 +12,42 @@ pub mod VST4_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -44,6 +80,42 @@ pub mod VST4_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -76,6 +148,48 @@ pub mod VST4_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -109,6 +223,36 @@ pub mod VST1_m_A4_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A4_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A4_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -139,6 +283,36 @@ pub mod VST1_m_A4_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A4_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A4_posti( D: ::aarchmrs_types::BitValue<1>, @@ -169,6 +343,42 @@ pub mod VST1_m_A4_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A4_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A4_postr( D: ::aarchmrs_types::BitValue<1>, @@ -200,6 +410,36 @@ pub mod VST2_m_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -230,6 +470,36 @@ pub mod VST2_m_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -260,6 +530,42 @@ pub mod VST2_m_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -291,6 +597,42 @@ pub mod VST3_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -323,6 +665,42 @@ pub mod VST3_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -355,6 +733,48 @@ pub mod VST3_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -388,6 +808,36 @@ pub mod VST1_m_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -418,6 +868,36 @@ pub mod VST1_m_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -448,6 +928,42 @@ pub mod VST1_m_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -479,6 +995,36 @@ pub mod VST1_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -509,6 +1055,36 @@ pub mod VST1_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -539,6 +1115,42 @@ pub mod VST1_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -570,6 +1182,42 @@ pub mod VST2_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -602,6 +1250,42 @@ pub mod VST2_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -634,6 +1318,48 @@ pub mod VST2_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -667,6 +1393,36 @@ pub mod VST1_m_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -697,6 +1453,36 @@ pub mod VST1_m_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -727,6 +1513,42 @@ pub mod VST1_m_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -758,6 +1580,42 @@ pub mod VLD4_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -790,6 +1648,42 @@ pub mod VLD4_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -822,6 +1716,48 @@ pub mod VLD4_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -855,6 +1791,36 @@ pub mod VLD1_m_A4_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A4_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A4_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -885,6 +1851,36 @@ pub mod VLD1_m_A4_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A4_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A4_posti( D: ::aarchmrs_types::BitValue<1>, @@ -915,6 +1911,42 @@ pub mod VLD1_m_A4_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A4_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A4_postr( D: ::aarchmrs_types::BitValue<1>, @@ -946,6 +1978,36 @@ pub mod VLD2_m_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -976,6 +2038,36 @@ pub mod VLD2_m_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1006,6 +2098,42 @@ pub mod VLD2_m_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1037,6 +2165,42 @@ pub mod VLD3_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1069,6 +2233,42 @@ pub mod VLD3_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1101,6 +2301,48 @@ pub mod VLD3_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1134,6 +2376,36 @@ pub mod VLD1_m_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1164,6 +2436,36 @@ pub mod VLD1_m_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1194,6 +2496,42 @@ pub mod VLD1_m_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1225,6 +2563,36 @@ pub mod VLD1_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1255,6 +2623,36 @@ pub mod VLD1_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1285,6 +2683,42 @@ pub mod VLD1_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1316,6 +2750,42 @@ pub mod VLD2_m_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1348,6 +2818,42 @@ pub mod VLD2_m_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1380,6 +2886,48 @@ pub mod VLD2_m_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1413,6 +2961,36 @@ pub mod VLD1_m_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1443,6 +3021,36 @@ pub mod VLD1_m_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1473,6 +3081,42 @@ pub mod VLD1_m_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_A2_postr( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ssone.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ssone.rs index 1ea4f976..d2b2cc02 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ssone.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldstv_ssone.rs @@ -12,6 +12,30 @@ pub mod VST1_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod VST1_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -68,6 +116,36 @@ pub mod VST1_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -97,6 +175,30 @@ pub mod VST2_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -125,6 +227,30 @@ pub mod VST2_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -153,6 +279,36 @@ pub mod VST2_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -182,6 +338,30 @@ pub mod VST3_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -210,6 +390,30 @@ pub mod VST3_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -238,6 +442,36 @@ pub mod VST3_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -267,6 +501,30 @@ pub mod VST4_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -295,6 +553,30 @@ pub mod VST4_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -323,6 +605,36 @@ pub mod VST4_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -352,6 +664,30 @@ pub mod VST1_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -380,6 +716,30 @@ pub mod VST1_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -408,6 +768,36 @@ pub mod VST1_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -437,6 +827,30 @@ pub mod VST2_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -465,6 +879,30 @@ pub mod VST2_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -493,6 +931,36 @@ pub mod VST2_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -522,6 +990,30 @@ pub mod VST3_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -550,6 +1042,30 @@ pub mod VST3_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -578,6 +1094,36 @@ pub mod VST3_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -607,6 +1153,30 @@ pub mod VST4_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -635,6 +1205,30 @@ pub mod VST4_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -663,6 +1257,36 @@ pub mod VST4_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -692,6 +1316,30 @@ pub mod VST1_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -720,6 +1368,30 @@ pub mod VST1_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -748,6 +1420,36 @@ pub mod VST1_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -777,6 +1479,30 @@ pub mod VST2_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -805,6 +1531,30 @@ pub mod VST2_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -833,6 +1583,36 @@ pub mod VST2_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -862,6 +1642,30 @@ pub mod VST3_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -890,6 +1694,30 @@ pub mod VST3_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -918,6 +1746,36 @@ pub mod VST3_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -947,6 +1805,30 @@ pub mod VST4_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -975,6 +1857,30 @@ pub mod VST4_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1003,6 +1909,36 @@ pub mod VST4_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1032,6 +1968,30 @@ pub mod VLD1_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1060,6 +2020,30 @@ pub mod VLD1_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1088,6 +2072,36 @@ pub mod VLD1_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1117,6 +2131,30 @@ pub mod VLD2_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1145,6 +2183,30 @@ pub mod VLD2_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1173,6 +2235,36 @@ pub mod VLD2_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1202,6 +2294,30 @@ pub mod VLD3_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1230,6 +2346,30 @@ pub mod VLD3_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1258,6 +2398,36 @@ pub mod VLD3_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1287,6 +2457,30 @@ pub mod VLD4_1_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1315,6 +2509,30 @@ pub mod VLD4_1_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1343,6 +2561,36 @@ pub mod VLD4_1_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1372,6 +2620,30 @@ pub mod VLD1_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1400,6 +2672,30 @@ pub mod VLD1_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1428,6 +2724,36 @@ pub mod VLD1_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1457,6 +2783,30 @@ pub mod VLD2_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1485,6 +2835,30 @@ pub mod VLD2_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1513,6 +2887,36 @@ pub mod VLD2_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1542,6 +2946,30 @@ pub mod VLD3_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1570,6 +2998,30 @@ pub mod VLD3_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1598,6 +3050,36 @@ pub mod VLD3_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1627,6 +3109,30 @@ pub mod VLD4_1_A2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1655,6 +3161,30 @@ pub mod VLD4_1_A2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1683,6 +3213,36 @@ pub mod VLD4_1_A2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1712,6 +3272,30 @@ pub mod VLD1_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1740,6 +3324,30 @@ pub mod VLD1_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1768,6 +3376,36 @@ pub mod VLD1_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1797,6 +3435,30 @@ pub mod VLD2_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1825,6 +3487,30 @@ pub mod VLD2_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1853,6 +3539,36 @@ pub mod VLD2_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1882,6 +3598,30 @@ pub mod VLD3_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1910,6 +3650,30 @@ pub mod VLD3_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1938,6 +3702,36 @@ pub mod VLD3_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1967,6 +3761,30 @@ pub mod VLD4_1_A3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1995,6 +3813,30 @@ pub mod VLD4_1_A3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -2023,6 +3865,36 @@ pub mod VLD4_1_A3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_A3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_A3_postr( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldv_ssall.rs b/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldv_ssall.rs index 9e5f7066..0ba06f36 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldv_ssall.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/advsimdls/ldv_ssall.rs @@ -12,6 +12,42 @@ pub mod VLD1_a_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_a_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_a_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -44,6 +80,42 @@ pub mod VLD1_a_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_a_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_a_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -76,6 +148,48 @@ pub mod VLD1_a_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_a_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_a_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -109,6 +223,42 @@ pub mod VLD2_a_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_a_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_a_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -141,6 +291,42 @@ pub mod VLD2_a_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_a_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_a_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -173,6 +359,48 @@ pub mod VLD2_a_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_a_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_a_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -206,6 +434,36 @@ pub mod VLD3_a_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_a_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_a_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -236,6 +494,36 @@ pub mod VLD3_a_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_a_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_a_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -266,6 +554,42 @@ pub mod VLD3_a_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_a_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_a_A1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -298,6 +622,42 @@ pub mod VLD4_a_A1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_a_A1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_a_A1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -330,6 +690,42 @@ pub mod VLD4_a_A1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_a_A1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_a_A1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -362,6 +758,48 @@ pub mod VLD4_a_A1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_a_A1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_a_A1_postr( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/uncondhints/barriers.rs b/aarchmrs-instructions/src/A32/uncond_as/uncondhints/barriers.rs index f63dd300..e169d138 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/uncondhints/barriers.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/uncondhints/barriers.rs @@ -26,6 +26,12 @@ pub mod DSB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DSB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; #[inline] pub const fn DSB_A1( option: ::aarchmrs_types::BitValue<4>, @@ -72,6 +78,12 @@ pub mod DMB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DMB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; #[inline] pub const fn DMB_A1( option: ::aarchmrs_types::BitValue<4>, @@ -90,6 +102,12 @@ pub mod ISB_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ISB_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; #[inline] pub const fn ISB_A1( option: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_imm.rs b/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_imm.rs index 57a4128c..8a2617c8 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_imm.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_imm.rs @@ -12,6 +12,24 @@ pub mod PLI_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLI_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLI_i_A1( U: ::aarchmrs_types::BitValue<1>, @@ -37,6 +55,18 @@ pub mod PLD_l_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000010000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_l_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLD_l_A1( U: ::aarchmrs_types::BitValue<1>, @@ -59,6 +89,24 @@ pub mod PLD_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLD_i_A1( U: ::aarchmrs_types::BitValue<1>, @@ -84,6 +132,24 @@ pub mod PLDW_i_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLDW_i_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLDW_i_A1( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_reg.rs b/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_reg.rs index 98e87c11..25b3a382 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_reg.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/uncondhints/preload_reg.rs @@ -12,6 +12,24 @@ pub mod PLI_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLI_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLI_r_A1_RRX( U: ::aarchmrs_types::BitValue<1>, @@ -37,6 +55,36 @@ pub mod PLI_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLI_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLI_r_A1( U: ::aarchmrs_types::BitValue<1>, @@ -67,6 +115,36 @@ pub mod PLD_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLD_r_A1( U: ::aarchmrs_types::BitValue<1>, @@ -97,6 +175,24 @@ pub mod PLD_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLD_r_A1_RRX( U: ::aarchmrs_types::BitValue<1>, @@ -122,6 +218,36 @@ pub mod PLDW_r_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLDW_r_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLDW_r_A1( U: ::aarchmrs_types::BitValue<1>, @@ -152,6 +278,24 @@ pub mod PLDW_r_A1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLDW_r_A1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLDW_r_A1_RRX( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/cps.rs b/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/cps.rs index da5ac6a0..3ab0c7e3 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/cps.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/cps.rs @@ -12,6 +12,12 @@ pub mod SETEND_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011101111110100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETEND_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_WIDTH: u32 = 1u32; #[inline] pub const fn SETEND_A1(E: ::aarchmrs_types::BitValue<1>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -28,6 +34,30 @@ pub mod CPS_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPS_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPS_A1_AS( A: ::aarchmrs_types::BitValue<1>, @@ -54,6 +84,30 @@ pub mod CPSID_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSID_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSID_A1_AS( A: ::aarchmrs_types::BitValue<1>, @@ -80,6 +134,30 @@ pub mod CPSID_A1_ASM { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSID_A1_ASM"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSID_A1_ASM( A: ::aarchmrs_types::BitValue<1>, @@ -106,6 +184,30 @@ pub mod CPSIE_A1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSIE_A1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSIE_A1_AS( A: ::aarchmrs_types::BitValue<1>, @@ -132,6 +234,30 @@ pub mod CPSIE_A1_ASM { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSIE_A1_ASM"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSIE_A1_ASM( A: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/setpan.rs b/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/setpan.rs index 249980c9..5bc091a4 100644 --- a/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/setpan.rs +++ b/aarchmrs-instructions/src/A32/uncond_as/uncondmisc/setpan.rs @@ -12,6 +12,12 @@ pub mod SETPAN_A1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111110100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETPAN_A1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm1_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm1_WIDTH: u32 = 1u32; #[inline] pub const fn SETPAN_A1( imm1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/control/barriers.rs b/aarchmrs-instructions/src/A64/control/barriers.rs index 8d7b1db9..ece86a13 100644 --- a/aarchmrs-instructions/src/A64/control/barriers.rs +++ b/aarchmrs-instructions/src/A64/control/barriers.rs @@ -12,6 +12,12 @@ pub mod CLREX_BN_barriers { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLREX_BN_barriers"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; #[inline] pub const fn CLREX_BN_barriers( CRm: ::aarchmrs_types::BitValue<4>, @@ -30,6 +36,12 @@ pub mod DSB_BO_barriers { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DSB_BO_barriers"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; #[inline] pub const fn DSB_BO_barriers( CRm: ::aarchmrs_types::BitValue<4>, @@ -48,6 +60,12 @@ pub mod DMB_BO_barriers { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DMB_BO_barriers"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; #[inline] pub const fn DMB_BO_barriers( CRm: ::aarchmrs_types::BitValue<4>, @@ -66,6 +84,12 @@ pub mod ISB_BI_barriers { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ISB_BI_barriers"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; #[inline] pub const fn ISB_BI_barriers( CRm: ::aarchmrs_types::BitValue<4>, @@ -98,6 +122,12 @@ pub mod DSB_BOn_barriers { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DSB_BOn_barriers"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; #[inline] pub const fn DSB_BOn_barriers( imm2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/control/branch_imm.rs b/aarchmrs-instructions/src/A64/control/branch_imm.rs index 6221de90..473c5021 100644 --- a/aarchmrs-instructions/src/A64/control/branch_imm.rs +++ b/aarchmrs-instructions/src/A64/control/branch_imm.rs @@ -12,6 +12,12 @@ pub mod B_only_branch_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "B_only_branch_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm26_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm26_WIDTH: u32 = 26u32; #[inline] pub const fn B_only_branch_imm( imm26: ::aarchmrs_types::BitValue<26>, @@ -30,6 +36,12 @@ pub mod BL_only_branch_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BL_only_branch_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm26_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm26_WIDTH: u32 = 26u32; #[inline] pub const fn BL_only_branch_imm( imm26: ::aarchmrs_types::BitValue<26>, diff --git a/aarchmrs-instructions/src/A64/control/branch_reg.rs b/aarchmrs-instructions/src/A64/control/branch_reg.rs index f8f17c03..3308265f 100644 --- a/aarchmrs-instructions/src/A64/control/branch_reg.rs +++ b/aarchmrs-instructions/src/A64/control/branch_reg.rs @@ -12,6 +12,12 @@ pub mod BR_64_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BR_64_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BR_64_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -30,6 +36,12 @@ pub mod BRAAZ_64_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BRAAZ_64_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BRAAZ_64_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -48,6 +60,12 @@ pub mod BRABZ_64_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BRABZ_64_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BRABZ_64_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -66,6 +84,12 @@ pub mod BLR_64_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BLR_64_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BLR_64_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -84,6 +108,12 @@ pub mod BLRAAZ_64_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BLRAAZ_64_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BLRAAZ_64_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -102,6 +132,12 @@ pub mod BLRABZ_64_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BLRABZ_64_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BLRABZ_64_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -120,6 +156,12 @@ pub mod RET_64R_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RET_64R_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn RET_64R_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +180,12 @@ pub mod RETAASPPCR_64M_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RETAASPPCR_64M_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn RETAASPPCR_64M_branch_reg( Rm: ::aarchmrs_types::BitValue<5>, @@ -170,6 +218,12 @@ pub mod RETABSPPCR_64M_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RETABSPPCR_64M_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn RETABSPPCR_64M_branch_reg( Rm: ::aarchmrs_types::BitValue<5>, @@ -244,6 +298,12 @@ pub mod TEXIT_te_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEXIT_te_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 1u32; #[inline] pub const fn TEXIT_te_branch_reg( op1: ::aarchmrs_types::BitValue<1>, @@ -278,6 +338,18 @@ pub mod BRAA_64P_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BRAA_64P_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BRAA_64P_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -299,6 +371,18 @@ pub mod BRAB_64P_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BRAB_64P_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BRAB_64P_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -320,6 +404,18 @@ pub mod BLRAA_64P_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BLRAA_64P_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BLRAA_64P_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, @@ -341,6 +437,18 @@ pub mod BLRAB_64P_branch_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BLRAB_64P_branch_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BLRAB_64P_branch_reg( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/control/compbranch.rs b/aarchmrs-instructions/src/A64/control/compbranch.rs index e9a26034..ffe3f046 100644 --- a/aarchmrs-instructions/src/A64/control/compbranch.rs +++ b/aarchmrs-instructions/src/A64/control/compbranch.rs @@ -12,6 +12,18 @@ pub mod CBZ_32_compbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBZ_32_compbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn CBZ_32_compbranch( imm19: ::aarchmrs_types::BitValue<19>, @@ -31,6 +43,18 @@ pub mod CBNZ_32_compbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBNZ_32_compbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn CBNZ_32_compbranch( imm19: ::aarchmrs_types::BitValue<19>, @@ -50,6 +74,18 @@ pub mod CBZ_64_compbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBZ_64_compbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn CBZ_64_compbranch( imm19: ::aarchmrs_types::BitValue<19>, @@ -69,6 +105,18 @@ pub mod CBNZ_64_compbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBNZ_64_compbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn CBNZ_64_compbranch( imm19: ::aarchmrs_types::BitValue<19>, diff --git a/aarchmrs-instructions/src/A64/control/compbranch_imm.rs b/aarchmrs-instructions/src/A64/control/compbranch_imm.rs index b43a6a8b..9ea51477 100644 --- a/aarchmrs-instructions/src/A64/control/compbranch_imm.rs +++ b/aarchmrs-instructions/src/A64/control/compbranch_imm.rs @@ -12,6 +12,24 @@ pub mod CBGT_32_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBGT_32_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBGT_32_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -36,6 +54,24 @@ pub mod CBLT_32_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBLT_32_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBLT_32_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -60,6 +96,24 @@ pub mod CBHI_32_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHI_32_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBHI_32_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -84,6 +138,24 @@ pub mod CBLO_32_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBLO_32_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBLO_32_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -108,6 +180,24 @@ pub mod CBEQ_32_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBEQ_32_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBEQ_32_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -132,6 +222,24 @@ pub mod CBNE_32_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBNE_32_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBNE_32_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -156,6 +264,24 @@ pub mod CBGT_64_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBGT_64_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBGT_64_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -180,6 +306,24 @@ pub mod CBLT_64_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBLT_64_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBLT_64_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -204,6 +348,24 @@ pub mod CBHI_64_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHI_64_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBHI_64_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -228,6 +390,24 @@ pub mod CBLO_64_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBLO_64_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBLO_64_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -252,6 +432,24 @@ pub mod CBEQ_64_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBEQ_64_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBEQ_64_imm( imm6: ::aarchmrs_types::BitValue<6>, @@ -276,6 +474,24 @@ pub mod CBNE_64_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBNE_64_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn CBNE_64_imm( imm6: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/control/compbranch_regs.rs b/aarchmrs-instructions/src/A64/control/compbranch_regs.rs index 5e3e6697..63d71164 100644 --- a/aarchmrs-instructions/src/A64/control/compbranch_regs.rs +++ b/aarchmrs-instructions/src/A64/control/compbranch_regs.rs @@ -12,6 +12,24 @@ pub mod CBGT_32_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBGT_32_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBGT_32_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod CBGE_32_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBGE_32_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBGE_32_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod CBHI_32_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHI_32_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHI_32_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod CBHS_32_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHS_32_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHS_32_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod CBEQ_32_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBEQ_32_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBEQ_32_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod CBNE_32_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBNE_32_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBNE_32_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod CBGT_64_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBGT_64_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBGT_64_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod CBGE_64_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBGE_64_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBGE_64_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod CBHI_64_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHI_64_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHI_64_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod CBHS_64_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHS_64_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHS_64_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod CBEQ_64_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBEQ_64_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBEQ_64_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod CBNE_64_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBNE_64_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBNE_64_regs( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/control/compbranch_regs2.rs b/aarchmrs-instructions/src/A64/control/compbranch_regs2.rs index d1324212..f0ef4baa 100644 --- a/aarchmrs-instructions/src/A64/control/compbranch_regs2.rs +++ b/aarchmrs-instructions/src/A64/control/compbranch_regs2.rs @@ -12,6 +12,24 @@ pub mod CBBGT_8_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBBGT_8_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBBGT_8_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod CBBGE_8_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBBGE_8_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBBGE_8_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod CBBHI_8_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBBHI_8_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBBHI_8_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod CBBHS_8_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBBHS_8_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBBHS_8_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod CBBEQ_8_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBBEQ_8_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBBEQ_8_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod CBBNE_8_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBBNE_8_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBBNE_8_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod CBHGT_16_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHGT_16_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHGT_16_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod CBHGE_16_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHGE_16_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHGE_16_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod CBHHI_16_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHHI_16_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHHI_16_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod CBHHS_16_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHHS_16_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHHS_16_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod CBHEQ_16_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHEQ_16_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHEQ_16_regs( Rm: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod CBHNE_16_regs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBHNE_16_regs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CBHNE_16_regs( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/control/condbranch.rs b/aarchmrs-instructions/src/A64/control/condbranch.rs index 40b3fc8f..2cfe45b4 100644 --- a/aarchmrs-instructions/src/A64/control/condbranch.rs +++ b/aarchmrs-instructions/src/A64/control/condbranch.rs @@ -12,6 +12,18 @@ pub mod B_only_condbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "B_only_condbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn B_only_condbranch( imm19: ::aarchmrs_types::BitValue<19>, @@ -34,6 +46,18 @@ pub mod BC_only_condbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BC_only_condbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn BC_only_condbranch( imm19: ::aarchmrs_types::BitValue<19>, diff --git a/aarchmrs-instructions/src/A64/control/exception.rs b/aarchmrs-instructions/src/A64/control/exception.rs index df01e607..fecbd7c6 100644 --- a/aarchmrs-instructions/src/A64/control/exception.rs +++ b/aarchmrs-instructions/src/A64/control/exception.rs @@ -12,6 +12,12 @@ pub mod SVC_EX_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SVC_EX_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn SVC_EX_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -30,6 +36,12 @@ pub mod HVC_EX_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "HVC_EX_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn HVC_EX_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -48,6 +60,12 @@ pub mod SMC_EX_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMC_EX_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn SMC_EX_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -66,6 +84,12 @@ pub mod BRK_EX_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BRK_EX_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn BRK_EX_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -84,6 +108,12 @@ pub mod HLT_EX_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "HLT_EX_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn HLT_EX_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -102,6 +132,12 @@ pub mod DCPS1_DC_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DCPS1_DC_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn DCPS1_DC_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -120,6 +156,12 @@ pub mod DCPS2_DC_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DCPS2_DC_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn DCPS2_DC_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -138,6 +180,12 @@ pub mod DCPS3_DC_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DCPS3_DC_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn DCPS3_DC_exception( imm16: ::aarchmrs_types::BitValue<16>, @@ -156,6 +204,18 @@ pub mod TENTER_te_exception { pub const SHOULD_BE_MASK: u32 = 0b00000000000000011111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TENTER_te_exception"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 1u32; #[inline] pub const fn TENTER_te_exception( op1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/control/hints.rs b/aarchmrs-instructions/src/A64/control/hints.rs index 01aec272..9c0cb5f8 100644 --- a/aarchmrs-instructions/src/A64/control/hints.rs +++ b/aarchmrs-instructions/src/A64/control/hints.rs @@ -12,6 +12,18 @@ pub mod HINT_HM_hints { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "HINT_HM_hints"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; #[inline] pub const fn HINT_HM_hints( CRm: ::aarchmrs_types::BitValue<4>, @@ -398,6 +410,12 @@ pub mod BTI_HB_hints { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BTI_HB_hints"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 2u32; #[inline] pub const fn BTI_HB_hints( op2: ::aarchmrs_types::BitValue<2>, @@ -444,6 +462,12 @@ pub mod STSHH_HI_hints { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STSHH_HI_hints"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 1u32; #[inline] pub const fn STSHH_HI_hints( op2: ::aarchmrs_types::BitValue<1>, @@ -462,6 +486,12 @@ pub mod SHUH_HI_hints { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHUH_HI_hints"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 1u32; #[inline] pub const fn SHUH_HI_hints( op2: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/control/miscbranch.rs b/aarchmrs-instructions/src/A64/control/miscbranch.rs index db90ab5d..bbe75ea1 100644 --- a/aarchmrs-instructions/src/A64/control/miscbranch.rs +++ b/aarchmrs-instructions/src/A64/control/miscbranch.rs @@ -12,6 +12,12 @@ pub mod RETAASPPC_only_miscbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RETAASPPC_only_miscbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn RETAASPPC_only_miscbranch( imm16: ::aarchmrs_types::BitValue<16>, @@ -30,6 +36,12 @@ pub mod RETABSPPC_only_miscbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RETABSPPC_only_miscbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn RETABSPPC_only_miscbranch( imm16: ::aarchmrs_types::BitValue<16>, diff --git a/aarchmrs-instructions/src/A64/control/pstate.rs b/aarchmrs-instructions/src/A64/control/pstate.rs index 43833fe3..b5c9465b 100644 --- a/aarchmrs-instructions/src/A64/control/pstate.rs +++ b/aarchmrs-instructions/src/A64/control/pstate.rs @@ -12,6 +12,24 @@ pub mod MSR_SI_pstate { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSR_SI_pstate"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; #[inline] pub const fn MSR_SI_pstate( op1: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/control/syspairinstrs.rs b/aarchmrs-instructions/src/A64/control/syspairinstrs.rs index 191d1ed1..750a98d8 100644 --- a/aarchmrs-instructions/src/A64/control/syspairinstrs.rs +++ b/aarchmrs-instructions/src/A64/control/syspairinstrs.rs @@ -12,6 +12,36 @@ pub mod SYSP_CR_syspairinstrs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SYSP_CR_syspairinstrs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; #[inline] pub const fn SYSP_CR_syspairinstrs( op1: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/control/systeminstrs.rs b/aarchmrs-instructions/src/A64/control/systeminstrs.rs index 399ceb79..e26b473b 100644 --- a/aarchmrs-instructions/src/A64/control/systeminstrs.rs +++ b/aarchmrs-instructions/src/A64/control/systeminstrs.rs @@ -12,6 +12,36 @@ pub mod SYS_CR_systeminstrs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SYS_CR_systeminstrs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; #[inline] pub const fn SYS_CR_systeminstrs( op1: ::aarchmrs_types::BitValue<3>, @@ -39,6 +69,36 @@ pub mod SYSL_RC_systeminstrs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SYSL_RC_systeminstrs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; #[inline] pub const fn SYSL_RC_systeminstrs( op1: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/control/systeminstrswithreg.rs b/aarchmrs-instructions/src/A64/control/systeminstrswithreg.rs index 2cb8e701..f0f03d45 100644 --- a/aarchmrs-instructions/src/A64/control/systeminstrswithreg.rs +++ b/aarchmrs-instructions/src/A64/control/systeminstrswithreg.rs @@ -12,6 +12,12 @@ pub mod WFET_only_systeminstrswithreg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "WFET_only_systeminstrswithreg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn WFET_only_systeminstrswithreg( Rd: ::aarchmrs_types::BitValue<5>, @@ -30,6 +36,12 @@ pub mod WFIT_only_systeminstrswithreg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "WFIT_only_systeminstrswithreg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn WFIT_only_systeminstrswithreg( Rd: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/control/systemmove.rs b/aarchmrs-instructions/src/A64/control/systemmove.rs index 0428044b..919fc61a 100644 --- a/aarchmrs-instructions/src/A64/control/systemmove.rs +++ b/aarchmrs-instructions/src/A64/control/systemmove.rs @@ -12,6 +12,42 @@ pub mod MSR_SR_systemmove { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSR_SR_systemmove"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_WIDTH: u32 = 1u32; #[inline] pub const fn MSR_SR_systemmove( o0: ::aarchmrs_types::BitValue<1>, @@ -41,6 +77,42 @@ pub mod MRS_RS_systemmove { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRS_RS_systemmove"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_WIDTH: u32 = 1u32; #[inline] pub const fn MRS_RS_systemmove( o0: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/control/systemmovepr.rs b/aarchmrs-instructions/src/A64/control/systemmovepr.rs index 3370f92c..e25dfc70 100644 --- a/aarchmrs-instructions/src/A64/control/systemmovepr.rs +++ b/aarchmrs-instructions/src/A64/control/systemmovepr.rs @@ -12,6 +12,42 @@ pub mod MSRR_SR_systemmovepr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSRR_SR_systemmovepr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_WIDTH: u32 = 1u32; #[inline] pub const fn MSRR_SR_systemmovepr( o0: ::aarchmrs_types::BitValue<1>, @@ -41,6 +77,42 @@ pub mod MRRS_RS_systemmovepr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRRS_RS_systemmovepr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o0_WIDTH: u32 = 1u32; #[inline] pub const fn MRRS_RS_systemmovepr( o0: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/control/tchange_imm.rs b/aarchmrs-instructions/src/A64/control/tchange_imm.rs index bdb0a4ae..58fc63aa 100644 --- a/aarchmrs-instructions/src/A64/control/tchange_imm.rs +++ b/aarchmrs-instructions/src/A64/control/tchange_imm.rs @@ -12,6 +12,24 @@ pub mod TCHANGEB_tc_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000011111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TCHANGEB_tc_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 1u32; #[inline] pub const fn TCHANGEB_tc_imm( op1: ::aarchmrs_types::BitValue<1>, @@ -36,6 +54,24 @@ pub mod TCHANGEF_tc_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000011111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TCHANGEF_tc_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 1u32; #[inline] pub const fn TCHANGEF_tc_imm( op1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/control/tchange_reg.rs b/aarchmrs-instructions/src/A64/control/tchange_reg.rs index d7de7acc..870b1f72 100644 --- a/aarchmrs-instructions/src/A64/control/tchange_reg.rs +++ b/aarchmrs-instructions/src/A64/control/tchange_reg.rs @@ -12,6 +12,24 @@ pub mod TCHANGEB_tc_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TCHANGEB_tc_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 1u32; #[inline] pub const fn TCHANGEB_tc_reg( op1: ::aarchmrs_types::BitValue<1>, @@ -36,6 +54,24 @@ pub mod TCHANGEF_tc_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TCHANGEF_tc_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op1_WIDTH: u32 = 1u32; #[inline] pub const fn TCHANGEF_tc_reg( op1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/control/testbranch.rs b/aarchmrs-instructions/src/A64/control/testbranch.rs index 9974e8f1..5ba46ed5 100644 --- a/aarchmrs-instructions/src/A64/control/testbranch.rs +++ b/aarchmrs-instructions/src/A64/control/testbranch.rs @@ -12,6 +12,30 @@ pub mod TBZ_only_testbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBZ_only_testbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm14_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm14_WIDTH: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b40_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b40_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b5_OFFSET: u32 = 31u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b5_WIDTH: u32 = 1u32; #[inline] pub const fn TBZ_only_testbranch( b5: ::aarchmrs_types::BitValue<1>, @@ -37,6 +61,30 @@ pub mod TBNZ_only_testbranch { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBNZ_only_testbranch"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm14_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm14_WIDTH: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b40_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b40_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b5_OFFSET: u32 = 31u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b5_WIDTH: u32 = 1u32; #[inline] pub const fn TBNZ_only_testbranch( b5: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/dpimm/addsub_imm.rs b/aarchmrs-instructions/src/A64/dpimm/addsub_imm.rs index 48cfa873..c85a0092 100644 --- a/aarchmrs-instructions/src/A64/dpimm/addsub_imm.rs +++ b/aarchmrs-instructions/src/A64/dpimm/addsub_imm.rs @@ -12,6 +12,30 @@ pub mod ADD_32_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_32_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_32_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, @@ -37,6 +61,30 @@ pub mod ADDS_32S_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_32S_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn ADDS_32S_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, @@ -62,6 +110,30 @@ pub mod SUB_32_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_32_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn SUB_32_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, @@ -87,6 +159,30 @@ pub mod SUBS_32S_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_32S_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn SUBS_32S_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, @@ -112,6 +208,30 @@ pub mod ADD_64_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_64_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_64_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, @@ -137,6 +257,30 @@ pub mod ADDS_64S_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_64S_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn ADDS_64S_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, @@ -162,6 +306,30 @@ pub mod SUB_64_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_64_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn SUB_64_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, @@ -187,6 +355,30 @@ pub mod SUBS_64S_addsub_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_64S_addsub_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; #[inline] pub const fn SUBS_64S_addsub_imm( sh: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/dpimm/addsub_immtags.rs b/aarchmrs-instructions/src/A64/dpimm/addsub_immtags.rs index 372bd51a..7bf3318c 100644 --- a/aarchmrs-instructions/src/A64/dpimm/addsub_immtags.rs +++ b/aarchmrs-instructions/src/A64/dpimm/addsub_immtags.rs @@ -12,6 +12,30 @@ pub mod ADDG_64_addsub_immtags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001100000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDG_64_addsub_immtags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ADDG_64_addsub_immtags( imm6: ::aarchmrs_types::BitValue<6>, @@ -38,6 +62,30 @@ pub mod SUBG_64_addsub_immtags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001100000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBG_64_addsub_immtags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn SUBG_64_addsub_immtags( imm6: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/dpimm/bitfield.rs b/aarchmrs-instructions/src/A64/dpimm/bitfield.rs index ad2bf96a..bf4b809b 100644 --- a/aarchmrs-instructions/src/A64/dpimm/bitfield.rs +++ b/aarchmrs-instructions/src/A64/dpimm/bitfield.rs @@ -12,6 +12,30 @@ pub mod SBFM_32M_bitfield { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBFM_32M_bitfield"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn SBFM_32M_bitfield( immr: ::aarchmrs_types::BitValue<6>, @@ -37,6 +61,30 @@ pub mod BFM_32M_bitfield { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFM_32M_bitfield"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn BFM_32M_bitfield( immr: ::aarchmrs_types::BitValue<6>, @@ -62,6 +110,30 @@ pub mod UBFM_32M_bitfield { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UBFM_32M_bitfield"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn UBFM_32M_bitfield( immr: ::aarchmrs_types::BitValue<6>, @@ -87,6 +159,30 @@ pub mod SBFM_64M_bitfield { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBFM_64M_bitfield"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn SBFM_64M_bitfield( immr: ::aarchmrs_types::BitValue<6>, @@ -112,6 +208,30 @@ pub mod BFM_64M_bitfield { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFM_64M_bitfield"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn BFM_64M_bitfield( immr: ::aarchmrs_types::BitValue<6>, @@ -137,6 +257,30 @@ pub mod UBFM_64M_bitfield { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UBFM_64M_bitfield"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn UBFM_64M_bitfield( immr: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/dpimm/dp_1src_imm.rs b/aarchmrs-instructions/src/A64/dpimm/dp_1src_imm.rs index 66a9f2a8..bf7b9827 100644 --- a/aarchmrs-instructions/src/A64/dpimm/dp_1src_imm.rs +++ b/aarchmrs-instructions/src/A64/dpimm/dp_1src_imm.rs @@ -12,6 +12,12 @@ pub mod AUTIASPPC_only_dp_1src_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIASPPC_only_dp_1src_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn AUTIASPPC_only_dp_1src_imm( imm16: ::aarchmrs_types::BitValue<16>, @@ -30,6 +36,12 @@ pub mod AUTIBSPPC_only_dp_1src_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIBSPPC_only_dp_1src_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn AUTIBSPPC_only_dp_1src_imm( imm16: ::aarchmrs_types::BitValue<16>, diff --git a/aarchmrs-instructions/src/A64/dpimm/extract.rs b/aarchmrs-instructions/src/A64/dpimm/extract.rs index ab9fcec4..c223f6e1 100644 --- a/aarchmrs-instructions/src/A64/dpimm/extract.rs +++ b/aarchmrs-instructions/src/A64/dpimm/extract.rs @@ -12,6 +12,30 @@ pub mod EXTR_32_extract { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EXTR_32_extract"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn EXTR_32_extract( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod EXTR_64_extract { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EXTR_64_extract"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn EXTR_64_extract( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpimm/log_imm.rs b/aarchmrs-instructions/src/A64/dpimm/log_imm.rs index de6970f4..e0f5d2c1 100644 --- a/aarchmrs-instructions/src/A64/dpimm/log_imm.rs +++ b/aarchmrs-instructions/src/A64/dpimm/log_imm.rs @@ -12,6 +12,30 @@ pub mod AND_32_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_32_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn AND_32_log_imm( immr: ::aarchmrs_types::BitValue<6>, @@ -37,6 +61,30 @@ pub mod ORR_32_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_32_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn ORR_32_log_imm( immr: ::aarchmrs_types::BitValue<6>, @@ -62,6 +110,30 @@ pub mod EOR_32_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_32_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn EOR_32_log_imm( immr: ::aarchmrs_types::BitValue<6>, @@ -87,6 +159,30 @@ pub mod ANDS_32S_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_32S_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; #[inline] pub const fn ANDS_32S_log_imm( immr: ::aarchmrs_types::BitValue<6>, @@ -112,6 +208,36 @@ pub mod AND_64_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_64_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; #[inline] pub const fn AND_64_log_imm( N: ::aarchmrs_types::BitValue<1>, @@ -139,6 +265,36 @@ pub mod ORR_64_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_64_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; #[inline] pub const fn ORR_64_log_imm( N: ::aarchmrs_types::BitValue<1>, @@ -166,6 +322,36 @@ pub mod EOR_64_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_64_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; #[inline] pub const fn EOR_64_log_imm( N: ::aarchmrs_types::BitValue<1>, @@ -193,6 +379,36 @@ pub mod ANDS_64S_log_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_64S_log_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imms_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immr_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; #[inline] pub const fn ANDS_64S_log_imm( N: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/dpimm/minmax_imm.rs b/aarchmrs-instructions/src/A64/dpimm/minmax_imm.rs index 286065cf..fdb739ec 100644 --- a/aarchmrs-instructions/src/A64/dpimm/minmax_imm.rs +++ b/aarchmrs-instructions/src/A64/dpimm/minmax_imm.rs @@ -12,6 +12,24 @@ pub mod SMAX_32_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMAX_32_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn SMAX_32_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, @@ -35,6 +53,24 @@ pub mod UMAX_32U_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAX_32U_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn UMAX_32U_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, @@ -58,6 +94,24 @@ pub mod SMIN_32_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMIN_32_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn SMIN_32_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, @@ -81,6 +135,24 @@ pub mod UMIN_32U_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMIN_32U_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn UMIN_32U_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, @@ -104,6 +176,24 @@ pub mod SMAX_64_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMAX_64_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn SMAX_64_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, @@ -127,6 +217,24 @@ pub mod UMAX_64U_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAX_64U_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn UMAX_64U_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, @@ -150,6 +258,24 @@ pub mod SMIN_64_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMIN_64_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn SMIN_64_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, @@ -173,6 +299,24 @@ pub mod UMIN_64U_minmax_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMIN_64U_minmax_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn UMIN_64U_minmax_imm( imm8: ::aarchmrs_types::BitValue<8>, diff --git a/aarchmrs-instructions/src/A64/dpimm/movewide.rs b/aarchmrs-instructions/src/A64/dpimm/movewide.rs index 5683f1e9..443f60b7 100644 --- a/aarchmrs-instructions/src/A64/dpimm/movewide.rs +++ b/aarchmrs-instructions/src/A64/dpimm/movewide.rs @@ -12,6 +12,24 @@ pub mod MOVN_32_movewide { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVN_32_movewide"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_WIDTH: u32 = 1u32; #[inline] pub const fn MOVN_32_movewide( hw: ::aarchmrs_types::BitValue<1>, @@ -35,6 +53,24 @@ pub mod MOVZ_32_movewide { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVZ_32_movewide"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_WIDTH: u32 = 1u32; #[inline] pub const fn MOVZ_32_movewide( hw: ::aarchmrs_types::BitValue<1>, @@ -58,6 +94,24 @@ pub mod MOVK_32_movewide { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVK_32_movewide"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_WIDTH: u32 = 1u32; #[inline] pub const fn MOVK_32_movewide( hw: ::aarchmrs_types::BitValue<1>, @@ -81,6 +135,24 @@ pub mod MOVN_64_movewide { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVN_64_movewide"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_WIDTH: u32 = 2u32; #[inline] pub const fn MOVN_64_movewide( hw: ::aarchmrs_types::BitValue<2>, @@ -104,6 +176,24 @@ pub mod MOVZ_64_movewide { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVZ_64_movewide"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_WIDTH: u32 = 2u32; #[inline] pub const fn MOVZ_64_movewide( hw: ::aarchmrs_types::BitValue<2>, @@ -127,6 +217,24 @@ pub mod MOVK_64_movewide { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVK_64_movewide"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_hw_WIDTH: u32 = 2u32; #[inline] pub const fn MOVK_64_movewide( hw: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/dpimm/pcreladdr.rs b/aarchmrs-instructions/src/A64/dpimm/pcreladdr.rs index 3ecefd3c..369851eb 100644 --- a/aarchmrs-instructions/src/A64/dpimm/pcreladdr.rs +++ b/aarchmrs-instructions/src/A64/dpimm/pcreladdr.rs @@ -12,6 +12,24 @@ pub mod ADR_only_pcreladdr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADR_only_pcreladdr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immhi_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immhi_WIDTH: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immlo_OFFSET: u32 = 29u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immlo_WIDTH: u32 = 2u32; #[inline] pub const fn ADR_only_pcreladdr( immlo: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod ADRP_only_pcreladdr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADRP_only_pcreladdr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immhi_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immhi_WIDTH: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immlo_OFFSET: u32 = 29u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immlo_WIDTH: u32 = 2u32; #[inline] pub const fn ADRP_only_pcreladdr( immlo: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/dpreg/addsub_carry.rs b/aarchmrs-instructions/src/A64/dpreg/addsub_carry.rs index 785bb686..958e3ed8 100644 --- a/aarchmrs-instructions/src/A64/dpreg/addsub_carry.rs +++ b/aarchmrs-instructions/src/A64/dpreg/addsub_carry.rs @@ -12,6 +12,24 @@ pub mod ADC_32_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_32_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADC_32_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod ADCS_32_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_32_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADCS_32_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod SBC_32_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_32_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SBC_32_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod SBCS_32_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_32_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SBCS_32_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod ADC_64_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_64_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADC_64_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod ADCS_64_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_64_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADCS_64_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod SBC_64_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_64_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SBC_64_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod SBCS_64_addsub_carry { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_64_addsub_carry"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SBCS_64_addsub_carry( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/addsub_ext.rs b/aarchmrs-instructions/src/A64/dpreg/addsub_ext.rs index a06778f4..0389a4e3 100644 --- a/aarchmrs-instructions/src/A64/dpreg/addsub_ext.rs +++ b/aarchmrs-instructions/src/A64/dpreg/addsub_ext.rs @@ -12,6 +12,36 @@ pub mod ADD_32_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_32_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADD_32_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +69,36 @@ pub mod ADDS_32S_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_32S_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADDS_32S_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +126,36 @@ pub mod SUB_32_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_32_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUB_32_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +183,36 @@ pub mod SUBS_32S_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_32S_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUBS_32S_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, @@ -120,6 +240,36 @@ pub mod ADD_64_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_64_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADD_64_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, @@ -147,6 +297,36 @@ pub mod ADDS_64S_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_64S_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADDS_64S_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, @@ -174,6 +354,36 @@ pub mod SUB_64_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_64_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUB_64_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, @@ -201,6 +411,36 @@ pub mod SUBS_64S_addsub_ext { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_64S_addsub_ext"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUBS_64S_addsub_ext( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/addsub_pt.rs b/aarchmrs-instructions/src/A64/dpreg/addsub_pt.rs index 37361af9..81bd4462 100644 --- a/aarchmrs-instructions/src/A64/dpreg/addsub_pt.rs +++ b/aarchmrs-instructions/src/A64/dpreg/addsub_pt.rs @@ -12,6 +12,30 @@ pub mod ADDPT_64_addsub_pt { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDPT_64_addsub_pt"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADDPT_64_addsub_pt( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod SUBPT_64_addsub_pt { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBPT_64_addsub_pt"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUBPT_64_addsub_pt( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/addsub_shift.rs b/aarchmrs-instructions/src/A64/dpreg/addsub_shift.rs index 1e2a84e9..9204b238 100644 --- a/aarchmrs-instructions/src/A64/dpreg/addsub_shift.rs +++ b/aarchmrs-instructions/src/A64/dpreg/addsub_shift.rs @@ -12,6 +12,36 @@ pub mod ADD_32_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_32_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ADD_32_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod ADDS_32_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_32_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ADDS_32_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -68,6 +128,36 @@ pub mod SUB_32_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_32_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn SUB_32_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -96,6 +186,36 @@ pub mod SUBS_32_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_32_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn SUBS_32_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -124,6 +244,36 @@ pub mod ADD_64_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_64_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ADD_64_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -152,6 +302,36 @@ pub mod ADDS_64_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_64_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ADDS_64_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -180,6 +360,36 @@ pub mod SUB_64_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_64_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn SUB_64_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -208,6 +418,36 @@ pub mod SUBS_64_addsub_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_64_addsub_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn SUBS_64_addsub_shift( shift: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/dpreg/condcmp_imm.rs b/aarchmrs-instructions/src/A64/dpreg/condcmp_imm.rs index e940be00..e8c6c439 100644 --- a/aarchmrs-instructions/src/A64/dpreg/condcmp_imm.rs +++ b/aarchmrs-instructions/src/A64/dpreg/condcmp_imm.rs @@ -12,6 +12,30 @@ pub mod CCMN_32_condcmp_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMN_32_condcmp_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn CCMN_32_condcmp_imm( imm5: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod CCMP_32_condcmp_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMP_32_condcmp_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn CCMP_32_condcmp_imm( imm5: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod CCMN_64_condcmp_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMN_64_condcmp_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn CCMN_64_condcmp_imm( imm5: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod CCMP_64_condcmp_imm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMP_64_condcmp_imm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn CCMP_64_condcmp_imm( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/condcmp_reg.rs b/aarchmrs-instructions/src/A64/dpreg/condcmp_reg.rs index 463736f2..a1154ac5 100644 --- a/aarchmrs-instructions/src/A64/dpreg/condcmp_reg.rs +++ b/aarchmrs-instructions/src/A64/dpreg/condcmp_reg.rs @@ -12,6 +12,30 @@ pub mod CCMN_32_condcmp_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMN_32_condcmp_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CCMN_32_condcmp_reg( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod CCMP_32_condcmp_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMP_32_condcmp_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CCMP_32_condcmp_reg( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod CCMN_64_condcmp_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMN_64_condcmp_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CCMN_64_condcmp_reg( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod CCMP_64_condcmp_reg { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CCMP_64_condcmp_reg"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CCMP_64_condcmp_reg( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/condsel.rs b/aarchmrs-instructions/src/A64/dpreg/condsel.rs index f2bc04da..7163387a 100644 --- a/aarchmrs-instructions/src/A64/dpreg/condsel.rs +++ b/aarchmrs-instructions/src/A64/dpreg/condsel.rs @@ -12,6 +12,30 @@ pub mod CSEL_32_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSEL_32_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSEL_32_condsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod CSINC_32_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSINC_32_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSINC_32_condsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod CSINV_32_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSINV_32_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSINV_32_condsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod CSNEG_32_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSNEG_32_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSNEG_32_condsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod CSEL_64_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSEL_64_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSEL_64_condsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod CSINC_64_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSINC_64_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSINC_64_condsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod CSINV_64_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSINV_64_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSINV_64_condsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod CSNEG_64_condsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CSNEG_64_condsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CSNEG_64_condsel( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/dp_1src.rs b/aarchmrs-instructions/src/A64/dpreg/dp_1src.rs index 131bf0c8..b2e8d3a6 100644 --- a/aarchmrs-instructions/src/A64/dpreg/dp_1src.rs +++ b/aarchmrs-instructions/src/A64/dpreg/dp_1src.rs @@ -12,6 +12,18 @@ pub mod RBIT_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RBIT_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn RBIT_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod REV16_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV16_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn REV16_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod REV_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn REV_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod CLZ_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLZ_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CLZ_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -96,6 +144,18 @@ pub mod CLS_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLS_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CLS_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -117,6 +177,18 @@ pub mod CTZ_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CTZ_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CTZ_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +210,18 @@ pub mod CNT_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CNT_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CNT_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -159,6 +243,18 @@ pub mod ABS_32_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ABS_32_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn ABS_32_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -180,6 +276,18 @@ pub mod RBIT_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RBIT_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn RBIT_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -201,6 +309,18 @@ pub mod REV16_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV16_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn REV16_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -222,6 +342,18 @@ pub mod REV32_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV32_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn REV32_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -243,6 +375,18 @@ pub mod REV_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn REV_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -264,6 +408,18 @@ pub mod CLZ_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLZ_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CLZ_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -285,6 +441,18 @@ pub mod CLS_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLS_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CLS_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -306,6 +474,18 @@ pub mod CTZ_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CTZ_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CTZ_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -327,6 +507,18 @@ pub mod CNT_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CNT_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CNT_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -348,6 +540,18 @@ pub mod ABS_64_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ABS_64_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn ABS_64_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -369,6 +573,18 @@ pub mod PACIA_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACIA_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn PACIA_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -390,6 +606,18 @@ pub mod PACIB_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACIB_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn PACIB_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -411,6 +639,18 @@ pub mod PACDA_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACDA_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn PACDA_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -432,6 +672,18 @@ pub mod PACDB_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACDB_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn PACDB_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -453,6 +705,18 @@ pub mod AUTIA_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIA_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AUTIA_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -474,6 +738,18 @@ pub mod AUTIB_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIB_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AUTIB_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -495,6 +771,18 @@ pub mod AUTDA_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTDA_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AUTDA_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -516,6 +804,18 @@ pub mod AUTDB_64P_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTDB_64P_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AUTDB_64P_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -537,6 +837,12 @@ pub mod PACIZA_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACIZA_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn PACIZA_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -555,6 +861,12 @@ pub mod PACIZB_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACIZB_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn PACIZB_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -573,6 +885,12 @@ pub mod PACDZA_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACDZA_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn PACDZA_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -591,6 +909,12 @@ pub mod PACDZB_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACDZB_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn PACDZB_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -609,6 +933,12 @@ pub mod AUTIZA_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIZA_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn AUTIZA_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -627,6 +957,12 @@ pub mod AUTIZB_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIZB_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn AUTIZB_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -645,6 +981,12 @@ pub mod AUTDZA_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTDZA_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn AUTDZA_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -663,6 +1005,12 @@ pub mod AUTDZB_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTDZB_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn AUTDZB_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -681,6 +1029,12 @@ pub mod XPACI_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "XPACI_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn XPACI_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -699,6 +1053,12 @@ pub mod XPACD_64Z_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "XPACD_64Z_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; #[inline] pub const fn XPACD_64Z_dp_1src( Rd: ::aarchmrs_types::BitValue<5>, @@ -773,6 +1133,12 @@ pub mod AUTIASPPCR_64LRR_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIASPPCR_64LRR_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AUTIASPPCR_64LRR_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, @@ -791,6 +1157,12 @@ pub mod AUTIBSPPCR_64LRR_dp_1src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AUTIBSPPCR_64LRR_dp_1src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AUTIBSPPCR_64LRR_dp_1src( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/dp_2src.rs b/aarchmrs-instructions/src/A64/dpreg/dp_2src.rs index 046b3597..f84a752b 100644 --- a/aarchmrs-instructions/src/A64/dpreg/dp_2src.rs +++ b/aarchmrs-instructions/src/A64/dpreg/dp_2src.rs @@ -12,6 +12,24 @@ pub mod UDIV_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDIV_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UDIV_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod SDIV_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SDIV_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SDIV_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod LSLV_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LSLV_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LSLV_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod LSRV_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LSRV_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LSRV_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod ASRV_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ASRV_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ASRV_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod RORV_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RORV_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn RORV_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod CRC32B_32C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32B_32C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32B_32C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod CRC32H_32C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32H_32C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32H_32C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod CRC32W_32C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32W_32C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32W_32C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod CRC32CB_32C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CB_32C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32CB_32C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod CRC32CH_32C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CH_32C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32CH_32C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod CRC32CW_32C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CW_32C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32CW_32C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -300,6 +516,24 @@ pub mod SMAX_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMAX_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMAX_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -324,6 +558,24 @@ pub mod UMAX_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAX_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMAX_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -348,6 +600,24 @@ pub mod SMIN_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMIN_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMIN_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -372,6 +642,24 @@ pub mod UMIN_32_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMIN_32_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMIN_32_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -396,6 +684,24 @@ pub mod SUBP_64S_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBP_64S_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUBP_64S_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -420,6 +726,24 @@ pub mod UDIV_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDIV_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UDIV_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -444,6 +768,24 @@ pub mod SDIV_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SDIV_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SDIV_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -468,6 +810,24 @@ pub mod IRG_64I_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "IRG_64I_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn IRG_64I_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -492,6 +852,24 @@ pub mod GMI_64G_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "GMI_64G_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn GMI_64G_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -516,6 +894,24 @@ pub mod LSLV_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LSLV_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LSLV_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -540,6 +936,24 @@ pub mod LSRV_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LSRV_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LSRV_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -564,6 +978,24 @@ pub mod ASRV_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ASRV_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ASRV_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -588,6 +1020,24 @@ pub mod RORV_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RORV_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn RORV_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -612,6 +1062,24 @@ pub mod PACGA_64P_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PACGA_64P_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn PACGA_64P_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -636,6 +1104,24 @@ pub mod CRC32X_64C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32X_64C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32X_64C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -660,6 +1146,24 @@ pub mod CRC32CX_64C_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CX_64C_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CRC32CX_64C_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -684,6 +1188,24 @@ pub mod SMAX_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMAX_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMAX_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -708,6 +1230,24 @@ pub mod UMAX_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAX_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMAX_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -732,6 +1272,24 @@ pub mod SMIN_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMIN_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMIN_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -756,6 +1314,24 @@ pub mod UMIN_64_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMIN_64_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMIN_64_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, @@ -780,6 +1356,24 @@ pub mod SUBPS_64S_dp_2src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBPS_64S_dp_2src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUBPS_64S_dp_2src( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/dp_3src.rs b/aarchmrs-instructions/src/A64/dpreg/dp_3src.rs index fc226c78..88e11144 100644 --- a/aarchmrs-instructions/src/A64/dpreg/dp_3src.rs +++ b/aarchmrs-instructions/src/A64/dpreg/dp_3src.rs @@ -12,6 +12,30 @@ pub mod MADD_32A_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MADD_32A_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn MADD_32A_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod MSUB_32A_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSUB_32A_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn MSUB_32A_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod MADD_64A_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MADD_64A_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn MADD_64A_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod MSUB_64A_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSUB_64A_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn MSUB_64A_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod SMADDL_64WA_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMADDL_64WA_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMADDL_64WA_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod SMSUBL_64WA_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMSUBL_64WA_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMSUBL_64WA_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,24 @@ pub mod SMULH_64_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULH_64_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMULH_64_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -192,6 +354,30 @@ pub mod MADDPT_64A_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MADDPT_64A_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn MADDPT_64A_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -218,6 +404,30 @@ pub mod MSUBPT_64A_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSUBPT_64A_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn MSUBPT_64A_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -244,6 +454,30 @@ pub mod UMADDL_64WA_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMADDL_64WA_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMADDL_64WA_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -270,6 +504,30 @@ pub mod UMSUBL_64WA_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMSUBL_64WA_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMSUBL_64WA_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, @@ -296,6 +554,24 @@ pub mod UMULH_64_dp_3src { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMULH_64_dp_3src"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMULH_64_dp_3src( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/dpreg/log_shift.rs b/aarchmrs-instructions/src/A64/dpreg/log_shift.rs index f60e11a4..e45e77c5 100644 --- a/aarchmrs-instructions/src/A64/dpreg/log_shift.rs +++ b/aarchmrs-instructions/src/A64/dpreg/log_shift.rs @@ -12,6 +12,36 @@ pub mod AND_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn AND_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod BIC_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn BIC_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -68,6 +128,36 @@ pub mod ORR_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ORR_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -96,6 +186,36 @@ pub mod ORN_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORN_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ORN_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -124,6 +244,36 @@ pub mod EOR_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn EOR_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -152,6 +302,36 @@ pub mod EON_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EON_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn EON_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -180,6 +360,36 @@ pub mod ANDS_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ANDS_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -208,6 +418,36 @@ pub mod BICS_32_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_32_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn BICS_32_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -236,6 +476,36 @@ pub mod AND_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn AND_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -264,6 +534,36 @@ pub mod BIC_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn BIC_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -292,6 +592,36 @@ pub mod ORR_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ORR_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -320,6 +650,36 @@ pub mod ORN_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORN_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ORN_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -348,6 +708,36 @@ pub mod EOR_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn EOR_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -376,6 +766,36 @@ pub mod EON_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EON_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn EON_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -404,6 +824,36 @@ pub mod ANDS_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn ANDS_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, @@ -432,6 +882,36 @@ pub mod BICS_64_log_shift { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_64_log_shift"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_shift_WIDTH: u32 = 2u32; #[inline] pub const fn BICS_64_log_shift( shift: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/dpreg/rmif.rs b/aarchmrs-instructions/src/A64/dpreg/rmif.rs index 1112af35..54df45e4 100644 --- a/aarchmrs-instructions/src/A64/dpreg/rmif.rs +++ b/aarchmrs-instructions/src/A64/dpreg/rmif.rs @@ -12,6 +12,24 @@ pub mod RMIF_only_rmif { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RMIF_only_rmif"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn RMIF_only_rmif( imm6: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/dpreg/setf.rs b/aarchmrs-instructions/src/A64/dpreg/setf.rs index d626bcda..6fe5cf47 100644 --- a/aarchmrs-instructions/src/A64/dpreg/setf.rs +++ b/aarchmrs-instructions/src/A64/dpreg/setf.rs @@ -12,6 +12,12 @@ pub mod SETF8_only_setf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETF8_only_setf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SETF8_only_setf( Rn: ::aarchmrs_types::BitValue<5>, @@ -30,6 +36,12 @@ pub mod SETF16_only_setf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETF16_only_setf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SETF16_only_setf( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/asisdlse.rs b/aarchmrs-instructions/src/A64/ldst/asisdlse.rs index 9a5d319e..62c992ee 100644 --- a/aarchmrs-instructions/src/A64/ldst/asisdlse.rs +++ b/aarchmrs-instructions/src/A64/ldst/asisdlse.rs @@ -12,6 +12,30 @@ pub mod ST4_asisdlse_R4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlse_R4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlse_R4( Q: ::aarchmrs_types::BitValue<1>, @@ -38,6 +62,30 @@ pub mod ST1_asisdlse_R4_4v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlse_R4_4v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlse_R4_4v( Q: ::aarchmrs_types::BitValue<1>, @@ -64,6 +112,30 @@ pub mod ST3_asisdlse_R3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlse_R3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlse_R3( Q: ::aarchmrs_types::BitValue<1>, @@ -90,6 +162,30 @@ pub mod ST1_asisdlse_R3_3v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlse_R3_3v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlse_R3_3v( Q: ::aarchmrs_types::BitValue<1>, @@ -116,6 +212,30 @@ pub mod ST1_asisdlse_R1_1v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlse_R1_1v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlse_R1_1v( Q: ::aarchmrs_types::BitValue<1>, @@ -142,6 +262,30 @@ pub mod ST2_asisdlse_R2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlse_R2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlse_R2( Q: ::aarchmrs_types::BitValue<1>, @@ -168,6 +312,30 @@ pub mod ST1_asisdlse_R2_2v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlse_R2_2v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlse_R2_2v( Q: ::aarchmrs_types::BitValue<1>, @@ -194,6 +362,30 @@ pub mod LD4_asisdlse_R4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlse_R4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlse_R4( Q: ::aarchmrs_types::BitValue<1>, @@ -220,6 +412,30 @@ pub mod LD1_asisdlse_R4_4v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlse_R4_4v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlse_R4_4v( Q: ::aarchmrs_types::BitValue<1>, @@ -246,6 +462,30 @@ pub mod LD3_asisdlse_R3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlse_R3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlse_R3( Q: ::aarchmrs_types::BitValue<1>, @@ -272,6 +512,30 @@ pub mod LD1_asisdlse_R3_3v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlse_R3_3v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlse_R3_3v( Q: ::aarchmrs_types::BitValue<1>, @@ -298,6 +562,30 @@ pub mod LD1_asisdlse_R1_1v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlse_R1_1v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlse_R1_1v( Q: ::aarchmrs_types::BitValue<1>, @@ -324,6 +612,30 @@ pub mod LD2_asisdlse_R2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlse_R2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlse_R2( Q: ::aarchmrs_types::BitValue<1>, @@ -350,6 +662,30 @@ pub mod LD1_asisdlse_R2_2v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlse_R2_2v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlse_R2_2v( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/ldst/asisdlsep.rs b/aarchmrs-instructions/src/A64/ldst/asisdlsep.rs index fda2aebd..dd5db99e 100644 --- a/aarchmrs-instructions/src/A64/ldst/asisdlsep.rs +++ b/aarchmrs-instructions/src/A64/ldst/asisdlsep.rs @@ -12,6 +12,36 @@ pub mod ST4_asisdlsep_R4_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsep_R4_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsep_R4_r( Q: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod ST1_asisdlsep_R4_r4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_R4_r4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_R4_r4( Q: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod ST3_asisdlsep_R3_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsep_R3_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsep_R3_r( Q: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod ST1_asisdlsep_R3_r3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_R3_r3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_R3_r3( Q: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod ST1_asisdlsep_R1_r1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_R1_r1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_R1_r1( Q: ::aarchmrs_types::BitValue<1>, @@ -157,6 +307,36 @@ pub mod ST2_asisdlsep_R2_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsep_R2_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsep_R2_r( Q: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod ST1_asisdlsep_R2_r2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_R2_r2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_R2_r2( Q: ::aarchmrs_types::BitValue<1>, @@ -215,6 +425,30 @@ pub mod ST4_asisdlsep_I4_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsep_I4_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsep_I4_i( Q: ::aarchmrs_types::BitValue<1>, @@ -241,6 +475,30 @@ pub mod ST1_asisdlsep_I4_i4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_I4_i4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_I4_i4( Q: ::aarchmrs_types::BitValue<1>, @@ -267,6 +525,30 @@ pub mod ST3_asisdlsep_I3_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsep_I3_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsep_I3_i( Q: ::aarchmrs_types::BitValue<1>, @@ -293,6 +575,30 @@ pub mod ST1_asisdlsep_I3_i3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_I3_i3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_I3_i3( Q: ::aarchmrs_types::BitValue<1>, @@ -319,6 +625,30 @@ pub mod ST1_asisdlsep_I1_i1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_I1_i1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_I1_i1( Q: ::aarchmrs_types::BitValue<1>, @@ -345,6 +675,30 @@ pub mod ST2_asisdlsep_I2_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsep_I2_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsep_I2_i( Q: ::aarchmrs_types::BitValue<1>, @@ -371,6 +725,30 @@ pub mod ST1_asisdlsep_I2_i2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsep_I2_i2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsep_I2_i2( Q: ::aarchmrs_types::BitValue<1>, @@ -397,6 +775,36 @@ pub mod LD4_asisdlsep_R4_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsep_R4_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsep_R4_r( Q: ::aarchmrs_types::BitValue<1>, @@ -426,6 +834,36 @@ pub mod LD1_asisdlsep_R4_r4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_R4_r4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_R4_r4( Q: ::aarchmrs_types::BitValue<1>, @@ -455,6 +893,36 @@ pub mod LD3_asisdlsep_R3_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsep_R3_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsep_R3_r( Q: ::aarchmrs_types::BitValue<1>, @@ -484,6 +952,36 @@ pub mod LD1_asisdlsep_R3_r3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_R3_r3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_R3_r3( Q: ::aarchmrs_types::BitValue<1>, @@ -513,6 +1011,36 @@ pub mod LD1_asisdlsep_R1_r1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_R1_r1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_R1_r1( Q: ::aarchmrs_types::BitValue<1>, @@ -542,6 +1070,36 @@ pub mod LD2_asisdlsep_R2_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsep_R2_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsep_R2_r( Q: ::aarchmrs_types::BitValue<1>, @@ -571,6 +1129,36 @@ pub mod LD1_asisdlsep_R2_r2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_R2_r2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_R2_r2( Q: ::aarchmrs_types::BitValue<1>, @@ -600,6 +1188,30 @@ pub mod LD4_asisdlsep_I4_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsep_I4_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsep_I4_i( Q: ::aarchmrs_types::BitValue<1>, @@ -626,6 +1238,30 @@ pub mod LD1_asisdlsep_I4_i4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_I4_i4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_I4_i4( Q: ::aarchmrs_types::BitValue<1>, @@ -652,6 +1288,30 @@ pub mod LD3_asisdlsep_I3_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsep_I3_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsep_I3_i( Q: ::aarchmrs_types::BitValue<1>, @@ -678,6 +1338,30 @@ pub mod LD1_asisdlsep_I3_i3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_I3_i3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_I3_i3( Q: ::aarchmrs_types::BitValue<1>, @@ -704,6 +1388,30 @@ pub mod LD1_asisdlsep_I1_i1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_I1_i1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_I1_i1( Q: ::aarchmrs_types::BitValue<1>, @@ -730,6 +1438,30 @@ pub mod LD2_asisdlsep_I2_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsep_I2_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsep_I2_i( Q: ::aarchmrs_types::BitValue<1>, @@ -756,6 +1488,30 @@ pub mod LD1_asisdlsep_I2_i2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsep_I2_i2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsep_I2_i2( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/ldst/asisdlso.rs b/aarchmrs-instructions/src/A64/ldst/asisdlso.rs index 5078eefb..71eeb76a 100644 --- a/aarchmrs-instructions/src/A64/ldst/asisdlso.rs +++ b/aarchmrs-instructions/src/A64/ldst/asisdlso.rs @@ -12,6 +12,36 @@ pub mod ST1_asisdlso_B1_1b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlso_B1_1b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlso_B1_1b( Q: ::aarchmrs_types::BitValue<1>, @@ -40,6 +70,36 @@ pub mod ST3_asisdlso_B3_3b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlso_B3_3b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlso_B3_3b( Q: ::aarchmrs_types::BitValue<1>, @@ -68,6 +128,36 @@ pub mod ST1_asisdlso_H1_1h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlso_H1_1h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlso_H1_1h( Q: ::aarchmrs_types::BitValue<1>, @@ -97,6 +187,36 @@ pub mod ST3_asisdlso_H3_3h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlso_H3_3h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlso_H3_3h( Q: ::aarchmrs_types::BitValue<1>, @@ -126,6 +246,30 @@ pub mod ST1_asisdlso_S1_1s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlso_S1_1s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlso_S1_1s( Q: ::aarchmrs_types::BitValue<1>, @@ -153,6 +297,24 @@ pub mod ST1_asisdlso_D1_1d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlso_D1_1d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlso_D1_1d( Q: ::aarchmrs_types::BitValue<1>, @@ -177,6 +339,30 @@ pub mod ST3_asisdlso_S3_3s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlso_S3_3s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlso_S3_3s( Q: ::aarchmrs_types::BitValue<1>, @@ -204,6 +390,24 @@ pub mod ST3_asisdlso_D3_3d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlso_D3_3d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlso_D3_3d( Q: ::aarchmrs_types::BitValue<1>, @@ -228,6 +432,24 @@ pub mod STL1_asisdlso_D1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STL1_asisdlso_D1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn STL1_asisdlso_D1( Q: ::aarchmrs_types::BitValue<1>, @@ -252,6 +474,36 @@ pub mod ST2_asisdlso_B2_2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlso_B2_2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlso_B2_2b( Q: ::aarchmrs_types::BitValue<1>, @@ -280,6 +532,36 @@ pub mod ST4_asisdlso_B4_4b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlso_B4_4b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlso_B4_4b( Q: ::aarchmrs_types::BitValue<1>, @@ -308,6 +590,36 @@ pub mod ST2_asisdlso_H2_2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlso_H2_2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlso_H2_2h( Q: ::aarchmrs_types::BitValue<1>, @@ -337,6 +649,36 @@ pub mod ST4_asisdlso_H4_4h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlso_H4_4h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlso_H4_4h( Q: ::aarchmrs_types::BitValue<1>, @@ -366,6 +708,30 @@ pub mod ST2_asisdlso_S2_2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlso_S2_2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlso_S2_2s( Q: ::aarchmrs_types::BitValue<1>, @@ -393,6 +759,24 @@ pub mod ST2_asisdlso_D2_2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlso_D2_2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlso_D2_2d( Q: ::aarchmrs_types::BitValue<1>, @@ -417,6 +801,30 @@ pub mod ST4_asisdlso_S4_4s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlso_S4_4s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlso_S4_4s( Q: ::aarchmrs_types::BitValue<1>, @@ -444,6 +852,24 @@ pub mod ST4_asisdlso_D4_4d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlso_D4_4d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlso_D4_4d( Q: ::aarchmrs_types::BitValue<1>, @@ -468,6 +894,36 @@ pub mod LD1_asisdlso_B1_1b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlso_B1_1b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlso_B1_1b( Q: ::aarchmrs_types::BitValue<1>, @@ -496,6 +952,36 @@ pub mod LD3_asisdlso_B3_3b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlso_B3_3b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlso_B3_3b( Q: ::aarchmrs_types::BitValue<1>, @@ -524,6 +1010,36 @@ pub mod LD1_asisdlso_H1_1h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlso_H1_1h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlso_H1_1h( Q: ::aarchmrs_types::BitValue<1>, @@ -553,6 +1069,36 @@ pub mod LD3_asisdlso_H3_3h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlso_H3_3h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlso_H3_3h( Q: ::aarchmrs_types::BitValue<1>, @@ -582,6 +1128,30 @@ pub mod LD1_asisdlso_S1_1s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlso_S1_1s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlso_S1_1s( Q: ::aarchmrs_types::BitValue<1>, @@ -609,6 +1179,24 @@ pub mod LD1_asisdlso_D1_1d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlso_D1_1d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlso_D1_1d( Q: ::aarchmrs_types::BitValue<1>, @@ -633,6 +1221,30 @@ pub mod LD3_asisdlso_S3_3s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlso_S3_3s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlso_S3_3s( Q: ::aarchmrs_types::BitValue<1>, @@ -660,6 +1272,24 @@ pub mod LD3_asisdlso_D3_3d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlso_D3_3d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlso_D3_3d( Q: ::aarchmrs_types::BitValue<1>, @@ -684,6 +1314,30 @@ pub mod LD1R_asisdlso_R1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1R_asisdlso_R1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1R_asisdlso_R1( Q: ::aarchmrs_types::BitValue<1>, @@ -710,6 +1364,30 @@ pub mod LD3R_asisdlso_R3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3R_asisdlso_R3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3R_asisdlso_R3( Q: ::aarchmrs_types::BitValue<1>, @@ -736,6 +1414,24 @@ pub mod LDAP1_asisdlso_D1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAP1_asisdlso_D1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LDAP1_asisdlso_D1( Q: ::aarchmrs_types::BitValue<1>, @@ -760,6 +1456,36 @@ pub mod LD2_asisdlso_B2_2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlso_B2_2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlso_B2_2b( Q: ::aarchmrs_types::BitValue<1>, @@ -788,6 +1514,36 @@ pub mod LD4_asisdlso_B4_4b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlso_B4_4b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlso_B4_4b( Q: ::aarchmrs_types::BitValue<1>, @@ -816,6 +1572,36 @@ pub mod LD2_asisdlso_H2_2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlso_H2_2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlso_H2_2h( Q: ::aarchmrs_types::BitValue<1>, @@ -845,6 +1631,36 @@ pub mod LD4_asisdlso_H4_4h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlso_H4_4h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlso_H4_4h( Q: ::aarchmrs_types::BitValue<1>, @@ -874,6 +1690,30 @@ pub mod LD2_asisdlso_S2_2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlso_S2_2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlso_S2_2s( Q: ::aarchmrs_types::BitValue<1>, @@ -901,6 +1741,24 @@ pub mod LD2_asisdlso_D2_2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlso_D2_2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlso_D2_2d( Q: ::aarchmrs_types::BitValue<1>, @@ -925,6 +1783,30 @@ pub mod LD4_asisdlso_S4_4s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlso_S4_4s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlso_S4_4s( Q: ::aarchmrs_types::BitValue<1>, @@ -952,6 +1834,24 @@ pub mod LD4_asisdlso_D4_4d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlso_D4_4d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlso_D4_4d( Q: ::aarchmrs_types::BitValue<1>, @@ -976,6 +1876,30 @@ pub mod LD2R_asisdlso_R2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2R_asisdlso_R2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2R_asisdlso_R2( Q: ::aarchmrs_types::BitValue<1>, @@ -1002,6 +1926,30 @@ pub mod LD4R_asisdlso_R4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4R_asisdlso_R4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4R_asisdlso_R4( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/ldst/asisdlsop.rs b/aarchmrs-instructions/src/A64/ldst/asisdlsop.rs index 797fa44c..9ffd5d1e 100644 --- a/aarchmrs-instructions/src/A64/ldst/asisdlsop.rs +++ b/aarchmrs-instructions/src/A64/ldst/asisdlsop.rs @@ -12,6 +12,42 @@ pub mod ST1_asisdlsop_BX1_r1b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_BX1_r1b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_BX1_r1b( Q: ::aarchmrs_types::BitValue<1>, @@ -43,6 +79,42 @@ pub mod ST3_asisdlsop_BX3_r3b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_BX3_r3b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_BX3_r3b( Q: ::aarchmrs_types::BitValue<1>, @@ -74,6 +146,42 @@ pub mod ST1_asisdlsop_HX1_r1h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_HX1_r1h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_HX1_r1h( Q: ::aarchmrs_types::BitValue<1>, @@ -106,6 +214,42 @@ pub mod ST3_asisdlsop_HX3_r3h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_HX3_r3h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_HX3_r3h( Q: ::aarchmrs_types::BitValue<1>, @@ -138,6 +282,36 @@ pub mod ST1_asisdlsop_SX1_r1s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_SX1_r1s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_SX1_r1s( Q: ::aarchmrs_types::BitValue<1>, @@ -168,6 +342,30 @@ pub mod ST1_asisdlsop_DX1_r1d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_DX1_r1d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_DX1_r1d( Q: ::aarchmrs_types::BitValue<1>, @@ -195,6 +393,36 @@ pub mod ST3_asisdlsop_SX3_r3s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_SX3_r3s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_SX3_r3s( Q: ::aarchmrs_types::BitValue<1>, @@ -225,6 +453,30 @@ pub mod ST3_asisdlsop_DX3_r3d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_DX3_r3d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_DX3_r3d( Q: ::aarchmrs_types::BitValue<1>, @@ -252,6 +504,36 @@ pub mod ST1_asisdlsop_B1_i1b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_B1_i1b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_B1_i1b( Q: ::aarchmrs_types::BitValue<1>, @@ -280,6 +562,36 @@ pub mod ST3_asisdlsop_B3_i3b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_B3_i3b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_B3_i3b( Q: ::aarchmrs_types::BitValue<1>, @@ -308,6 +620,36 @@ pub mod ST1_asisdlsop_H1_i1h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_H1_i1h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_H1_i1h( Q: ::aarchmrs_types::BitValue<1>, @@ -337,6 +679,36 @@ pub mod ST3_asisdlsop_H3_i3h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_H3_i3h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_H3_i3h( Q: ::aarchmrs_types::BitValue<1>, @@ -366,6 +738,30 @@ pub mod ST1_asisdlsop_S1_i1s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_S1_i1s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_S1_i1s( Q: ::aarchmrs_types::BitValue<1>, @@ -393,6 +789,24 @@ pub mod ST1_asisdlsop_D1_i1d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST1_asisdlsop_D1_i1d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST1_asisdlsop_D1_i1d( Q: ::aarchmrs_types::BitValue<1>, @@ -417,6 +831,30 @@ pub mod ST3_asisdlsop_S3_i3s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_S3_i3s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_S3_i3s( Q: ::aarchmrs_types::BitValue<1>, @@ -444,6 +882,24 @@ pub mod ST3_asisdlsop_D3_i3d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST3_asisdlsop_D3_i3d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST3_asisdlsop_D3_i3d( Q: ::aarchmrs_types::BitValue<1>, @@ -468,6 +924,42 @@ pub mod ST2_asisdlsop_BX2_r2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_BX2_r2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_BX2_r2b( Q: ::aarchmrs_types::BitValue<1>, @@ -499,6 +991,42 @@ pub mod ST4_asisdlsop_BX4_r4b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_BX4_r4b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_BX4_r4b( Q: ::aarchmrs_types::BitValue<1>, @@ -530,6 +1058,42 @@ pub mod ST2_asisdlsop_HX2_r2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_HX2_r2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_HX2_r2h( Q: ::aarchmrs_types::BitValue<1>, @@ -562,6 +1126,42 @@ pub mod ST4_asisdlsop_HX4_r4h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_HX4_r4h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_HX4_r4h( Q: ::aarchmrs_types::BitValue<1>, @@ -594,6 +1194,36 @@ pub mod ST2_asisdlsop_SX2_r2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_SX2_r2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_SX2_r2s( Q: ::aarchmrs_types::BitValue<1>, @@ -624,6 +1254,30 @@ pub mod ST2_asisdlsop_DX2_r2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_DX2_r2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_DX2_r2d( Q: ::aarchmrs_types::BitValue<1>, @@ -651,6 +1305,36 @@ pub mod ST4_asisdlsop_SX4_r4s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_SX4_r4s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_SX4_r4s( Q: ::aarchmrs_types::BitValue<1>, @@ -681,6 +1365,30 @@ pub mod ST4_asisdlsop_DX4_r4d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_DX4_r4d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_DX4_r4d( Q: ::aarchmrs_types::BitValue<1>, @@ -708,6 +1416,36 @@ pub mod ST2_asisdlsop_B2_i2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_B2_i2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_B2_i2b( Q: ::aarchmrs_types::BitValue<1>, @@ -736,6 +1474,36 @@ pub mod ST4_asisdlsop_B4_i4b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_B4_i4b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_B4_i4b( Q: ::aarchmrs_types::BitValue<1>, @@ -764,6 +1532,36 @@ pub mod ST2_asisdlsop_H2_i2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_H2_i2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_H2_i2h( Q: ::aarchmrs_types::BitValue<1>, @@ -793,6 +1591,36 @@ pub mod ST4_asisdlsop_H4_i4h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_H4_i4h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_H4_i4h( Q: ::aarchmrs_types::BitValue<1>, @@ -822,6 +1650,30 @@ pub mod ST2_asisdlsop_S2_i2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_S2_i2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_S2_i2s( Q: ::aarchmrs_types::BitValue<1>, @@ -849,6 +1701,24 @@ pub mod ST2_asisdlsop_D2_i2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2_asisdlsop_D2_i2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST2_asisdlsop_D2_i2d( Q: ::aarchmrs_types::BitValue<1>, @@ -873,6 +1743,30 @@ pub mod ST4_asisdlsop_S4_i4s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_S4_i4s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_S4_i4s( Q: ::aarchmrs_types::BitValue<1>, @@ -900,6 +1794,24 @@ pub mod ST4_asisdlsop_D4_i4d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST4_asisdlsop_D4_i4d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ST4_asisdlsop_D4_i4d( Q: ::aarchmrs_types::BitValue<1>, @@ -924,6 +1836,42 @@ pub mod LD1_asisdlsop_BX1_r1b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_BX1_r1b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_BX1_r1b( Q: ::aarchmrs_types::BitValue<1>, @@ -955,6 +1903,42 @@ pub mod LD3_asisdlsop_BX3_r3b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_BX3_r3b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_BX3_r3b( Q: ::aarchmrs_types::BitValue<1>, @@ -986,6 +1970,42 @@ pub mod LD1_asisdlsop_HX1_r1h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_HX1_r1h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_HX1_r1h( Q: ::aarchmrs_types::BitValue<1>, @@ -1018,6 +2038,42 @@ pub mod LD3_asisdlsop_HX3_r3h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_HX3_r3h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_HX3_r3h( Q: ::aarchmrs_types::BitValue<1>, @@ -1050,6 +2106,36 @@ pub mod LD1_asisdlsop_SX1_r1s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_SX1_r1s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_SX1_r1s( Q: ::aarchmrs_types::BitValue<1>, @@ -1080,6 +2166,30 @@ pub mod LD1_asisdlsop_DX1_r1d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_DX1_r1d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_DX1_r1d( Q: ::aarchmrs_types::BitValue<1>, @@ -1107,6 +2217,36 @@ pub mod LD3_asisdlsop_SX3_r3s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_SX3_r3s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_SX3_r3s( Q: ::aarchmrs_types::BitValue<1>, @@ -1137,6 +2277,30 @@ pub mod LD3_asisdlsop_DX3_r3d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_DX3_r3d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_DX3_r3d( Q: ::aarchmrs_types::BitValue<1>, @@ -1164,6 +2328,36 @@ pub mod LD1R_asisdlsop_RX1_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1R_asisdlsop_RX1_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1R_asisdlsop_RX1_r( Q: ::aarchmrs_types::BitValue<1>, @@ -1193,6 +2387,36 @@ pub mod LD3R_asisdlsop_RX3_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3R_asisdlsop_RX3_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3R_asisdlsop_RX3_r( Q: ::aarchmrs_types::BitValue<1>, @@ -1222,6 +2446,36 @@ pub mod LD1_asisdlsop_B1_i1b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_B1_i1b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_B1_i1b( Q: ::aarchmrs_types::BitValue<1>, @@ -1250,6 +2504,36 @@ pub mod LD3_asisdlsop_B3_i3b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_B3_i3b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_B3_i3b( Q: ::aarchmrs_types::BitValue<1>, @@ -1278,6 +2562,36 @@ pub mod LD1_asisdlsop_H1_i1h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_H1_i1h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_H1_i1h( Q: ::aarchmrs_types::BitValue<1>, @@ -1307,6 +2621,36 @@ pub mod LD3_asisdlsop_H3_i3h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_H3_i3h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_H3_i3h( Q: ::aarchmrs_types::BitValue<1>, @@ -1336,6 +2680,30 @@ pub mod LD1_asisdlsop_S1_i1s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_S1_i1s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_S1_i1s( Q: ::aarchmrs_types::BitValue<1>, @@ -1363,6 +2731,24 @@ pub mod LD1_asisdlsop_D1_i1d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1_asisdlsop_D1_i1d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1_asisdlsop_D1_i1d( Q: ::aarchmrs_types::BitValue<1>, @@ -1387,6 +2773,30 @@ pub mod LD3_asisdlsop_S3_i3s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_S3_i3s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_S3_i3s( Q: ::aarchmrs_types::BitValue<1>, @@ -1414,6 +2824,24 @@ pub mod LD3_asisdlsop_D3_i3d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3_asisdlsop_D3_i3d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3_asisdlsop_D3_i3d( Q: ::aarchmrs_types::BitValue<1>, @@ -1438,6 +2866,30 @@ pub mod LD1R_asisdlsop_R1_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD1R_asisdlsop_R1_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD1R_asisdlsop_R1_i( Q: ::aarchmrs_types::BitValue<1>, @@ -1464,6 +2916,30 @@ pub mod LD3R_asisdlsop_R3_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD3R_asisdlsop_R3_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD3R_asisdlsop_R3_i( Q: ::aarchmrs_types::BitValue<1>, @@ -1490,6 +2966,42 @@ pub mod LD2_asisdlsop_BX2_r2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_BX2_r2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_BX2_r2b( Q: ::aarchmrs_types::BitValue<1>, @@ -1521,6 +3033,42 @@ pub mod LD4_asisdlsop_BX4_r4b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_BX4_r4b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_BX4_r4b( Q: ::aarchmrs_types::BitValue<1>, @@ -1552,6 +3100,42 @@ pub mod LD2_asisdlsop_HX2_r2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_HX2_r2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_HX2_r2h( Q: ::aarchmrs_types::BitValue<1>, @@ -1584,6 +3168,42 @@ pub mod LD4_asisdlsop_HX4_r4h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_HX4_r4h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_HX4_r4h( Q: ::aarchmrs_types::BitValue<1>, @@ -1616,6 +3236,36 @@ pub mod LD2_asisdlsop_SX2_r2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_SX2_r2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_SX2_r2s( Q: ::aarchmrs_types::BitValue<1>, @@ -1646,6 +3296,30 @@ pub mod LD2_asisdlsop_DX2_r2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_DX2_r2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_DX2_r2d( Q: ::aarchmrs_types::BitValue<1>, @@ -1673,6 +3347,36 @@ pub mod LD4_asisdlsop_SX4_r4s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_SX4_r4s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_SX4_r4s( Q: ::aarchmrs_types::BitValue<1>, @@ -1703,6 +3407,30 @@ pub mod LD4_asisdlsop_DX4_r4d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_DX4_r4d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_DX4_r4d( Q: ::aarchmrs_types::BitValue<1>, @@ -1730,6 +3458,36 @@ pub mod LD2R_asisdlsop_RX2_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2R_asisdlsop_RX2_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2R_asisdlsop_RX2_r( Q: ::aarchmrs_types::BitValue<1>, @@ -1759,6 +3517,36 @@ pub mod LD4R_asisdlsop_RX4_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4R_asisdlsop_RX4_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4R_asisdlsop_RX4_r( Q: ::aarchmrs_types::BitValue<1>, @@ -1788,6 +3576,36 @@ pub mod LD2_asisdlsop_B2_i2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_B2_i2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_B2_i2b( Q: ::aarchmrs_types::BitValue<1>, @@ -1816,6 +3634,36 @@ pub mod LD4_asisdlsop_B4_i4b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_B4_i4b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_B4_i4b( Q: ::aarchmrs_types::BitValue<1>, @@ -1844,6 +3692,36 @@ pub mod LD2_asisdlsop_H2_i2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_H2_i2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_H2_i2h( Q: ::aarchmrs_types::BitValue<1>, @@ -1873,6 +3751,36 @@ pub mod LD4_asisdlsop_H4_i4h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_H4_i4h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_H4_i4h( Q: ::aarchmrs_types::BitValue<1>, @@ -1902,6 +3810,30 @@ pub mod LD2_asisdlsop_S2_i2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_S2_i2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_S2_i2s( Q: ::aarchmrs_types::BitValue<1>, @@ -1929,6 +3861,24 @@ pub mod LD2_asisdlsop_D2_i2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2_asisdlsop_D2_i2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2_asisdlsop_D2_i2d( Q: ::aarchmrs_types::BitValue<1>, @@ -1953,6 +3903,30 @@ pub mod LD4_asisdlsop_S4_i4s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_S4_i4s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_S4_i4s( Q: ::aarchmrs_types::BitValue<1>, @@ -1980,6 +3954,24 @@ pub mod LD4_asisdlsop_D4_i4d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4_asisdlsop_D4_i4d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4_asisdlsop_D4_i4d( Q: ::aarchmrs_types::BitValue<1>, @@ -2004,6 +3996,30 @@ pub mod LD2R_asisdlsop_R2_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD2R_asisdlsop_R2_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD2R_asisdlsop_R2_i( Q: ::aarchmrs_types::BitValue<1>, @@ -2030,6 +4046,30 @@ pub mod LD4R_asisdlsop_R4_i { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD4R_asisdlsop_R4_i"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn LD4R_asisdlsop_R4_i( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/ldst/comswap.rs b/aarchmrs-instructions/src/A64/ldst/comswap.rs index cd904a02..d6ffadc6 100644 --- a/aarchmrs-instructions/src/A64/ldst/comswap.rs +++ b/aarchmrs-instructions/src/A64/ldst/comswap.rs @@ -12,6 +12,24 @@ pub mod CASB_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASB_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASB_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod CASLB_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASLB_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASLB_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod CASAB_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASAB_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASAB_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod CASALB_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASALB_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASALB_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod CASH_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASH_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASH_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod CASLH_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASLH_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASLH_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod CASAH_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASAH_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASAH_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod CASALH_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASALH_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASALH_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod CAS_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CAS_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CAS_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod CASL_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASL_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASL_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod CASA_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASA_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASA_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod CASAL_C32_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASAL_C32_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASAL_C32_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -300,6 +516,24 @@ pub mod CAS_C64_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CAS_C64_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CAS_C64_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -324,6 +558,24 @@ pub mod CASL_C64_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASL_C64_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASL_C64_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -348,6 +600,24 @@ pub mod CASA_C64_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASA_C64_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASA_C64_comswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -372,6 +642,24 @@ pub mod CASAL_C64_comswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASAL_C64_comswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASAL_C64_comswap( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/comswap_unpriv.rs b/aarchmrs-instructions/src/A64/ldst/comswap_unpriv.rs index 7ec5f092..b7e32d6c 100644 --- a/aarchmrs-instructions/src/A64/ldst/comswap_unpriv.rs +++ b/aarchmrs-instructions/src/A64/ldst/comswap_unpriv.rs @@ -12,6 +12,24 @@ pub mod CAST_C64_comswap_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CAST_C64_comswap_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CAST_C64_comswap_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod CASLT_C64_comswap_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASLT_C64_comswap_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASLT_C64_comswap_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod CASAT_C64_comswap_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASAT_C64_comswap_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASAT_C64_comswap_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod CASALT_C64_comswap_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASALT_C64_comswap_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASALT_C64_comswap_unpriv( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/comswappr.rs b/aarchmrs-instructions/src/A64/ldst/comswappr.rs index 9455f230..7ddf1ce8 100644 --- a/aarchmrs-instructions/src/A64/ldst/comswappr.rs +++ b/aarchmrs-instructions/src/A64/ldst/comswappr.rs @@ -12,6 +12,24 @@ pub mod CASP_CP32_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASP_CP32_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASP_CP32_comswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod CASPL_CP32_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPL_CP32_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPL_CP32_comswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod CASPA_CP32_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPA_CP32_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPA_CP32_comswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod CASPAL_CP32_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPAL_CP32_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPAL_CP32_comswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod CASP_CP64_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASP_CP64_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASP_CP64_comswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod CASPL_CP64_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPL_CP64_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPL_CP64_comswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod CASPA_CP64_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPA_CP64_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPA_CP64_comswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod CASPAL_CP64_comswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPAL_CP64_comswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPAL_CP64_comswappr( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/comswappr_unpriv.rs b/aarchmrs-instructions/src/A64/ldst/comswappr_unpriv.rs index 10898ac0..241bd8a7 100644 --- a/aarchmrs-instructions/src/A64/ldst/comswappr_unpriv.rs +++ b/aarchmrs-instructions/src/A64/ldst/comswappr_unpriv.rs @@ -12,6 +12,24 @@ pub mod CASPT_CP64_comswappr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPT_CP64_comswappr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPT_CP64_comswappr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod CASPLT_CP64_comswappr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPLT_CP64_comswappr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPLT_CP64_comswappr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod CASPAT_CP64_comswappr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPAT_CP64_comswappr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPAT_CP64_comswappr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod CASPALT_CP64_comswappr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CASPALT_CP64_comswappr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn CASPALT_CP64_comswappr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldapstl_simd.rs b/aarchmrs-instructions/src/A64/ldst/ldapstl_simd.rs index 56fc65de..97f4ae73 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldapstl_simd.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldapstl_simd.rs @@ -12,6 +12,24 @@ pub mod STLUR_B_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLUR_B_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLUR_B_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -36,6 +54,24 @@ pub mod LDAPUR_B_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPUR_B_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPUR_B_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -60,6 +96,24 @@ pub mod STLUR_Q_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLUR_Q_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLUR_Q_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -84,6 +138,24 @@ pub mod LDAPUR_Q_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPUR_Q_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPUR_Q_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -108,6 +180,24 @@ pub mod STLUR_H_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLUR_H_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLUR_H_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -132,6 +222,24 @@ pub mod LDAPUR_H_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPUR_H_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPUR_H_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -156,6 +264,24 @@ pub mod STLUR_S_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLUR_S_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLUR_S_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -180,6 +306,24 @@ pub mod LDAPUR_S_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPUR_S_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPUR_S_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -204,6 +348,24 @@ pub mod STLUR_D_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLUR_D_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLUR_D_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, @@ -228,6 +390,24 @@ pub mod LDAPUR_D_ldapstl_simd { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPUR_D_ldapstl_simd"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPUR_D_ldapstl_simd( imm9: ::aarchmrs_types::BitValue<9>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldapstl_unscaled.rs b/aarchmrs-instructions/src/A64/ldst/ldapstl_unscaled.rs index 165063b9..ff28067a 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldapstl_unscaled.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldapstl_unscaled.rs @@ -12,6 +12,24 @@ pub mod STLURB_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLURB_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLURB_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -36,6 +54,24 @@ pub mod LDAPURB_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPURB_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPURB_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -60,6 +96,24 @@ pub mod LDAPURSB_64_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPURSB_64_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPURSB_64_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -84,6 +138,24 @@ pub mod LDAPURSB_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPURSB_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPURSB_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -108,6 +180,24 @@ pub mod STLURH_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLURH_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLURH_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -132,6 +222,24 @@ pub mod LDAPURH_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPURH_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPURH_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -156,6 +264,24 @@ pub mod LDAPURSH_64_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPURSH_64_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPURSH_64_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -180,6 +306,24 @@ pub mod LDAPURSH_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPURSH_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPURSH_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -204,6 +348,24 @@ pub mod STLUR_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLUR_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLUR_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -228,6 +390,24 @@ pub mod LDAPUR_32_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPUR_32_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPUR_32_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -252,6 +432,24 @@ pub mod LDAPURSW_64_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPURSW_64_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPURSW_64_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -276,6 +474,24 @@ pub mod STLUR_64_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLUR_64_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STLUR_64_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -300,6 +516,24 @@ pub mod LDAPUR_64_ldapstl_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPUR_64_ldapstl_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDAPUR_64_ldapstl_unscaled( imm9: ::aarchmrs_types::BitValue<9>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldapstl_writeback.rs b/aarchmrs-instructions/src/A64/ldst/ldapstl_writeback.rs index d6b49d6e..12aaf29b 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldapstl_writeback.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldapstl_writeback.rs @@ -12,6 +12,18 @@ pub mod STLR_32S_ldapstl_writeback { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLR_32S_ldapstl_writeback"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLR_32S_ldapstl_writeback( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod LDAPR_32L_ldapstl_writeback { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPR_32L_ldapstl_writeback"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAPR_32L_ldapstl_writeback( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod STLR_64S_ldapstl_writeback { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLR_64S_ldapstl_writeback"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLR_64S_ldapstl_writeback( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod LDAPR_64L_ldapstl_writeback { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPR_64L_ldapstl_writeback"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAPR_64L_ldapstl_writeback( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldiappstilp.rs b/aarchmrs-instructions/src/A64/ldst/ldiappstilp.rs index f23893e7..00b8fd7e 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldiappstilp.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldiappstilp.rs @@ -12,6 +12,24 @@ pub mod STILP_32SE_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STILP_32SE_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn STILP_32SE_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod STILP_32S_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STILP_32S_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn STILP_32S_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod LDIAPP_32LE_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDIAPP_32LE_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDIAPP_32LE_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod LDIAPP_32L_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDIAPP_32L_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDIAPP_32L_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod STILP_64SS_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STILP_64SS_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn STILP_64SS_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod STILP_64S_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STILP_64S_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn STILP_64S_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod STLP_64_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLP_64_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn STLP_64_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod LDIAPP_64LS_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDIAPP_64LS_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDIAPP_64LS_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod LDIAPP_64L_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDIAPP_64L_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDIAPP_64L_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod LDAP_64_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAP_64_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDAP_64_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod LDAPP_64_ldiappstilp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPP_64_ldiappstilp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDAPP_64_ldiappstilp( Rt2: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_gcs.rs b/aarchmrs-instructions/src/A64/ldst/ldst_gcs.rs index 98ee8df5..29d68eec 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_gcs.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_gcs.rs @@ -12,6 +12,18 @@ pub mod GCSSTR_64_ldst_gcs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "GCSSTR_64_ldst_gcs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn GCSSTR_64_ldst_gcs( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod GCSSTTR_64_ldst_gcs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "GCSSTTR_64_ldst_gcs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn GCSSTTR_64_ldst_gcs( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_immpost.rs b/aarchmrs-instructions/src/A64/ldst/ldst_immpost.rs index 9e7e7fae..f27047f3 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_immpost.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_immpost.rs @@ -12,6 +12,24 @@ pub mod STRB_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STRB_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -36,6 +54,24 @@ pub mod LDRB_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRB_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -60,6 +96,24 @@ pub mod LDRSB_64_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_64_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSB_64_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -84,6 +138,24 @@ pub mod LDRSB_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSB_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -108,6 +180,24 @@ pub mod STR_B_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_B_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_B_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -132,6 +222,24 @@ pub mod LDR_B_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_B_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_B_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -156,6 +264,24 @@ pub mod STR_Q_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_Q_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_Q_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -180,6 +306,24 @@ pub mod LDR_Q_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_Q_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_Q_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -204,6 +348,24 @@ pub mod STRH_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STRH_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -228,6 +390,24 @@ pub mod LDRH_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRH_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -252,6 +432,24 @@ pub mod LDRSH_64_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_64_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSH_64_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -276,6 +474,24 @@ pub mod LDRSH_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSH_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -300,6 +516,24 @@ pub mod STR_H_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_H_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_H_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -324,6 +558,24 @@ pub mod LDR_H_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_H_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_H_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -348,6 +600,24 @@ pub mod STR_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -372,6 +642,24 @@ pub mod LDR_32_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_32_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_32_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -396,6 +684,24 @@ pub mod LDRSW_64_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSW_64_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSW_64_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -420,6 +726,24 @@ pub mod STR_S_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_S_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_S_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -444,6 +768,24 @@ pub mod LDR_S_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_S_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_S_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -468,6 +810,24 @@ pub mod STR_64_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_64_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_64_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -492,6 +852,24 @@ pub mod LDR_64_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_64_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_64_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -516,6 +894,24 @@ pub mod STR_D_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_D_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_D_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, @@ -540,6 +936,24 @@ pub mod LDR_D_ldst_immpost { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_D_ldst_immpost"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_D_ldst_immpost( imm9: ::aarchmrs_types::BitValue<9>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_immpre.rs b/aarchmrs-instructions/src/A64/ldst/ldst_immpre.rs index 689f3aee..41ed184e 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_immpre.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_immpre.rs @@ -12,6 +12,24 @@ pub mod STRB_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STRB_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -36,6 +54,24 @@ pub mod LDRB_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRB_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -60,6 +96,24 @@ pub mod LDRSB_64_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_64_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSB_64_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -84,6 +138,24 @@ pub mod LDRSB_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSB_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -108,6 +180,24 @@ pub mod STR_B_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_B_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_B_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -132,6 +222,24 @@ pub mod LDR_B_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_B_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_B_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -156,6 +264,24 @@ pub mod STR_Q_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_Q_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_Q_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -180,6 +306,24 @@ pub mod LDR_Q_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_Q_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_Q_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -204,6 +348,24 @@ pub mod STRH_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STRH_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -228,6 +390,24 @@ pub mod LDRH_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRH_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -252,6 +432,24 @@ pub mod LDRSH_64_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_64_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSH_64_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -276,6 +474,24 @@ pub mod LDRSH_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSH_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -300,6 +516,24 @@ pub mod STR_H_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_H_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_H_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -324,6 +558,24 @@ pub mod LDR_H_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_H_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_H_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -348,6 +600,24 @@ pub mod STR_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -372,6 +642,24 @@ pub mod LDR_32_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_32_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_32_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -396,6 +684,24 @@ pub mod LDRSW_64_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSW_64_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDRSW_64_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -420,6 +726,24 @@ pub mod STR_S_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_S_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_S_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -444,6 +768,24 @@ pub mod LDR_S_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_S_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_S_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -468,6 +810,24 @@ pub mod STR_64_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_64_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_64_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -492,6 +852,24 @@ pub mod LDR_64_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_64_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_64_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -516,6 +894,24 @@ pub mod STR_D_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_D_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STR_D_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, @@ -540,6 +936,24 @@ pub mod LDR_D_ldst_immpre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_D_ldst_immpre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDR_D_ldst_immpre( imm9: ::aarchmrs_types::BitValue<9>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_pac.rs b/aarchmrs-instructions/src/A64/ldst/ldst_pac.rs index d370726b..d91b5864 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_pac.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_pac.rs @@ -12,6 +12,30 @@ pub mod LDRAA_64_ldst_pac { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRAA_64_ldst_pac"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn LDRAA_64_ldst_pac( S: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod LDRAA_64W_ldst_pac { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRAA_64W_ldst_pac"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn LDRAA_64W_ldst_pac( S: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod LDRAB_64_ldst_pac { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRAB_64_ldst_pac"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn LDRAB_64_ldst_pac( S: ::aarchmrs_types::BitValue<1>, @@ -93,6 +165,30 @@ pub mod LDRAB_64W_ldst_pac { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRAB_64W_ldst_pac"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn LDRAB_64W_ldst_pac( S: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_pos.rs b/aarchmrs-instructions/src/A64/ldst/ldst_pos.rs index 96df9813..f1975e71 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_pos.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_pos.rs @@ -12,6 +12,24 @@ pub mod STRB_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STRB_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -35,6 +53,24 @@ pub mod LDRB_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDRB_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -58,6 +94,24 @@ pub mod LDRSB_64_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_64_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDRSB_64_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -81,6 +135,24 @@ pub mod LDRSB_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDRSB_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -104,6 +176,24 @@ pub mod STR_B_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_B_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STR_B_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -127,6 +217,24 @@ pub mod LDR_B_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_B_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDR_B_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -150,6 +258,24 @@ pub mod STR_Q_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_Q_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STR_Q_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -173,6 +299,24 @@ pub mod LDR_Q_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_Q_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDR_Q_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -196,6 +340,24 @@ pub mod STRH_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STRH_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -219,6 +381,24 @@ pub mod LDRH_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDRH_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -242,6 +422,24 @@ pub mod LDRSH_64_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_64_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDRSH_64_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -265,6 +463,24 @@ pub mod LDRSH_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDRSH_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -288,6 +504,24 @@ pub mod STR_H_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_H_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STR_H_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -311,6 +545,24 @@ pub mod LDR_H_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_H_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDR_H_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -334,6 +586,24 @@ pub mod STR_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STR_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -357,6 +627,24 @@ pub mod LDR_32_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_32_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDR_32_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -380,6 +668,24 @@ pub mod LDRSW_64_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSW_64_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDRSW_64_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -403,6 +709,24 @@ pub mod STR_S_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_S_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STR_S_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -426,6 +750,24 @@ pub mod LDR_S_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_S_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDR_S_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -449,6 +791,24 @@ pub mod STR_64_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_64_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STR_64_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -472,6 +832,24 @@ pub mod LDR_64_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_64_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDR_64_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -495,6 +873,24 @@ pub mod PRFM_P_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PRFM_P_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn PRFM_P_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -518,6 +914,24 @@ pub mod STR_D_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_D_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn STR_D_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, @@ -541,6 +955,24 @@ pub mod LDR_D_ldst_pos { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_D_ldst_pos"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; #[inline] pub const fn LDR_D_ldst_pos( imm12: ::aarchmrs_types::BitValue<12>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_regoff.rs b/aarchmrs-instructions/src/A64/ldst/ldst_regoff.rs index 66f75ff8..7f2b5225 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_regoff.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_regoff.rs @@ -12,6 +12,36 @@ pub mod STRB_32B_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_32B_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STRB_32B_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,30 @@ pub mod STRB_32BL_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_32BL_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STRB_32BL_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -67,6 +121,36 @@ pub mod LDRB_32B_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_32B_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRB_32B_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -95,6 +179,30 @@ pub mod LDRB_32BL_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_32BL_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRB_32BL_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -122,6 +230,36 @@ pub mod LDRSB_64B_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_64B_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRSB_64B_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -150,6 +288,30 @@ pub mod LDRSB_64BL_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_64BL_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRSB_64BL_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -177,6 +339,36 @@ pub mod LDRSB_32B_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_32B_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRSB_32B_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -205,6 +397,30 @@ pub mod LDRSB_32BL_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_32BL_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRSB_32BL_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -232,6 +448,36 @@ pub mod STR_B_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_B_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_B_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -260,6 +506,30 @@ pub mod STR_BL_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_BL_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_BL_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -287,6 +557,36 @@ pub mod LDR_B_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_B_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_B_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -315,6 +615,30 @@ pub mod LDR_BL_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_BL_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_BL_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -342,6 +666,36 @@ pub mod STR_Q_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_Q_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_Q_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -370,6 +724,36 @@ pub mod LDR_Q_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_Q_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_Q_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -398,6 +782,36 @@ pub mod STRH_32_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_32_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STRH_32_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -426,6 +840,36 @@ pub mod LDRH_32_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_32_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRH_32_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -454,6 +898,36 @@ pub mod LDRSH_64_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_64_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRSH_64_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -482,6 +956,36 @@ pub mod LDRSH_32_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_32_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRSH_32_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -510,6 +1014,36 @@ pub mod STR_H_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_H_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_H_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -538,6 +1072,36 @@ pub mod LDR_H_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_H_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_H_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -566,6 +1130,36 @@ pub mod STR_32_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_32_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_32_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -594,6 +1188,36 @@ pub mod LDR_32_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_32_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_32_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -622,6 +1246,36 @@ pub mod LDRSW_64_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSW_64_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDRSW_64_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -650,6 +1304,36 @@ pub mod STR_S_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_S_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_S_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -678,6 +1362,36 @@ pub mod LDR_S_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_S_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_S_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -706,6 +1420,36 @@ pub mod STR_64_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_64_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_64_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -734,6 +1478,36 @@ pub mod LDR_64_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_64_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_64_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -762,6 +1536,42 @@ pub mod PRFM_P_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PRFM_P_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_13_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_13_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_15_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn PRFM_P_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -793,6 +1603,42 @@ pub mod RPRFM_R_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RPRFM_R_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_13_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_13_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_15_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn RPRFM_R_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -825,6 +1671,36 @@ pub mod STR_D_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_D_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn STR_D_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, @@ -853,6 +1729,36 @@ pub mod LDR_D_ldst_regoff { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_D_ldst_regoff"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_D_ldst_regoff( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_unpriv.rs b/aarchmrs-instructions/src/A64/ldst/ldst_unpriv.rs index 49cee878..c0991901 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_unpriv.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_unpriv.rs @@ -12,6 +12,24 @@ pub mod STTRB_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTRB_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STTRB_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -36,6 +54,24 @@ pub mod LDTRB_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTRB_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTRB_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -60,6 +96,24 @@ pub mod LDTRSB_64_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTRSB_64_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTRSB_64_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -84,6 +138,24 @@ pub mod LDTRSB_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTRSB_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTRSB_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -108,6 +180,24 @@ pub mod STTRH_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTRH_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STTRH_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -132,6 +222,24 @@ pub mod LDTRH_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTRH_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTRH_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -156,6 +264,24 @@ pub mod LDTRSH_64_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTRSH_64_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTRSH_64_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -180,6 +306,24 @@ pub mod LDTRSH_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTRSH_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTRSH_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -204,6 +348,24 @@ pub mod STTR_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTR_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STTR_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -228,6 +390,24 @@ pub mod LDTR_32_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTR_32_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTR_32_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -252,6 +432,24 @@ pub mod LDTRSW_64_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTRSW_64_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTRSW_64_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -276,6 +474,24 @@ pub mod STTR_64_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTR_64_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STTR_64_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, @@ -300,6 +516,24 @@ pub mod LDTR_64_ldst_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTR_64_ldst_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDTR_64_ldst_unpriv( imm9: ::aarchmrs_types::BitValue<9>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldst_unscaled.rs b/aarchmrs-instructions/src/A64/ldst/ldst_unscaled.rs index fc5adc74..cf7cff60 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldst_unscaled.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldst_unscaled.rs @@ -12,6 +12,24 @@ pub mod STURB_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STURB_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STURB_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -36,6 +54,24 @@ pub mod LDURB_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDURB_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDURB_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -60,6 +96,24 @@ pub mod LDURSB_64_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDURSB_64_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDURSB_64_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -84,6 +138,24 @@ pub mod LDURSB_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDURSB_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDURSB_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -108,6 +180,24 @@ pub mod STUR_B_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STUR_B_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STUR_B_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -132,6 +222,24 @@ pub mod LDUR_B_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUR_B_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDUR_B_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -156,6 +264,24 @@ pub mod STUR_Q_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STUR_Q_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STUR_Q_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -180,6 +306,24 @@ pub mod LDUR_Q_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUR_Q_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDUR_Q_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -204,6 +348,24 @@ pub mod STURH_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STURH_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STURH_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -228,6 +390,24 @@ pub mod LDURH_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDURH_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDURH_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -252,6 +432,24 @@ pub mod LDURSH_64_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDURSH_64_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDURSH_64_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -276,6 +474,24 @@ pub mod LDURSH_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDURSH_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDURSH_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -300,6 +516,24 @@ pub mod STUR_H_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STUR_H_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STUR_H_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -324,6 +558,24 @@ pub mod LDUR_H_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUR_H_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDUR_H_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -348,6 +600,24 @@ pub mod STUR_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STUR_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STUR_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -372,6 +642,24 @@ pub mod LDUR_32_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUR_32_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDUR_32_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -396,6 +684,24 @@ pub mod LDURSW_64_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDURSW_64_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDURSW_64_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -420,6 +726,24 @@ pub mod STUR_S_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STUR_S_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STUR_S_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -444,6 +768,24 @@ pub mod LDUR_S_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUR_S_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDUR_S_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -468,6 +810,24 @@ pub mod STUR_64_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STUR_64_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STUR_64_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -492,6 +852,24 @@ pub mod LDUR_64_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUR_64_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDUR_64_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -516,6 +894,24 @@ pub mod PRFUM_P_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PRFUM_P_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn PRFUM_P_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -540,6 +936,24 @@ pub mod STUR_D_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STUR_D_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STUR_D_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, @@ -564,6 +978,24 @@ pub mod LDUR_D_ldst_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUR_D_ldst_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDUR_D_ldst_unscaled( imm9: ::aarchmrs_types::BitValue<9>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstexclp.rs b/aarchmrs-instructions/src/A64/ldst/ldstexclp.rs index a6157e51..5ba6d407 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstexclp.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstexclp.rs @@ -12,6 +12,30 @@ pub mod STXP_SP32_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STXP_SP32_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STXP_SP32_ldstexclp( Rs: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod STLXP_SP32_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLXP_SP32_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLXP_SP32_ldstexclp( Rs: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,24 @@ pub mod LDXP_LP32_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDXP_LP32_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDXP_LP32_ldstexclp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -87,6 +153,24 @@ pub mod LDAXP_LP32_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAXP_LP32_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDAXP_LP32_ldstexclp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -110,6 +194,30 @@ pub mod STXP_SP64_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STXP_SP64_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STXP_SP64_ldstexclp( Rs: ::aarchmrs_types::BitValue<5>, @@ -136,6 +244,30 @@ pub mod STLXP_SP64_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLXP_SP64_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLXP_SP64_ldstexclp( Rs: ::aarchmrs_types::BitValue<5>, @@ -162,6 +294,24 @@ pub mod LDXP_LP64_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDXP_LP64_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDXP_LP64_ldstexclp( Rt2: ::aarchmrs_types::BitValue<5>, @@ -185,6 +335,24 @@ pub mod LDAXP_LP64_ldstexclp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAXP_LP64_ldstexclp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDAXP_LP64_ldstexclp( Rt2: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstexclr.rs b/aarchmrs-instructions/src/A64/ldst/ldstexclr.rs index c9957f48..23917b73 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstexclr.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstexclr.rs @@ -12,6 +12,24 @@ pub mod STXRB_SR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STXRB_SR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STXRB_SR32_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod STLXRB_SR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLXRB_SR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLXRB_SR32_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,18 @@ pub mod LDXRB_LR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDXRB_LR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDXRB_LR32_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, @@ -81,6 +129,18 @@ pub mod LDAXRB_LR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAXRB_LR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAXRB_LR32_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, @@ -102,6 +162,24 @@ pub mod STXRH_SR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STXRH_SR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STXRH_SR32_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -126,6 +204,24 @@ pub mod STLXRH_SR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLXRH_SR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLXRH_SR32_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -150,6 +246,18 @@ pub mod LDXRH_LR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDXRH_LR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDXRH_LR32_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, @@ -171,6 +279,18 @@ pub mod LDAXRH_LR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAXRH_LR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAXRH_LR32_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, @@ -192,6 +312,24 @@ pub mod STXR_SR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STXR_SR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STXR_SR32_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -216,6 +354,24 @@ pub mod STLXR_SR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLXR_SR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLXR_SR32_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -240,6 +396,18 @@ pub mod LDXR_LR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDXR_LR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDXR_LR32_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, @@ -261,6 +429,18 @@ pub mod LDAXR_LR32_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAXR_LR32_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAXR_LR32_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, @@ -282,6 +462,24 @@ pub mod STXR_SR64_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STXR_SR64_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STXR_SR64_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -306,6 +504,24 @@ pub mod STLXR_SR64_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLXR_SR64_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLXR_SR64_ldstexclr( Rs: ::aarchmrs_types::BitValue<5>, @@ -330,6 +546,18 @@ pub mod LDXR_LR64_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDXR_LR64_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDXR_LR64_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, @@ -351,6 +579,18 @@ pub mod LDAXR_LR64_ldstexclr { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAXR_LR64_ldstexclr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAXR_LR64_ldstexclr( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstexclr_unpriv.rs b/aarchmrs-instructions/src/A64/ldst/ldstexclr_unpriv.rs index 4ede0a2d..8047b906 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstexclr_unpriv.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstexclr_unpriv.rs @@ -12,6 +12,24 @@ pub mod STTXR_SR32_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTXR_SR32_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STTXR_SR32_ldstexclr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod STLTXR_SR32_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLTXR_SR32_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLTXR_SR32_ldstexclr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,18 @@ pub mod LDTXR_LR32_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTXR_LR32_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDTXR_LR32_ldstexclr_unpriv( Rn: ::aarchmrs_types::BitValue<5>, @@ -81,6 +129,18 @@ pub mod LDATXR_LR32_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDATXR_LR32_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDATXR_LR32_ldstexclr_unpriv( Rn: ::aarchmrs_types::BitValue<5>, @@ -102,6 +162,24 @@ pub mod STTXR_SR64_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTXR_SR64_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STTXR_SR64_ldstexclr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -126,6 +204,24 @@ pub mod STLTXR_SR64_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLTXR_SR64_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STLTXR_SR64_ldstexclr_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -150,6 +246,18 @@ pub mod LDTXR_LR64_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTXR_LR64_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDTXR_LR64_ldstexclr_unpriv( Rn: ::aarchmrs_types::BitValue<5>, @@ -171,6 +279,18 @@ pub mod LDATXR_LR64_ldstexclr_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDATXR_LR64_ldstexclr_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDATXR_LR64_ldstexclr_unpriv( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstnapair_offs.rs b/aarchmrs-instructions/src/A64/ldst/ldstnapair_offs.rs index 5dd19f21..57793ae3 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstnapair_offs.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstnapair_offs.rs @@ -12,6 +12,30 @@ pub mod STNP_32_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STNP_32_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STNP_32_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -37,6 +61,30 @@ pub mod LDNP_32_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDNP_32_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDNP_32_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -62,6 +110,30 @@ pub mod STNP_S_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STNP_S_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STNP_S_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -87,6 +159,30 @@ pub mod LDNP_S_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDNP_S_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDNP_S_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -112,6 +208,30 @@ pub mod STNP_D_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STNP_D_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STNP_D_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -137,6 +257,30 @@ pub mod LDNP_D_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDNP_D_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDNP_D_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -162,6 +306,30 @@ pub mod STNP_64_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STNP_64_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STNP_64_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -187,6 +355,30 @@ pub mod LDNP_64_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDNP_64_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDNP_64_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -212,6 +404,30 @@ pub mod STNP_Q_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STNP_Q_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STNP_Q_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -237,6 +453,30 @@ pub mod LDNP_Q_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDNP_Q_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDNP_Q_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -262,6 +502,30 @@ pub mod STTNP_64_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTNP_64_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTNP_64_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -287,6 +551,30 @@ pub mod LDTNP_64_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTNP_64_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTNP_64_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -312,6 +600,30 @@ pub mod STTNP_Q_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTNP_Q_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTNP_Q_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, @@ -337,6 +649,30 @@ pub mod LDTNP_Q_ldstnapair_offs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTNP_Q_ldstnapair_offs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTNP_Q_ldstnapair_offs( imm7: ::aarchmrs_types::BitValue<7>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstord.rs b/aarchmrs-instructions/src/A64/ldst/ldstord.rs index 42a53ad7..23edb7c7 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstord.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstord.rs @@ -12,6 +12,18 @@ pub mod STLLRB_SL32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLLRB_SL32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLLRB_SL32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod STLRB_SL32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLRB_SL32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLRB_SL32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod LDLARB_LR32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDLARB_LR32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDLARB_LR32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod LDARB_LR32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDARB_LR32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDARB_LR32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -96,6 +144,18 @@ pub mod STLLRH_SL32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLLRH_SL32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLLRH_SL32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -117,6 +177,18 @@ pub mod STLRH_SL32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLRH_SL32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLRH_SL32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +210,18 @@ pub mod LDLARH_LR32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDLARH_LR32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDLARH_LR32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -159,6 +243,18 @@ pub mod LDARH_LR32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDARH_LR32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDARH_LR32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -180,6 +276,18 @@ pub mod STLLR_SL32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLLR_SL32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLLR_SL32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -201,6 +309,18 @@ pub mod STLR_SL32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLR_SL32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLR_SL32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -222,6 +342,18 @@ pub mod LDLAR_LR32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDLAR_LR32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDLAR_LR32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -243,6 +375,18 @@ pub mod LDAR_LR32_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAR_LR32_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAR_LR32_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -264,6 +408,18 @@ pub mod STLLR_SL64_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLLR_SL64_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLLR_SL64_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -285,6 +441,18 @@ pub mod STLR_SL64_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLR_SL64_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STLR_SL64_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -306,6 +474,18 @@ pub mod LDLAR_LR64_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDLAR_LR64_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDLAR_LR64_ldstord( Rn: ::aarchmrs_types::BitValue<5>, @@ -327,6 +507,18 @@ pub mod LDAR_LR64_ldstord { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110111110000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAR_LR64_ldstord"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAR_LR64_ldstord( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstpair_off.rs b/aarchmrs-instructions/src/A64/ldst/ldstpair_off.rs index 6b24c67b..c5b354d5 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstpair_off.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstpair_off.rs @@ -12,6 +12,30 @@ pub mod STP_32_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_32_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_32_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -37,6 +61,30 @@ pub mod LDP_32_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_32_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_32_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -62,6 +110,30 @@ pub mod STP_S_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_S_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_S_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -87,6 +159,30 @@ pub mod LDP_S_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_S_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_S_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -112,6 +208,30 @@ pub mod STGP_64_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STGP_64_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_simm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_simm7_WIDTH: u32 = 7u32; #[inline] pub const fn STGP_64_ldstpair_off( simm7: ::aarchmrs_types::BitValue<7>, @@ -137,6 +257,30 @@ pub mod LDPSW_64_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDPSW_64_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDPSW_64_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -162,6 +306,30 @@ pub mod STP_D_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_D_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_D_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -187,6 +355,30 @@ pub mod LDP_D_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_D_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_D_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -212,6 +404,30 @@ pub mod STP_64_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_64_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_64_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -237,6 +453,30 @@ pub mod LDP_64_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_64_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_64_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -262,6 +502,30 @@ pub mod STP_Q_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_Q_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_Q_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -287,6 +551,30 @@ pub mod LDP_Q_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_Q_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_Q_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -312,6 +600,30 @@ pub mod STTP_64_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTP_64_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTP_64_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -337,6 +649,30 @@ pub mod LDTP_64_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTP_64_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTP_64_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -362,6 +698,30 @@ pub mod STTP_Q_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTP_Q_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTP_Q_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, @@ -387,6 +747,30 @@ pub mod LDTP_Q_ldstpair_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTP_Q_ldstpair_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTP_Q_ldstpair_off( imm7: ::aarchmrs_types::BitValue<7>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstpair_post.rs b/aarchmrs-instructions/src/A64/ldst/ldstpair_post.rs index 8536cb45..53347dbb 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstpair_post.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstpair_post.rs @@ -12,6 +12,30 @@ pub mod STP_32_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_32_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_32_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -37,6 +61,30 @@ pub mod LDP_32_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_32_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_32_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -62,6 +110,30 @@ pub mod STP_S_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_S_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_S_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -87,6 +159,30 @@ pub mod LDP_S_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_S_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_S_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -112,6 +208,30 @@ pub mod STGP_64_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STGP_64_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_simm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_simm7_WIDTH: u32 = 7u32; #[inline] pub const fn STGP_64_ldstpair_post( simm7: ::aarchmrs_types::BitValue<7>, @@ -137,6 +257,30 @@ pub mod LDPSW_64_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDPSW_64_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDPSW_64_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -162,6 +306,30 @@ pub mod STP_D_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_D_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_D_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -187,6 +355,30 @@ pub mod LDP_D_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_D_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_D_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -212,6 +404,30 @@ pub mod STP_64_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_64_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_64_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -237,6 +453,30 @@ pub mod LDP_64_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_64_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_64_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -262,6 +502,30 @@ pub mod STP_Q_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_Q_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_Q_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -287,6 +551,30 @@ pub mod LDP_Q_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_Q_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_Q_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -312,6 +600,30 @@ pub mod STTP_64_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTP_64_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTP_64_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -337,6 +649,30 @@ pub mod LDTP_64_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTP_64_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTP_64_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -362,6 +698,30 @@ pub mod STTP_Q_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTP_Q_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTP_Q_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, @@ -387,6 +747,30 @@ pub mod LDTP_Q_ldstpair_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTP_Q_ldstpair_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTP_Q_ldstpair_post( imm7: ::aarchmrs_types::BitValue<7>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldstpair_pre.rs b/aarchmrs-instructions/src/A64/ldst/ldstpair_pre.rs index e5522895..94d25f3a 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldstpair_pre.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldstpair_pre.rs @@ -12,6 +12,30 @@ pub mod STP_32_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_32_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_32_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -37,6 +61,30 @@ pub mod LDP_32_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_32_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_32_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -62,6 +110,30 @@ pub mod STP_S_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_S_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_S_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -87,6 +159,30 @@ pub mod LDP_S_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_S_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_S_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -112,6 +208,30 @@ pub mod STGP_64_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STGP_64_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_simm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_simm7_WIDTH: u32 = 7u32; #[inline] pub const fn STGP_64_ldstpair_pre( simm7: ::aarchmrs_types::BitValue<7>, @@ -137,6 +257,30 @@ pub mod LDPSW_64_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDPSW_64_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDPSW_64_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -162,6 +306,30 @@ pub mod STP_D_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_D_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_D_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -187,6 +355,30 @@ pub mod LDP_D_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_D_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_D_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -212,6 +404,30 @@ pub mod STP_64_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_64_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_64_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -237,6 +453,30 @@ pub mod LDP_64_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_64_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_64_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -262,6 +502,30 @@ pub mod STP_Q_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STP_Q_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STP_Q_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -287,6 +551,30 @@ pub mod LDP_Q_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDP_Q_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDP_Q_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -312,6 +600,30 @@ pub mod STTP_64_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTP_64_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTP_64_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -337,6 +649,30 @@ pub mod LDTP_64_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTP_64_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTP_64_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -362,6 +698,30 @@ pub mod STTP_Q_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STTP_Q_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn STTP_Q_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, @@ -387,6 +747,30 @@ pub mod LDTP_Q_ldstpair_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTP_Q_ldstpair_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn LDTP_Q_ldstpair_pre( imm7: ::aarchmrs_types::BitValue<7>, diff --git a/aarchmrs-instructions/src/A64/ldst/ldsttags.rs b/aarchmrs-instructions/src/A64/ldst/ldsttags.rs index 09c59746..3a41cd31 100644 --- a/aarchmrs-instructions/src/A64/ldst/ldsttags.rs +++ b/aarchmrs-instructions/src/A64/ldst/ldsttags.rs @@ -12,6 +12,24 @@ pub mod STG_64Spost_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STG_64Spost_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STG_64Spost_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -36,6 +54,24 @@ pub mod STG_64Soffset_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STG_64Soffset_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STG_64Soffset_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -60,6 +96,24 @@ pub mod STG_64Spre_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STG_64Spre_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STG_64Spre_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -84,6 +138,18 @@ pub mod STZGM_64bulk_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STZGM_64bulk_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STZGM_64bulk_ldsttags( Rn: ::aarchmrs_types::BitValue<5>, @@ -105,6 +171,24 @@ pub mod LDG_64Loffset_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDG_64Loffset_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn LDG_64Loffset_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -129,6 +213,24 @@ pub mod STZG_64Spost_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STZG_64Spost_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STZG_64Spost_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -153,6 +255,24 @@ pub mod STZG_64Soffset_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STZG_64Soffset_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STZG_64Soffset_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -177,6 +297,24 @@ pub mod STZG_64Spre_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STZG_64Spre_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STZG_64Spre_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -201,6 +339,24 @@ pub mod ST2G_64Spost_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2G_64Spost_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn ST2G_64Spost_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -225,6 +381,24 @@ pub mod ST2G_64Soffset_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2G_64Soffset_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn ST2G_64Soffset_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -249,6 +423,24 @@ pub mod ST2G_64Spre_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST2G_64Spre_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn ST2G_64Spre_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -273,6 +465,18 @@ pub mod STGM_64bulk_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STGM_64bulk_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn STGM_64bulk_ldsttags( Rn: ::aarchmrs_types::BitValue<5>, @@ -294,6 +498,24 @@ pub mod STZ2G_64Spost_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STZ2G_64Spost_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STZ2G_64Spost_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -318,6 +540,24 @@ pub mod STZ2G_64Soffset_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STZ2G_64Soffset_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STZ2G_64Soffset_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -342,6 +582,24 @@ pub mod STZ2G_64Spre_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STZ2G_64Spre_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9_WIDTH: u32 = 9u32; #[inline] pub const fn STZ2G_64Spre_ldsttags( imm9: ::aarchmrs_types::BitValue<9>, @@ -366,6 +624,18 @@ pub mod LDGM_64bulk_ldsttags { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDGM_64bulk_ldsttags"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDGM_64bulk_ldsttags( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/loadlit.rs b/aarchmrs-instructions/src/A64/ldst/loadlit.rs index e79f2be7..8ada0348 100644 --- a/aarchmrs-instructions/src/A64/ldst/loadlit.rs +++ b/aarchmrs-instructions/src/A64/ldst/loadlit.rs @@ -12,6 +12,18 @@ pub mod LDR_32_loadlit { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_32_loadlit"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn LDR_32_loadlit( imm19: ::aarchmrs_types::BitValue<19>, @@ -31,6 +43,18 @@ pub mod LDR_S_loadlit { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_S_loadlit"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn LDR_S_loadlit( imm19: ::aarchmrs_types::BitValue<19>, @@ -50,6 +74,18 @@ pub mod LDR_64_loadlit { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_64_loadlit"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn LDR_64_loadlit( imm19: ::aarchmrs_types::BitValue<19>, @@ -69,6 +105,18 @@ pub mod LDR_D_loadlit { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_D_loadlit"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn LDR_D_loadlit( imm19: ::aarchmrs_types::BitValue<19>, @@ -88,6 +136,18 @@ pub mod LDRSW_64_loadlit { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSW_64_loadlit"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn LDRSW_64_loadlit( imm19: ::aarchmrs_types::BitValue<19>, @@ -107,6 +167,18 @@ pub mod LDR_Q_loadlit { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_Q_loadlit"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn LDR_Q_loadlit( imm19: ::aarchmrs_types::BitValue<19>, @@ -126,6 +198,18 @@ pub mod PRFM_P_loadlit { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PRFM_P_loadlit"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm19_WIDTH: u32 = 19u32; #[inline] pub const fn PRFM_P_loadlit( imm19: ::aarchmrs_types::BitValue<19>, diff --git a/aarchmrs-instructions/src/A64/ldst/memcms.rs b/aarchmrs-instructions/src/A64/ldst/memcms.rs index bedaf946..faf04d75 100644 --- a/aarchmrs-instructions/src/A64/ldst/memcms.rs +++ b/aarchmrs-instructions/src/A64/ldst/memcms.rs @@ -12,6 +12,30 @@ pub mod CPYFP_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFP_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFP_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod CPYFPWT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPWT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPWT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod CPYFPRT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPRT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPRT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod CPYFPT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod CPYFPWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod CPYFPWTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPWTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPWTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod CPYFPRTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPRTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPRTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod CPYFPTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -220,6 +412,30 @@ pub mod CPYFPRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -246,6 +462,30 @@ pub mod CPYFPWTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPWTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPWTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -272,6 +512,30 @@ pub mod CPYFPRTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPRTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPRTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -298,6 +562,30 @@ pub mod CPYFPTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -324,6 +612,30 @@ pub mod CPYFPN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -350,6 +662,30 @@ pub mod CPYFPWTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPWTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPWTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -376,6 +712,30 @@ pub mod CPYFPRTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPRTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPRTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -402,6 +762,30 @@ pub mod CPYFPTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFPTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFPTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -428,6 +812,30 @@ pub mod CPYFM_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFM_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFM_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -454,6 +862,30 @@ pub mod CPYFMWT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMWT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMWT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -480,6 +912,30 @@ pub mod CPYFMRT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMRT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMRT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -506,6 +962,30 @@ pub mod CPYFMT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -532,6 +1012,30 @@ pub mod CPYFMWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -558,6 +1062,30 @@ pub mod CPYFMWTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMWTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMWTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -584,6 +1112,30 @@ pub mod CPYFMRTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMRTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMRTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -610,6 +1162,30 @@ pub mod CPYFMTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -636,6 +1212,30 @@ pub mod CPYFMRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -662,6 +1262,30 @@ pub mod CPYFMWTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMWTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMWTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -688,6 +1312,30 @@ pub mod CPYFMRTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMRTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMRTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -714,6 +1362,30 @@ pub mod CPYFMTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -740,6 +1412,30 @@ pub mod CPYFMN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -766,6 +1462,30 @@ pub mod CPYFMWTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMWTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMWTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -792,6 +1512,30 @@ pub mod CPYFMRTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMRTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMRTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -818,6 +1562,30 @@ pub mod CPYFMTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFMTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFMTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -844,6 +1612,30 @@ pub mod CPYFE_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFE_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFE_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -870,6 +1662,30 @@ pub mod CPYFEWT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFEWT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFEWT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -896,6 +1712,30 @@ pub mod CPYFERT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFERT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFERT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -922,6 +1762,30 @@ pub mod CPYFET_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFET_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFET_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -948,6 +1812,30 @@ pub mod CPYFEWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFEWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFEWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -974,6 +1862,30 @@ pub mod CPYFEWTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFEWTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFEWTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1000,6 +1912,30 @@ pub mod CPYFERTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFERTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFERTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1026,6 +1962,30 @@ pub mod CPYFETWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFETWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFETWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1052,6 +2012,30 @@ pub mod CPYFERN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFERN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFERN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1078,6 +2062,30 @@ pub mod CPYFEWTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFEWTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFEWTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1104,6 +2112,30 @@ pub mod CPYFERTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFERTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFERTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1130,6 +2162,30 @@ pub mod CPYFETRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFETRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFETRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1156,6 +2212,30 @@ pub mod CPYFEN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFEN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFEN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1182,6 +2262,30 @@ pub mod CPYFEWTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFEWTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFEWTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1208,6 +2312,30 @@ pub mod CPYFERTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFERTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFERTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1234,6 +2362,30 @@ pub mod CPYFETN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYFETN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYFETN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1260,6 +2412,30 @@ pub mod SETP_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETP_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETP_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1286,6 +2462,30 @@ pub mod SETPT_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETPT_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETPT_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1312,6 +2512,30 @@ pub mod SETPN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETPN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETPN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1338,6 +2562,30 @@ pub mod SETPTN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETPTN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETPTN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1364,6 +2612,30 @@ pub mod SETM_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETM_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETM_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1390,6 +2662,30 @@ pub mod SETMT_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETMT_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETMT_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1416,6 +2712,30 @@ pub mod SETMN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETMN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETMN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1442,6 +2762,30 @@ pub mod SETMTN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETMTN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETMTN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1468,6 +2812,30 @@ pub mod SETE_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETE_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETE_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1494,6 +2862,30 @@ pub mod SETET_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETET_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETET_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1520,6 +2912,30 @@ pub mod SETEN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETEN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETEN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1546,6 +2962,30 @@ pub mod SETETN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETETN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETETN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1572,6 +3012,30 @@ pub mod CPYP_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYP_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYP_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1598,6 +3062,30 @@ pub mod CPYPWT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPWT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPWT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1624,6 +3112,30 @@ pub mod CPYPRT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPRT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPRT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1650,6 +3162,30 @@ pub mod CPYPT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1676,6 +3212,30 @@ pub mod CPYPWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1702,6 +3262,30 @@ pub mod CPYPWTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPWTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPWTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1728,6 +3312,30 @@ pub mod CPYPRTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPRTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPRTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1754,6 +3362,30 @@ pub mod CPYPTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1780,6 +3412,30 @@ pub mod CPYPRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1806,6 +3462,30 @@ pub mod CPYPWTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPWTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPWTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1832,6 +3512,30 @@ pub mod CPYPRTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPRTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPRTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1858,6 +3562,30 @@ pub mod CPYPTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1884,6 +3612,30 @@ pub mod CPYPN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1910,6 +3662,30 @@ pub mod CPYPWTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPWTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPWTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1936,6 +3712,30 @@ pub mod CPYPRTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPRTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPRTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1962,6 +3762,30 @@ pub mod CPYPTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYPTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYPTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -1988,6 +3812,30 @@ pub mod CPYM_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYM_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYM_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2014,6 +3862,30 @@ pub mod CPYMWT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMWT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMWT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2040,6 +3912,30 @@ pub mod CPYMRT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMRT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMRT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2066,6 +3962,30 @@ pub mod CPYMT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2092,6 +4012,30 @@ pub mod CPYMWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2118,6 +4062,30 @@ pub mod CPYMWTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMWTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMWTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2144,6 +4112,30 @@ pub mod CPYMRTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMRTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMRTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2170,6 +4162,30 @@ pub mod CPYMTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2196,6 +4212,30 @@ pub mod CPYMRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2222,6 +4262,30 @@ pub mod CPYMWTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMWTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMWTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2248,6 +4312,30 @@ pub mod CPYMRTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMRTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMRTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2274,6 +4362,30 @@ pub mod CPYMTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2300,6 +4412,30 @@ pub mod CPYMN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2326,6 +4462,30 @@ pub mod CPYMWTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMWTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMWTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2352,6 +4512,30 @@ pub mod CPYMRTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMRTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMRTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2378,6 +4562,30 @@ pub mod CPYMTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYMTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYMTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2404,6 +4612,30 @@ pub mod CPYE_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYE_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYE_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2430,6 +4662,30 @@ pub mod CPYEWT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYEWT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYEWT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2456,6 +4712,30 @@ pub mod CPYERT_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYERT_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYERT_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2482,6 +4762,30 @@ pub mod CPYET_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYET_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYET_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2508,6 +4812,30 @@ pub mod CPYEWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYEWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYEWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2534,6 +4862,30 @@ pub mod CPYEWTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYEWTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYEWTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2560,6 +4912,30 @@ pub mod CPYERTWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYERTWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYERTWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2586,6 +4962,30 @@ pub mod CPYETWN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYETWN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYETWN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2612,6 +5012,30 @@ pub mod CPYERN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYERN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYERN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2638,6 +5062,30 @@ pub mod CPYEWTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYEWTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYEWTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2664,6 +5112,30 @@ pub mod CPYERTRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYERTRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYERTRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2690,6 +5162,30 @@ pub mod CPYETRN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYETRN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYETRN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2716,6 +5212,30 @@ pub mod CPYEN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYEN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYEN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2742,6 +5262,30 @@ pub mod CPYEWTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYEWTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYEWTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2768,6 +5312,30 @@ pub mod CPYERTN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYERTN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYERTN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2794,6 +5362,30 @@ pub mod CPYETN_CPY_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPYETN_CPY_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn CPYETN_CPY_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2820,6 +5412,30 @@ pub mod SETGP_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGP_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGP_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2846,6 +5462,30 @@ pub mod SETGPT_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGPT_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGPT_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2872,6 +5512,30 @@ pub mod SETGPN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGPN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGPN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2898,6 +5562,30 @@ pub mod SETGPTN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGPTN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGPTN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2924,6 +5612,30 @@ pub mod SETGM_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGM_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGM_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2950,6 +5662,30 @@ pub mod SETGMT_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGMT_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGMT_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -2976,6 +5712,30 @@ pub mod SETGMN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGMN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGMN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -3002,6 +5762,30 @@ pub mod SETGMTN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGMTN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGMTN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -3028,6 +5812,30 @@ pub mod SETGE_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGE_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGE_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -3054,6 +5862,30 @@ pub mod SETGET_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGET_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGET_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -3080,6 +5912,30 @@ pub mod SETGEN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGEN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGEN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, @@ -3106,6 +5962,30 @@ pub mod SETGETN_SET_memcms { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGETN_SET_memcms"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGETN_SET_memcms( sz: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/ldst/memop.rs b/aarchmrs-instructions/src/A64/ldst/memop.rs index b9dcc065..9801e360 100644 --- a/aarchmrs-instructions/src/A64/ldst/memop.rs +++ b/aarchmrs-instructions/src/A64/ldst/memop.rs @@ -12,6 +12,24 @@ pub mod LDADDB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod LDCLRB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod LDEORB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod LDSETB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod LDSMAXB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod LDSMINB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod LDUMAXB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod LDUMINB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod SWPB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod RCWCLR_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLR_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLR_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod RCWSWP_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWP_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWP_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod RCWSET_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSET_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSET_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -300,6 +516,24 @@ pub mod LDADDLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -324,6 +558,24 @@ pub mod LDCLRLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -348,6 +600,24 @@ pub mod LDEORLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -372,6 +642,24 @@ pub mod LDSETLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -396,6 +684,24 @@ pub mod LDSMAXLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -420,6 +726,24 @@ pub mod LDSMINLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -444,6 +768,24 @@ pub mod LDUMAXLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -468,6 +810,24 @@ pub mod LDUMINLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -492,6 +852,24 @@ pub mod SWPLB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPLB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPLB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -516,6 +894,24 @@ pub mod RCWCLRL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLRL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLRL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -540,6 +936,24 @@ pub mod RCWSWPL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWPL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWPL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -564,6 +978,24 @@ pub mod RCWSETL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSETL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSETL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -588,6 +1020,24 @@ pub mod LDADDAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -612,6 +1062,24 @@ pub mod LDCLRAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -636,6 +1104,24 @@ pub mod LDEORAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -660,6 +1146,24 @@ pub mod LDSETAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -684,6 +1188,24 @@ pub mod LDSMAXAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -708,6 +1230,24 @@ pub mod LDSMINAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -732,6 +1272,24 @@ pub mod LDUMAXAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -756,6 +1314,24 @@ pub mod LDUMINAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -780,6 +1356,24 @@ pub mod SWPAB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPAB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPAB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -804,6 +1398,24 @@ pub mod RCWCLRA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLRA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLRA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -828,6 +1440,24 @@ pub mod RCWSWPA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWPA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWPA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -852,6 +1482,24 @@ pub mod RCWSETA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSETA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSETA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -876,6 +1524,18 @@ pub mod LDAPRB_32L_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPRB_32L_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAPRB_32L_memop( Rn: ::aarchmrs_types::BitValue<5>, @@ -897,6 +1557,24 @@ pub mod LDADDALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -921,6 +1599,24 @@ pub mod LDCLRALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -945,6 +1641,24 @@ pub mod LDEORALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -969,6 +1683,24 @@ pub mod LDSETALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -993,6 +1725,24 @@ pub mod LDSMAXALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1017,6 +1767,24 @@ pub mod LDSMINALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1041,6 +1809,24 @@ pub mod LDUMAXALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1065,6 +1851,24 @@ pub mod LDUMINALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1089,6 +1893,24 @@ pub mod SWPALB_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPALB_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPALB_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1113,6 +1935,24 @@ pub mod RCWCLRAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLRAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLRAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1137,6 +1977,24 @@ pub mod RCWSWPAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWPAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWPAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1161,6 +2019,24 @@ pub mod RCWSETAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSETAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSETAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1185,6 +2061,24 @@ pub mod LDADDH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1209,6 +2103,24 @@ pub mod LDCLRH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1233,6 +2145,24 @@ pub mod LDEORH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1257,6 +2187,24 @@ pub mod LDSETH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1281,6 +2229,24 @@ pub mod LDSMAXH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1305,6 +2271,24 @@ pub mod LDSMINH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1329,6 +2313,24 @@ pub mod LDUMAXH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1353,6 +2355,24 @@ pub mod LDUMINH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1377,6 +2397,24 @@ pub mod SWPH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1401,6 +2439,24 @@ pub mod RCWSCLR_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLR_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLR_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1425,6 +2481,24 @@ pub mod RCWSSWP_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWP_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWP_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1449,6 +2523,24 @@ pub mod RCWSSET_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSET_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSET_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1473,6 +2565,24 @@ pub mod LDADDLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1497,6 +2607,24 @@ pub mod LDCLRLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1521,6 +2649,24 @@ pub mod LDEORLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1545,6 +2691,24 @@ pub mod LDSETLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1569,6 +2733,24 @@ pub mod LDSMAXLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1593,6 +2775,24 @@ pub mod LDSMINLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1617,6 +2817,24 @@ pub mod LDUMAXLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1641,6 +2859,24 @@ pub mod LDUMINLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1665,6 +2901,24 @@ pub mod SWPLH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPLH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPLH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1689,6 +2943,24 @@ pub mod RCWSCLRL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLRL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLRL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1713,6 +2985,24 @@ pub mod RCWSSWPL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWPL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWPL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1737,6 +3027,24 @@ pub mod RCWSSETL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSETL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSETL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1761,6 +3069,24 @@ pub mod LDADDAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1785,6 +3111,24 @@ pub mod LDCLRAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1809,6 +3153,24 @@ pub mod LDEORAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1833,6 +3195,24 @@ pub mod LDSETAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1857,6 +3237,24 @@ pub mod LDSMAXAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1881,6 +3279,24 @@ pub mod LDSMINAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1905,6 +3321,24 @@ pub mod LDUMAXAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1929,6 +3363,24 @@ pub mod LDUMINAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1953,6 +3405,24 @@ pub mod SWPAH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPAH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPAH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -1977,6 +3447,24 @@ pub mod RCWSCLRA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLRA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLRA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2001,6 +3489,24 @@ pub mod RCWSSWPA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWPA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWPA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2025,6 +3531,24 @@ pub mod RCWSSETA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSETA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSETA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2049,6 +3573,18 @@ pub mod LDAPRH_32L_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPRH_32L_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAPRH_32L_memop( Rn: ::aarchmrs_types::BitValue<5>, @@ -2070,6 +3606,24 @@ pub mod LDADDALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2094,6 +3648,24 @@ pub mod LDCLRALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2118,6 +3690,24 @@ pub mod LDEORALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2142,6 +3732,24 @@ pub mod LDSETALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2166,6 +3774,24 @@ pub mod LDSMAXALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2190,6 +3816,24 @@ pub mod LDSMINALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2214,6 +3858,24 @@ pub mod LDUMAXALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2238,6 +3900,24 @@ pub mod LDUMINALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2262,6 +3942,24 @@ pub mod SWPALH_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPALH_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPALH_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2286,6 +3984,24 @@ pub mod RCWSCLRAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLRAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLRAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2310,6 +4026,24 @@ pub mod RCWSSWPAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWPAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWPAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2334,6 +4068,24 @@ pub mod RCWSSETAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSETAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSETAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2358,6 +4110,24 @@ pub mod LDADD_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADD_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADD_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2382,6 +4152,24 @@ pub mod LDCLR_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLR_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLR_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2406,6 +4194,24 @@ pub mod LDEOR_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEOR_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEOR_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2430,6 +4236,24 @@ pub mod LDSET_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSET_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSET_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2454,6 +4278,24 @@ pub mod LDSMAX_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAX_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAX_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2478,6 +4320,24 @@ pub mod LDSMIN_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMIN_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMIN_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2502,6 +4362,24 @@ pub mod LDUMAX_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAX_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAX_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2526,6 +4404,24 @@ pub mod LDUMIN_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMIN_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMIN_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2550,6 +4446,24 @@ pub mod SWP_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWP_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWP_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2574,6 +4488,24 @@ pub mod LDADDL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2598,6 +4530,24 @@ pub mod LDCLRL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2622,6 +4572,24 @@ pub mod LDEORL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2646,6 +4614,24 @@ pub mod LDSETL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2670,6 +4656,24 @@ pub mod LDSMAXL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2694,6 +4698,24 @@ pub mod LDSMINL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2718,6 +4740,24 @@ pub mod LDUMAXL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2742,6 +4782,24 @@ pub mod LDUMINL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2766,6 +4824,24 @@ pub mod SWPL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2790,6 +4866,24 @@ pub mod LDADDA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2814,6 +4908,24 @@ pub mod LDCLRA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2838,6 +4950,24 @@ pub mod LDEORA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2862,6 +4992,24 @@ pub mod LDSETA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2886,6 +5034,24 @@ pub mod LDSMAXA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2910,6 +5076,24 @@ pub mod LDSMINA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2934,6 +5118,24 @@ pub mod LDUMAXA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2958,6 +5160,24 @@ pub mod LDUMINA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -2982,6 +5202,24 @@ pub mod SWPA_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPA_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPA_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3006,6 +5244,18 @@ pub mod LDAPR_32L_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPR_32L_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAPR_32L_memop( Rn: ::aarchmrs_types::BitValue<5>, @@ -3027,6 +5277,24 @@ pub mod LDADDAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3051,6 +5319,24 @@ pub mod LDCLRAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3075,6 +5361,24 @@ pub mod LDEORAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3099,6 +5403,24 @@ pub mod LDSETAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3123,6 +5445,24 @@ pub mod LDSMAXAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3147,6 +5487,24 @@ pub mod LDSMINAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3171,6 +5529,24 @@ pub mod LDUMAXAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3195,6 +5571,24 @@ pub mod LDUMINAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3219,6 +5613,24 @@ pub mod SWPAL_32_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPAL_32_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPAL_32_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3243,6 +5655,24 @@ pub mod LDADD_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADD_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADD_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3267,6 +5697,24 @@ pub mod LDCLR_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLR_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLR_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3291,6 +5739,24 @@ pub mod LDEOR_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEOR_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEOR_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3315,6 +5781,24 @@ pub mod LDSET_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSET_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSET_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3339,6 +5823,24 @@ pub mod LDSMAX_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAX_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAX_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3363,6 +5865,24 @@ pub mod LDSMIN_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMIN_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMIN_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3387,6 +5907,24 @@ pub mod LDUMAX_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAX_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAX_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3411,6 +5949,24 @@ pub mod LDUMIN_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMIN_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMIN_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3435,6 +5991,24 @@ pub mod SWP_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWP_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWP_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3459,6 +6033,24 @@ pub mod ST64BV0_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST64BV0_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn ST64BV0_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3483,6 +6075,24 @@ pub mod ST64BV_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST64BV_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn ST64BV_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3507,6 +6117,18 @@ pub mod ST64B_64L_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ST64B_64L_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn ST64B_64L_memop( Rn: ::aarchmrs_types::BitValue<5>, @@ -3528,6 +6150,18 @@ pub mod LD64B_64L_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LD64B_64L_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LD64B_64L_memop( Rn: ::aarchmrs_types::BitValue<5>, @@ -3549,6 +6183,24 @@ pub mod LDADDL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3573,6 +6225,24 @@ pub mod LDCLRL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3597,6 +6267,24 @@ pub mod LDEORL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3621,6 +6309,24 @@ pub mod LDSETL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3645,6 +6351,24 @@ pub mod LDSMAXL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3669,6 +6393,24 @@ pub mod LDSMINL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3693,6 +6435,24 @@ pub mod LDUMAXL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3717,6 +6477,24 @@ pub mod LDUMINL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3741,6 +6519,24 @@ pub mod SWPL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3765,6 +6561,24 @@ pub mod LDADDA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3789,6 +6603,24 @@ pub mod LDCLRA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3813,6 +6645,24 @@ pub mod LDEORA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3837,6 +6687,24 @@ pub mod LDSETA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3861,6 +6729,24 @@ pub mod LDSMAXA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3885,6 +6771,24 @@ pub mod LDSMINA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3909,6 +6813,24 @@ pub mod LDUMAXA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3933,6 +6855,24 @@ pub mod LDUMINA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3957,6 +6897,24 @@ pub mod SWPA_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPA_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPA_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -3981,6 +6939,18 @@ pub mod LDAPR_64L_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAPR_64L_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn LDAPR_64L_memop( Rn: ::aarchmrs_types::BitValue<5>, @@ -4002,6 +6972,24 @@ pub mod LDADDAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDADDAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDADDAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4026,6 +7014,24 @@ pub mod LDCLRAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4050,6 +7056,24 @@ pub mod LDEORAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDEORAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDEORAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4074,6 +7098,24 @@ pub mod LDSETAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4098,6 +7140,24 @@ pub mod LDSMAXAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMAXAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMAXAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4122,6 +7182,24 @@ pub mod LDSMINAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSMINAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDSMINAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4146,6 +7224,24 @@ pub mod LDUMAXAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMAXAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMAXAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4170,6 +7266,24 @@ pub mod LDUMINAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDUMINAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDUMINAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4194,6 +7308,24 @@ pub mod SWPAL_64_memop { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPAL_64_memop"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPAL_64_memop( Rs: ::aarchmrs_types::BitValue<5>, @@ -4218,6 +7350,24 @@ pub mod LDBFADD_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFADD_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFADD_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4242,6 +7392,24 @@ pub mod LDBFMAX_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAX_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAX_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4266,6 +7434,24 @@ pub mod LDBFMIN_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMIN_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMIN_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4290,6 +7476,24 @@ pub mod LDBFMAXNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAXNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAXNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4314,6 +7518,24 @@ pub mod LDBFMINNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMINNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMINNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4338,6 +7560,18 @@ pub mod STBFADD_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFADD_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFADD_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4361,6 +7595,18 @@ pub mod STBFMAX_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMAX_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMAX_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4384,6 +7630,18 @@ pub mod STBFMIN_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMIN_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMIN_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4407,6 +7665,18 @@ pub mod STBFMAXNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMAXNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMAXNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4430,6 +7700,18 @@ pub mod STBFMINNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMINNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMINNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4453,6 +7735,18 @@ pub mod STBFADDL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFADDL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFADDL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4476,6 +7770,18 @@ pub mod STBFMAXL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMAXL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMAXL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4499,6 +7805,18 @@ pub mod STBFMINL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMINL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMINL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4522,6 +7840,18 @@ pub mod STBFMAXNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMAXNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMAXNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4545,6 +7875,18 @@ pub mod STBFMINNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STBFMINNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STBFMINNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4568,6 +7910,24 @@ pub mod LDBFADDL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFADDL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFADDL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4592,6 +7952,24 @@ pub mod LDBFMAXL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAXL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAXL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4616,6 +7994,24 @@ pub mod LDBFMINL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMINL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMINL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4640,6 +8036,24 @@ pub mod LDBFMAXNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAXNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAXNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4664,6 +8078,24 @@ pub mod LDBFMINNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMINNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMINNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4688,6 +8120,24 @@ pub mod LDBFADDA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFADDA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFADDA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4712,6 +8162,24 @@ pub mod LDBFMAXA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAXA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAXA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4736,6 +8204,24 @@ pub mod LDBFMINA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMINA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMINA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4760,6 +8246,24 @@ pub mod LDBFMAXNMA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAXNMA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAXNMA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4784,6 +8288,24 @@ pub mod LDBFMINNMA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMINNMA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMINNMA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4808,6 +8330,24 @@ pub mod LDBFADDAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFADDAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFADDAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4832,6 +8372,24 @@ pub mod LDBFMAXAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAXAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAXAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4856,6 +8414,24 @@ pub mod LDBFMINAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMINAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMINAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4880,6 +8456,24 @@ pub mod LDBFMAXNMAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMAXNMAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMAXNMAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4904,6 +8498,24 @@ pub mod LDBFMINNMAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDBFMINNMAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDBFMINNMAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4928,6 +8540,24 @@ pub mod LDFADD_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADD_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADD_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4952,6 +8582,24 @@ pub mod LDFMAX_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAX_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAX_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -4976,6 +8624,24 @@ pub mod LDFMIN_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMIN_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMIN_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5000,6 +8666,24 @@ pub mod LDFMAXNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5024,6 +8708,24 @@ pub mod LDFMINNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5048,6 +8750,18 @@ pub mod STFADD_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFADD_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFADD_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5071,6 +8785,18 @@ pub mod STFMAX_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAX_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAX_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5094,6 +8820,18 @@ pub mod STFMIN_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMIN_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMIN_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5117,6 +8855,18 @@ pub mod STFMAXNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5140,6 +8890,18 @@ pub mod STFMINNM_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINNM_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINNM_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5163,6 +8925,18 @@ pub mod STFADDL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFADDL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFADDL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5186,6 +8960,18 @@ pub mod STFMAXL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5209,6 +8995,18 @@ pub mod STFMINL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5232,6 +9030,18 @@ pub mod STFMAXNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5255,6 +9065,18 @@ pub mod STFMINNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5278,6 +9100,24 @@ pub mod LDFADDL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5302,6 +9142,24 @@ pub mod LDFMAXL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5326,6 +9184,24 @@ pub mod LDFMINL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5350,6 +9226,24 @@ pub mod LDFMAXNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5374,6 +9268,24 @@ pub mod LDFMINNML_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNML_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNML_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5398,6 +9310,24 @@ pub mod LDFADDA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5422,6 +9352,24 @@ pub mod LDFMAXA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5446,6 +9394,24 @@ pub mod LDFMINA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5470,6 +9436,24 @@ pub mod LDFMAXNMA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNMA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNMA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5494,6 +9478,24 @@ pub mod LDFMINNMA_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNMA_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNMA_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5518,6 +9520,24 @@ pub mod LDFADDAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5542,6 +9562,24 @@ pub mod LDFMAXAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5566,6 +9604,24 @@ pub mod LDFMINAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5590,6 +9646,24 @@ pub mod LDFMAXNMAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNMAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNMAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5614,6 +9688,24 @@ pub mod LDFMINNMAL_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNMAL_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNMAL_16( Rs: ::aarchmrs_types::BitValue<5>, @@ -5638,6 +9730,24 @@ pub mod LDFADD_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADD_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADD_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5662,6 +9772,24 @@ pub mod LDFMAX_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAX_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAX_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5686,6 +9814,24 @@ pub mod LDFMIN_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMIN_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMIN_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5710,6 +9856,24 @@ pub mod LDFMAXNM_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNM_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNM_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5734,6 +9898,24 @@ pub mod LDFMINNM_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNM_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNM_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5758,6 +9940,18 @@ pub mod STFADD_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFADD_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFADD_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5781,6 +9975,18 @@ pub mod STFMAX_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAX_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAX_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5804,6 +10010,18 @@ pub mod STFMIN_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMIN_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMIN_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5827,6 +10045,18 @@ pub mod STFMAXNM_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXNM_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXNM_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5850,6 +10080,18 @@ pub mod STFMINNM_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINNM_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINNM_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5873,6 +10115,18 @@ pub mod STFADDL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFADDL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFADDL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5896,6 +10150,18 @@ pub mod STFMAXL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5919,6 +10185,18 @@ pub mod STFMINL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5942,6 +10220,18 @@ pub mod STFMAXNML_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXNML_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXNML_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5965,6 +10255,18 @@ pub mod STFMINNML_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINNML_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINNML_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -5988,6 +10290,24 @@ pub mod LDFADDL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6012,6 +10332,24 @@ pub mod LDFMAXL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6036,6 +10374,24 @@ pub mod LDFMINL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6060,6 +10416,24 @@ pub mod LDFMAXNML_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNML_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNML_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6084,6 +10458,24 @@ pub mod LDFMINNML_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNML_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNML_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6108,6 +10500,24 @@ pub mod LDFADDA_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDA_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDA_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6132,6 +10542,24 @@ pub mod LDFMAXA_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXA_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXA_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6156,6 +10584,24 @@ pub mod LDFMINA_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINA_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINA_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6180,6 +10626,24 @@ pub mod LDFMAXNMA_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNMA_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNMA_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6204,6 +10668,24 @@ pub mod LDFMINNMA_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNMA_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNMA_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6228,6 +10710,24 @@ pub mod LDFADDAL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDAL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDAL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6252,6 +10752,24 @@ pub mod LDFMAXAL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXAL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXAL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6276,6 +10794,24 @@ pub mod LDFMINAL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINAL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINAL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6300,6 +10836,24 @@ pub mod LDFMAXNMAL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNMAL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNMAL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6324,6 +10878,24 @@ pub mod LDFMINNMAL_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNMAL_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNMAL_32( Rs: ::aarchmrs_types::BitValue<5>, @@ -6348,6 +10920,24 @@ pub mod LDFADD_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADD_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADD_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6372,6 +10962,24 @@ pub mod LDFMAX_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAX_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAX_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6396,6 +11004,24 @@ pub mod LDFMIN_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMIN_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMIN_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6420,6 +11046,24 @@ pub mod LDFMAXNM_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNM_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNM_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6444,6 +11088,24 @@ pub mod LDFMINNM_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNM_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNM_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6468,6 +11130,18 @@ pub mod STFADD_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFADD_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFADD_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6491,6 +11165,18 @@ pub mod STFMAX_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAX_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAX_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6514,6 +11200,18 @@ pub mod STFMIN_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMIN_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMIN_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6537,6 +11235,18 @@ pub mod STFMAXNM_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXNM_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXNM_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6560,6 +11270,18 @@ pub mod STFMINNM_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINNM_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINNM_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6583,6 +11305,18 @@ pub mod STFADDL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFADDL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFADDL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6606,6 +11340,18 @@ pub mod STFMAXL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6629,6 +11375,18 @@ pub mod STFMINL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6652,6 +11410,18 @@ pub mod STFMAXNML_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMAXNML_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMAXNML_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6675,6 +11445,18 @@ pub mod STFMINNML_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STFMINNML_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn STFMINNML_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6698,6 +11480,24 @@ pub mod LDFADDL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6722,6 +11522,24 @@ pub mod LDFMAXL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6746,6 +11564,24 @@ pub mod LDFMINL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6770,6 +11606,24 @@ pub mod LDFMAXNML_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNML_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNML_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6794,6 +11648,24 @@ pub mod LDFMINNML_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNML_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNML_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6818,6 +11690,24 @@ pub mod LDFADDA_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDA_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDA_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6842,6 +11732,24 @@ pub mod LDFMAXA_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXA_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXA_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6866,6 +11774,24 @@ pub mod LDFMINA_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINA_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINA_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6890,6 +11816,24 @@ pub mod LDFMAXNMA_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNMA_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNMA_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6914,6 +11858,24 @@ pub mod LDFMINNMA_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNMA_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNMA_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6938,6 +11900,24 @@ pub mod LDFADDAL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFADDAL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFADDAL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6962,6 +11942,24 @@ pub mod LDFMAXAL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXAL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXAL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -6986,6 +11984,24 @@ pub mod LDFMINAL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINAL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINAL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -7010,6 +12026,24 @@ pub mod LDFMAXNMAL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMAXNMAL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMAXNMAL_64( Rs: ::aarchmrs_types::BitValue<5>, @@ -7034,6 +12068,24 @@ pub mod LDFMINNMAL_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDFMINNMAL_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDFMINNMAL_64( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/memop_128.rs b/aarchmrs-instructions/src/A64/ldst/memop_128.rs index f0450bee..1b491a45 100644 --- a/aarchmrs-instructions/src/A64/ldst/memop_128.rs +++ b/aarchmrs-instructions/src/A64/ldst/memop_128.rs @@ -12,6 +12,24 @@ pub mod LDCLRP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod LDSETP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod SWPP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn SWPP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod RCWCLRP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLRP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLRP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod RCWSWPP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWPP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWPP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod RCWSETP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSETP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSETP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod LDCLRPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod LDSETPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod SWPPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn SWPPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod RCWCLRPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLRPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLRPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod RCWSWPPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWPPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWPPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod RCWSETPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSETPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSETPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -300,6 +516,24 @@ pub mod LDCLRPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -324,6 +558,24 @@ pub mod LDSETPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -348,6 +600,24 @@ pub mod SWPPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn SWPPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -372,6 +642,24 @@ pub mod RCWCLRPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLRPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLRPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -396,6 +684,24 @@ pub mod RCWSWPPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWPPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWPPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -420,6 +726,24 @@ pub mod RCWSETPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSETPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSETPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -444,6 +768,24 @@ pub mod LDCLRPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDCLRPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDCLRPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -468,6 +810,24 @@ pub mod LDSETPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDSETPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn LDSETPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -492,6 +852,24 @@ pub mod SWPPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn SWPPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -516,6 +894,24 @@ pub mod RCWCLRPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCLRPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCLRPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -540,6 +936,24 @@ pub mod RCWSWPPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSWPPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSWPPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -564,6 +978,24 @@ pub mod RCWSETPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSETPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSETPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -588,6 +1020,24 @@ pub mod RCWSCLRP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLRP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLRP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -612,6 +1062,24 @@ pub mod RCWSSWPP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWPP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWPP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -636,6 +1104,24 @@ pub mod RCWSSETP_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSETP_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSETP_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -660,6 +1146,24 @@ pub mod RCWSCLRPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLRPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLRPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -684,6 +1188,24 @@ pub mod RCWSSWPPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWPPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWPPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -708,6 +1230,24 @@ pub mod RCWSSETPL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSETPL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSETPL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -732,6 +1272,24 @@ pub mod RCWSCLRPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLRPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLRPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -756,6 +1314,24 @@ pub mod RCWSSWPPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWPPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWPPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -780,6 +1356,24 @@ pub mod RCWSSETPA_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSETPA_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSETPA_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -804,6 +1398,24 @@ pub mod RCWSCLRPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCLRPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCLRPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -828,6 +1440,24 @@ pub mod RCWSSWPPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSWPPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSWPPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, @@ -852,6 +1482,24 @@ pub mod RCWSSETPAL_128_memop_128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSSETPAL_128_memop_128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSSETPAL_128_memop_128( Rt2: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/memop_unpriv.rs b/aarchmrs-instructions/src/A64/ldst/memop_unpriv.rs index b4921a38..550b33cb 100644 --- a/aarchmrs-instructions/src/A64/ldst/memop_unpriv.rs +++ b/aarchmrs-instructions/src/A64/ldst/memop_unpriv.rs @@ -12,6 +12,24 @@ pub mod LDTADD_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADD_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADD_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod LDTCLR_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLR_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLR_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod LDTSET_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSET_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSET_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod SWPT_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPT_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPT_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod LDTADDL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADDL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADDL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod LDTCLRL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLRL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLRL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod LDTSETL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSETL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSETL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod SWPTL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPTL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPTL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod LDTADDA_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADDA_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADDA_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod LDTCLRA_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLRA_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLRA_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod LDTSETA_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSETA_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSETA_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod SWPTA_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPTA_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPTA_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -300,6 +516,24 @@ pub mod LDTADDAL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADDAL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADDAL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -324,6 +558,24 @@ pub mod LDTCLRAL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLRAL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLRAL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -348,6 +600,24 @@ pub mod LDTSETAL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSETAL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSETAL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -372,6 +642,24 @@ pub mod SWPTAL_32_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPTAL_32_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPTAL_32_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -396,6 +684,24 @@ pub mod LDTADD_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADD_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADD_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -420,6 +726,24 @@ pub mod LDTCLR_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLR_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLR_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -444,6 +768,24 @@ pub mod LDTSET_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSET_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSET_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -468,6 +810,24 @@ pub mod SWPT_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPT_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPT_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -492,6 +852,24 @@ pub mod LDTADDL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADDL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADDL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -516,6 +894,24 @@ pub mod LDTCLRL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLRL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLRL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -540,6 +936,24 @@ pub mod LDTSETL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSETL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSETL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -564,6 +978,24 @@ pub mod SWPTL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPTL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPTL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -588,6 +1020,24 @@ pub mod LDTADDA_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADDA_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADDA_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -612,6 +1062,24 @@ pub mod LDTCLRA_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLRA_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLRA_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -636,6 +1104,24 @@ pub mod LDTSETA_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSETA_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSETA_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -660,6 +1146,24 @@ pub mod SWPTA_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPTA_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPTA_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -684,6 +1188,24 @@ pub mod LDTADDAL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTADDAL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTADDAL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -708,6 +1230,24 @@ pub mod LDTCLRAL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTCLRAL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTCLRAL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -732,6 +1272,24 @@ pub mod LDTSETAL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDTSETAL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn LDTSETAL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, @@ -756,6 +1314,24 @@ pub mod SWPTAL_64_memop_unpriv { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SWPTAL_64_memop_unpriv"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn SWPTAL_64_memop_unpriv( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/memset_go.rs b/aarchmrs-instructions/src/A64/ldst/memset_go.rs index a7661618..ed4996e0 100644 --- a/aarchmrs-instructions/src/A64/ldst/memset_go.rs +++ b/aarchmrs-instructions/src/A64/ldst/memset_go.rs @@ -12,6 +12,24 @@ pub mod SETGOP_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOP_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOP_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -35,6 +53,24 @@ pub mod SETGOPT_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOPT_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOPT_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -58,6 +94,24 @@ pub mod SETGOPN_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOPN_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOPN_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -81,6 +135,24 @@ pub mod SETGOPTN_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOPTN_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOPTN_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -104,6 +176,24 @@ pub mod SETGOM_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOM_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOM_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -127,6 +217,24 @@ pub mod SETGOMT_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOMT_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOMT_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -150,6 +258,24 @@ pub mod SETGOMN_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOMN_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOMN_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -173,6 +299,24 @@ pub mod SETGOMTN_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOMTN_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOMTN_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -196,6 +340,24 @@ pub mod SETGOE_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOE_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOE_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -219,6 +381,24 @@ pub mod SETGOET_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOET_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOET_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -242,6 +422,24 @@ pub mod SETGOEN_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOEN_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOEN_memset_go( sz: ::aarchmrs_types::BitValue<2>, @@ -265,6 +463,24 @@ pub mod SETGOETN_memset_go { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETGOETN_memset_go"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 2u32; #[inline] pub const fn SETGOETN_memset_go( sz: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/ldst/rcwcomswap.rs b/aarchmrs-instructions/src/A64/ldst/rcwcomswap.rs index 0fb720dd..0c6bd598 100644 --- a/aarchmrs-instructions/src/A64/ldst/rcwcomswap.rs +++ b/aarchmrs-instructions/src/A64/ldst/rcwcomswap.rs @@ -12,6 +12,24 @@ pub mod RCWCAS_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCAS_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCAS_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod RCWCASL_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCASL_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCASL_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod RCWCASA_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCASA_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCASA_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod RCWCASAL_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCASAL_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCASAL_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod RCWSCAS_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCAS_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCAS_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod RCWSCASL_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCASL_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCASL_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod RCWSCASA_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCASA_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCASA_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod RCWSCASAL_C64_rcwcomswap { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCASAL_C64_rcwcomswap"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCASAL_C64_rcwcomswap( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/ldst/rcwcomswappr.rs b/aarchmrs-instructions/src/A64/ldst/rcwcomswappr.rs index 627e82b7..b59ca066 100644 --- a/aarchmrs-instructions/src/A64/ldst/rcwcomswappr.rs +++ b/aarchmrs-instructions/src/A64/ldst/rcwcomswappr.rs @@ -12,6 +12,24 @@ pub mod RCWCASP_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCASP_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCASP_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod RCWCASPL_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCASPL_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCASPL_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod RCWCASPA_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCASPA_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCASPA_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod RCWCASPAL_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWCASPAL_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWCASPAL_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod RCWSCASP_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCASP_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCASP_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod RCWSCASPL_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCASPL_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCASPL_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod RCWSCASPA_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCASPA_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCASPA_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod RCWSCASPAL_C64_rcwcomswappr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RCWSCASPAL_C64_rcwcomswappr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 5u32; #[inline] pub const fn RCWSCASPAL_C64_rcwcomswappr( Rs: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/reserved/perm_undef.rs b/aarchmrs-instructions/src/A64/reserved/perm_undef.rs index 488b176c..91d05369 100644 --- a/aarchmrs-instructions/src/A64/reserved/perm_undef.rs +++ b/aarchmrs-instructions/src/A64/reserved/perm_undef.rs @@ -12,6 +12,12 @@ pub mod UDF_only_perm_undef { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDF_only_perm_undef"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm16_WIDTH: u32 = 16u32; #[inline] pub const fn UDF_only_perm_undef( imm16: ::aarchmrs_types::BitValue<16>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdall.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdall.rs index 64c34910..95ae32ea 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdall.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdall.rs @@ -12,6 +12,30 @@ pub mod SADDLV_asimdall_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADDLV_asimdall_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SADDLV_asimdall_only( Q: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod SMAXV_asimdall_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMAXV_asimdall_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMAXV_asimdall_only( Q: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod SMINV_asimdall_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMINV_asimdall_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMINV_asimdall_only( Q: ::aarchmrs_types::BitValue<1>, @@ -93,6 +165,30 @@ pub mod ADDV_asimdall_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDV_asimdall_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ADDV_asimdall_only( Q: ::aarchmrs_types::BitValue<1>, @@ -120,6 +216,24 @@ pub mod FMAXNMV_asimdall_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNMV_asimdall_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXNMV_asimdall_only_H( Q: ::aarchmrs_types::BitValue<1>, @@ -144,6 +258,24 @@ pub mod FMAXV_asimdall_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXV_asimdall_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXV_asimdall_only_H( Q: ::aarchmrs_types::BitValue<1>, @@ -168,6 +300,24 @@ pub mod FMINNMV_asimdall_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNMV_asimdall_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINNMV_asimdall_only_H( Q: ::aarchmrs_types::BitValue<1>, @@ -192,6 +342,24 @@ pub mod FMINV_asimdall_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINV_asimdall_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINV_asimdall_only_H( Q: ::aarchmrs_types::BitValue<1>, @@ -216,6 +384,30 @@ pub mod UADDLV_asimdall_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADDLV_asimdall_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UADDLV_asimdall_only( Q: ::aarchmrs_types::BitValue<1>, @@ -243,6 +435,30 @@ pub mod UMAXV_asimdall_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAXV_asimdall_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMAXV_asimdall_only( Q: ::aarchmrs_types::BitValue<1>, @@ -270,6 +486,30 @@ pub mod UMINV_asimdall_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMINV_asimdall_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMINV_asimdall_only( Q: ::aarchmrs_types::BitValue<1>, @@ -297,6 +537,18 @@ pub mod FMAXNMV_asimdall_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNMV_asimdall_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMAXNMV_asimdall_only_SD( Rn: ::aarchmrs_types::BitValue<5>, @@ -318,6 +570,18 @@ pub mod FMAXV_asimdall_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXV_asimdall_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMAXV_asimdall_only_SD( Rn: ::aarchmrs_types::BitValue<5>, @@ -339,6 +603,18 @@ pub mod FMINNMV_asimdall_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNMV_asimdall_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMINNMV_asimdall_only_SD( Rn: ::aarchmrs_types::BitValue<5>, @@ -360,6 +636,18 @@ pub mod FMINV_asimdall_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINV_asimdall_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMINV_asimdall_only_SD( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimddiff.rs b/aarchmrs-instructions/src/A64/simd_dp/asimddiff.rs index ade3b9b5..ed4d5fdd 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimddiff.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimddiff.rs @@ -12,6 +12,36 @@ pub mod SADDL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADDL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SADDL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,36 @@ pub mod SADDW_asimddiff_W { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADDW_asimddiff_W"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SADDW_asimddiff_W( Q: ::aarchmrs_types::BitValue<1>, @@ -72,6 +132,36 @@ pub mod SSUBL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSUBL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SSUBL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -102,6 +192,36 @@ pub mod SSUBW_asimddiff_W { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSUBW_asimddiff_W"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SSUBW_asimddiff_W( Q: ::aarchmrs_types::BitValue<1>, @@ -132,6 +252,36 @@ pub mod ADDHN_asimddiff_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDHN_asimddiff_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ADDHN_asimddiff_N( Q: ::aarchmrs_types::BitValue<1>, @@ -162,6 +312,36 @@ pub mod SABAL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SABAL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SABAL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -192,6 +372,36 @@ pub mod SUBHN_asimddiff_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBHN_asimddiff_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SUBHN_asimddiff_N( Q: ::aarchmrs_types::BitValue<1>, @@ -222,6 +432,36 @@ pub mod SABDL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SABDL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SABDL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -252,6 +492,36 @@ pub mod SMLAL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMLAL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -282,6 +552,36 @@ pub mod SQDMLAL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLAL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMLAL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -312,6 +612,36 @@ pub mod SMLSL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMLSL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -342,6 +672,36 @@ pub mod SQDMLSL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLSL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMLSL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -372,6 +732,36 @@ pub mod SMULL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMULL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -402,6 +792,36 @@ pub mod SQDMULL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMULL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -432,6 +852,36 @@ pub mod PMULL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PMULL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn PMULL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -462,6 +912,36 @@ pub mod UADDL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADDL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UADDL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -492,6 +972,36 @@ pub mod UADDW_asimddiff_W { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADDW_asimddiff_W"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UADDW_asimddiff_W( Q: ::aarchmrs_types::BitValue<1>, @@ -522,6 +1032,36 @@ pub mod USUBL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USUBL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USUBL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -552,6 +1092,36 @@ pub mod USUBW_asimddiff_W { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USUBW_asimddiff_W"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USUBW_asimddiff_W( Q: ::aarchmrs_types::BitValue<1>, @@ -582,6 +1152,36 @@ pub mod RADDHN_asimddiff_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RADDHN_asimddiff_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn RADDHN_asimddiff_N( Q: ::aarchmrs_types::BitValue<1>, @@ -612,6 +1212,36 @@ pub mod UABAL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UABAL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UABAL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -642,6 +1272,36 @@ pub mod RSUBHN_asimddiff_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSUBHN_asimddiff_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn RSUBHN_asimddiff_N( Q: ::aarchmrs_types::BitValue<1>, @@ -672,6 +1332,36 @@ pub mod UABDL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UABDL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UABDL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -702,6 +1392,36 @@ pub mod UMLAL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMLAL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMLAL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -732,6 +1452,36 @@ pub mod UMLSL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMLSL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMLSL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, @@ -762,6 +1512,36 @@ pub mod UMULL_asimddiff_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMULL_asimddiff_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMULL_asimddiff_L( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdelem.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdelem.rs index abab0be4..6f6c6250 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdelem.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdelem.rs @@ -12,6 +12,54 @@ pub mod SMLAL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMLAL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -48,6 +96,54 @@ pub mod SQDMLAL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLAL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMLAL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -84,6 +180,54 @@ pub mod SMLSL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMLSL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -120,6 +264,54 @@ pub mod SQDMLSL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLSL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMLSL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -156,6 +348,54 @@ pub mod MUL_asimdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MUL_asimdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MUL_asimdelem_R( Q: ::aarchmrs_types::BitValue<1>, @@ -192,6 +432,54 @@ pub mod SMULL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMULL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -228,6 +516,54 @@ pub mod SQDMULL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMULL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -264,6 +600,54 @@ pub mod SQDMULH_asimdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULH_asimdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMULH_asimdelem_R( Q: ::aarchmrs_types::BitValue<1>, @@ -300,6 +684,54 @@ pub mod SQRDMULH_asimdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMULH_asimdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRDMULH_asimdelem_R( Q: ::aarchmrs_types::BitValue<1>, @@ -336,6 +768,54 @@ pub mod SDOT_asimdelem_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SDOT_asimdelem_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SDOT_asimdelem_D( Q: ::aarchmrs_types::BitValue<1>, @@ -372,6 +852,48 @@ pub mod FDOT_asimdelem_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDOT_asimdelem_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDOT_asimdelem_D( Q: ::aarchmrs_types::BitValue<1>, @@ -406,6 +928,48 @@ pub mod FMLA_asimdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLA_asimdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLA_asimdelem_RH_H( Q: ::aarchmrs_types::BitValue<1>, @@ -440,6 +1004,48 @@ pub mod FMLS_asimdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLS_asimdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLS_asimdelem_RH_H( Q: ::aarchmrs_types::BitValue<1>, @@ -474,6 +1080,48 @@ pub mod FMUL_asimdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_asimdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMUL_asimdelem_RH_H( Q: ::aarchmrs_types::BitValue<1>, @@ -508,6 +1156,48 @@ pub mod SUDOT_asimdelem_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUDOT_asimdelem_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SUDOT_asimdelem_D( Q: ::aarchmrs_types::BitValue<1>, @@ -542,6 +1232,48 @@ pub mod FDOT_asimdelem_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDOT_asimdelem_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDOT_asimdelem_G( Q: ::aarchmrs_types::BitValue<1>, @@ -576,6 +1308,48 @@ pub mod FDOT_asimdelem_FP16FP32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDOT_asimdelem_FP16FP32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDOT_asimdelem_FP16FP32( Q: ::aarchmrs_types::BitValue<1>, @@ -610,6 +1384,48 @@ pub mod BFDOT_asimdelem_E { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFDOT_asimdelem_E"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BFDOT_asimdelem_E( Q: ::aarchmrs_types::BitValue<1>, @@ -644,6 +1460,54 @@ pub mod FMLA_asimdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLA_asimdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLA_asimdelem_R_SD( Q: ::aarchmrs_types::BitValue<1>, @@ -680,6 +1544,54 @@ pub mod FMLS_asimdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLS_asimdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLS_asimdelem_R_SD( Q: ::aarchmrs_types::BitValue<1>, @@ -716,6 +1628,54 @@ pub mod FMUL_asimdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_asimdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMUL_asimdelem_R_SD( Q: ::aarchmrs_types::BitValue<1>, @@ -752,6 +1712,48 @@ pub mod FMLAL_asimdelem_LH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLAL_asimdelem_LH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLAL_asimdelem_LH( Q: ::aarchmrs_types::BitValue<1>, @@ -786,6 +1788,48 @@ pub mod FMLSL_asimdelem_LH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLSL_asimdelem_LH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLSL_asimdelem_LH( Q: ::aarchmrs_types::BitValue<1>, @@ -820,6 +1864,48 @@ pub mod USDOT_asimdelem_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USDOT_asimdelem_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USDOT_asimdelem_D( Q: ::aarchmrs_types::BitValue<1>, @@ -854,6 +1940,48 @@ pub mod BFMLAL_asimdelem_F { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFMLAL_asimdelem_F"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BFMLAL_asimdelem_F( Q: ::aarchmrs_types::BitValue<1>, @@ -888,6 +2016,54 @@ pub mod MLA_asimdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLA_asimdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MLA_asimdelem_R( Q: ::aarchmrs_types::BitValue<1>, @@ -924,6 +2100,54 @@ pub mod UMLAL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMLAL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMLAL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -960,6 +2184,54 @@ pub mod MLS_asimdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLS_asimdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MLS_asimdelem_R( Q: ::aarchmrs_types::BitValue<1>, @@ -996,6 +2268,54 @@ pub mod UMLSL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMLSL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMLSL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -1032,6 +2352,54 @@ pub mod UMULL_asimdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMULL_asimdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMULL_asimdelem_L( Q: ::aarchmrs_types::BitValue<1>, @@ -1068,6 +2436,54 @@ pub mod SQRDMLAH_asimdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLAH_asimdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRDMLAH_asimdelem_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1104,6 +2520,54 @@ pub mod UDOT_asimdelem_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDOT_asimdelem_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UDOT_asimdelem_D( Q: ::aarchmrs_types::BitValue<1>, @@ -1140,6 +2604,54 @@ pub mod SQRDMLSH_asimdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLSH_asimdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRDMLSH_asimdelem_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1176,6 +2688,48 @@ pub mod FMULX_asimdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asimdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMULX_asimdelem_RH_H( Q: ::aarchmrs_types::BitValue<1>, @@ -1210,6 +2764,60 @@ pub mod FCMLA_advsimd_elt { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLA_advsimd_elt"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLA_advsimd_elt( Q: ::aarchmrs_types::BitValue<1>, @@ -1249,6 +2857,54 @@ pub mod FMULX_asimdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asimdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMULX_asimdelem_R_SD( Q: ::aarchmrs_types::BitValue<1>, @@ -1285,6 +2941,48 @@ pub mod FMLAL2_asimdelem_LH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLAL2_asimdelem_LH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLAL2_asimdelem_LH( Q: ::aarchmrs_types::BitValue<1>, @@ -1319,6 +3017,48 @@ pub mod FMLSL2_asimdelem_LH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLSL2_asimdelem_LH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLSL2_asimdelem_LH( Q: ::aarchmrs_types::BitValue<1>, @@ -1353,6 +3093,42 @@ pub mod FMLALB_asimdelem_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALB_asimdelem_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLALB_asimdelem_H( L: ::aarchmrs_types::BitValue<1>, @@ -1384,6 +3160,42 @@ pub mod FMLALLBB_asimdelem_J { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLBB_asimdelem_J"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLALLBB_asimdelem_J( L: ::aarchmrs_types::BitValue<1>, @@ -1415,6 +3227,42 @@ pub mod FMLALLBT_asimdelem_J { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLBT_asimdelem_J"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLALLBT_asimdelem_J( L: ::aarchmrs_types::BitValue<1>, @@ -1446,6 +3294,42 @@ pub mod FMLALT_asimdelem_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALT_asimdelem_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLALT_asimdelem_H( L: ::aarchmrs_types::BitValue<1>, @@ -1477,6 +3361,42 @@ pub mod FMLALLTB_asimdelem_J { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLTB_asimdelem_J"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLALLTB_asimdelem_J( L: ::aarchmrs_types::BitValue<1>, @@ -1508,6 +3428,42 @@ pub mod FMLALLTT_asimdelem_J { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLTT_asimdelem_J"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLALLTT_asimdelem_J( L: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdext.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdext.rs index 76d7a3b5..481284a4 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdext.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdext.rs @@ -12,6 +12,36 @@ pub mod EXT_asimdext_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EXT_asimdext_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn EXT_asimdext_only( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdimm.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdimm.rs index 850ab45e..edd4c928 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdimm.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdimm.rs @@ -12,6 +12,72 @@ pub mod MOVI_asimdimm_L_sl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVI_asimdimm_L_sl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MOVI_asimdimm_L_sl( Q: ::aarchmrs_types::BitValue<1>, @@ -54,6 +120,72 @@ pub mod ORR_asimdimm_L_sl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_asimdimm_L_sl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ORR_asimdimm_L_sl( Q: ::aarchmrs_types::BitValue<1>, @@ -96,6 +228,72 @@ pub mod MOVI_asimdimm_L_hl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVI_asimdimm_L_hl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MOVI_asimdimm_L_hl( Q: ::aarchmrs_types::BitValue<1>, @@ -138,6 +336,72 @@ pub mod ORR_asimdimm_L_hl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_asimdimm_L_hl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ORR_asimdimm_L_hl( Q: ::aarchmrs_types::BitValue<1>, @@ -180,6 +444,72 @@ pub mod MOVI_asimdimm_M_sm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVI_asimdimm_M_sm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MOVI_asimdimm_M_sm( Q: ::aarchmrs_types::BitValue<1>, @@ -222,6 +552,66 @@ pub mod MOVI_asimdimm_N_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVI_asimdimm_N_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MOVI_asimdimm_N_b( Q: ::aarchmrs_types::BitValue<1>, @@ -261,6 +651,66 @@ pub mod FMOV_asimdimm_S_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_asimdimm_S_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMOV_asimdimm_S_s( Q: ::aarchmrs_types::BitValue<1>, @@ -300,6 +750,66 @@ pub mod FMOV_asimdimm_H_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_asimdimm_H_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMOV_asimdimm_H_h( Q: ::aarchmrs_types::BitValue<1>, @@ -339,6 +849,72 @@ pub mod MVNI_asimdimm_L_sl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNI_asimdimm_L_sl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MVNI_asimdimm_L_sl( Q: ::aarchmrs_types::BitValue<1>, @@ -381,6 +957,72 @@ pub mod BIC_asimdimm_L_sl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_asimdimm_L_sl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BIC_asimdimm_L_sl( Q: ::aarchmrs_types::BitValue<1>, @@ -423,6 +1065,72 @@ pub mod MVNI_asimdimm_L_hl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNI_asimdimm_L_hl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MVNI_asimdimm_L_hl( Q: ::aarchmrs_types::BitValue<1>, @@ -465,6 +1173,72 @@ pub mod BIC_asimdimm_L_hl { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_asimdimm_L_hl"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BIC_asimdimm_L_hl( Q: ::aarchmrs_types::BitValue<1>, @@ -507,6 +1281,72 @@ pub mod MVNI_asimdimm_M_sm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNI_asimdimm_M_sm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MVNI_asimdimm_M_sm( Q: ::aarchmrs_types::BitValue<1>, @@ -549,6 +1389,60 @@ pub mod MOVI_asimdimm_D_ds { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVI_asimdimm_D_ds"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; #[inline] pub const fn MOVI_asimdimm_D_ds( a: ::aarchmrs_types::BitValue<1>, @@ -585,6 +1479,60 @@ pub mod MOVI_asimdimm_D2_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVI_asimdimm_D2_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; #[inline] pub const fn MOVI_asimdimm_D2_d( a: ::aarchmrs_types::BitValue<1>, @@ -621,6 +1569,60 @@ pub mod FMOV_asimdimm_D2_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_asimdimm_D2_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_g_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_f_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_e_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_d_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_c_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_b_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; #[inline] pub const fn FMOV_asimdimm_D2_d( a: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdins.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdins.rs index 5086abd1..a41a9227 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdins.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdins.rs @@ -12,6 +12,30 @@ pub mod DUP_asimdins_DV_v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DUP_asimdins_DV_v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn DUP_asimdins_DV_v( Q: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod DUP_asimdins_DR_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DUP_asimdins_DR_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn DUP_asimdins_DR_r( Q: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,24 @@ pub mod SMOV_asimdins_W_w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMOV_asimdins_W_w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn SMOV_asimdins_W_w( imm5: ::aarchmrs_types::BitValue<5>, @@ -90,6 +156,24 @@ pub mod UMOV_asimdins_W_w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMOV_asimdins_W_w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn UMOV_asimdins_W_w( imm5: ::aarchmrs_types::BitValue<5>, @@ -114,6 +198,24 @@ pub mod INS_asimdins_IR_r { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "INS_asimdins_IR_r"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn INS_asimdins_IR_r( imm5: ::aarchmrs_types::BitValue<5>, @@ -138,6 +240,24 @@ pub mod SMOV_asimdins_X_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMOV_asimdins_X_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn SMOV_asimdins_X_x( imm5: ::aarchmrs_types::BitValue<5>, @@ -162,6 +282,24 @@ pub mod UMOV_asimdins_X_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMOV_asimdins_X_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 1u32; #[inline] pub const fn UMOV_asimdins_X_x( imm5: ::aarchmrs_types::BitValue<1>, @@ -186,6 +324,30 @@ pub mod INS_asimdins_IV_v { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "INS_asimdins_IV_v"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn INS_asimdins_IV_v( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdmisc.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdmisc.rs index 529e7f24..de360d03 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdmisc.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdmisc.rs @@ -12,6 +12,30 @@ pub mod REV64_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV64_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn REV64_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod REV16_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV16_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn REV16_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod SADDLP_asimdmisc_P { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADDLP_asimdmisc_P"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SADDLP_asimdmisc_P( Q: ::aarchmrs_types::BitValue<1>, @@ -93,6 +165,30 @@ pub mod SUQADD_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUQADD_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SUQADD_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -120,6 +216,30 @@ pub mod CLS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CLS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -147,6 +267,30 @@ pub mod CNT_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CNT_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CNT_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -174,6 +318,30 @@ pub mod SADALP_asimdmisc_P { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADALP_asimdmisc_P"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SADALP_asimdmisc_P( Q: ::aarchmrs_types::BitValue<1>, @@ -201,6 +369,30 @@ pub mod SQABS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQABS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQABS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -228,6 +420,30 @@ pub mod CMGT_asimdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGT_asimdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMGT_asimdmisc_Z( Q: ::aarchmrs_types::BitValue<1>, @@ -255,6 +471,30 @@ pub mod CMEQ_asimdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMEQ_asimdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMEQ_asimdmisc_Z( Q: ::aarchmrs_types::BitValue<1>, @@ -282,6 +522,30 @@ pub mod CMLT_asimdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMLT_asimdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMLT_asimdmisc_Z( Q: ::aarchmrs_types::BitValue<1>, @@ -309,6 +573,30 @@ pub mod ABS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ABS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ABS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -336,6 +624,30 @@ pub mod XTN_asimdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "XTN_asimdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn XTN_asimdmisc_N( Q: ::aarchmrs_types::BitValue<1>, @@ -363,6 +675,30 @@ pub mod SQXTN_asimdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQXTN_asimdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQXTN_asimdmisc_N( Q: ::aarchmrs_types::BitValue<1>, @@ -390,6 +726,30 @@ pub mod FCVTN_asimdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTN_asimdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTN_asimdmisc_N( Q: ::aarchmrs_types::BitValue<1>, @@ -417,6 +777,30 @@ pub mod FCVTL_asimdmisc_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTL_asimdmisc_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTL_asimdmisc_L( Q: ::aarchmrs_types::BitValue<1>, @@ -444,6 +828,30 @@ pub mod FRINTN_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTN_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTN_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -471,6 +879,30 @@ pub mod FRINTM_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTM_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTM_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -498,6 +930,30 @@ pub mod FCVTNS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTNS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -525,6 +981,30 @@ pub mod FCVTMS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTMS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -552,6 +1032,30 @@ pub mod FCVTAS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTAS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -579,6 +1083,30 @@ pub mod SCVTF_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SCVTF_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -606,6 +1134,30 @@ pub mod FRINT32Z_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT32Z_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINT32Z_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -633,6 +1185,30 @@ pub mod FRINT64Z_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT64Z_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINT64Z_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -660,6 +1236,30 @@ pub mod FCMGT_asimdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asimdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGT_asimdmisc_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -687,6 +1287,30 @@ pub mod FCMEQ_asimdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asimdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMEQ_asimdmisc_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -714,6 +1338,30 @@ pub mod FCMLT_asimdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLT_asimdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLT_asimdmisc_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -741,6 +1389,30 @@ pub mod FABS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FABS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -768,6 +1440,30 @@ pub mod FRINTP_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTP_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTP_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -795,6 +1491,30 @@ pub mod FRINTZ_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTZ_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTZ_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -822,6 +1542,30 @@ pub mod FCVTPS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTPS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -849,6 +1593,30 @@ pub mod FCVTZS_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZS_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -876,6 +1644,30 @@ pub mod URECPE_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URECPE_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn URECPE_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -903,6 +1695,30 @@ pub mod FRECPE_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPE_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRECPE_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -930,6 +1746,24 @@ pub mod BFCVTN_asimdmisc_4S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFCVTN_asimdmisc_4S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BFCVTN_asimdmisc_4S( Q: ::aarchmrs_types::BitValue<1>, @@ -954,6 +1788,30 @@ pub mod REV32_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV32_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn REV32_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -981,6 +1839,30 @@ pub mod UADDLP_asimdmisc_P { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADDLP_asimdmisc_P"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UADDLP_asimdmisc_P( Q: ::aarchmrs_types::BitValue<1>, @@ -1008,6 +1890,30 @@ pub mod USQADD_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USQADD_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USQADD_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1035,6 +1941,30 @@ pub mod CLZ_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLZ_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CLZ_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1062,6 +1992,30 @@ pub mod UADALP_asimdmisc_P { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADALP_asimdmisc_P"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UADALP_asimdmisc_P( Q: ::aarchmrs_types::BitValue<1>, @@ -1089,6 +2043,30 @@ pub mod SQNEG_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQNEG_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQNEG_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1116,6 +2094,30 @@ pub mod CMGE_asimdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGE_asimdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMGE_asimdmisc_Z( Q: ::aarchmrs_types::BitValue<1>, @@ -1143,6 +2145,30 @@ pub mod CMLE_asimdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMLE_asimdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMLE_asimdmisc_Z( Q: ::aarchmrs_types::BitValue<1>, @@ -1170,6 +2196,30 @@ pub mod NEG_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "NEG_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn NEG_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1197,6 +2247,30 @@ pub mod SQXTUN_asimdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQXTUN_asimdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQXTUN_asimdmisc_N( Q: ::aarchmrs_types::BitValue<1>, @@ -1224,6 +2298,30 @@ pub mod SHLL_asimdmisc_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHLL_asimdmisc_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SHLL_asimdmisc_S( Q: ::aarchmrs_types::BitValue<1>, @@ -1251,6 +2349,30 @@ pub mod UQXTN_asimdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQXTN_asimdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQXTN_asimdmisc_N( Q: ::aarchmrs_types::BitValue<1>, @@ -1278,6 +2400,24 @@ pub mod FCVTXN_asimdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTXN_asimdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTXN_asimdmisc_N( Q: ::aarchmrs_types::BitValue<1>, @@ -1302,6 +2442,30 @@ pub mod FRINTA_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTA_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTA_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1329,6 +2493,30 @@ pub mod FRINTX_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTX_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTX_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1356,6 +2544,30 @@ pub mod FCVTNU_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTNU_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1383,6 +2595,30 @@ pub mod FCVTMU_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTMU_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1410,6 +2646,30 @@ pub mod FCVTAU_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTAU_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1437,6 +2697,30 @@ pub mod UCVTF_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UCVTF_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1464,6 +2748,30 @@ pub mod FRINT32X_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT32X_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINT32X_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1491,6 +2799,30 @@ pub mod FRINT64X_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT64X_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINT64X_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1518,6 +2850,24 @@ pub mod NOT_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "NOT_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn NOT_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1542,6 +2892,24 @@ pub mod F1CVTL_asimdmisc_V { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "F1CVTL_asimdmisc_V"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn F1CVTL_asimdmisc_V( Q: ::aarchmrs_types::BitValue<1>, @@ -1566,6 +2934,24 @@ pub mod RBIT_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RBIT_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn RBIT_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1590,6 +2976,24 @@ pub mod F2CVTL_asimdmisc_V { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "F2CVTL_asimdmisc_V"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn F2CVTL_asimdmisc_V( Q: ::aarchmrs_types::BitValue<1>, @@ -1614,6 +3018,30 @@ pub mod FCMGE_asimdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asimdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGE_asimdmisc_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -1641,6 +3069,30 @@ pub mod FCMLE_asimdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLE_asimdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLE_asimdmisc_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -1668,6 +3120,30 @@ pub mod FNEG_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNEG_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FNEG_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1695,6 +3171,30 @@ pub mod FRINTI_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTI_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTI_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1722,6 +3222,30 @@ pub mod FCVTPU_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTPU_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1749,6 +3273,30 @@ pub mod FCVTZU_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZU_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1776,6 +3324,30 @@ pub mod URSQRTE_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URSQRTE_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn URSQRTE_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1803,6 +3375,30 @@ pub mod FRSQRTE_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTE_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRSQRTE_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1830,6 +3426,30 @@ pub mod FSQRT_asimdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSQRT_asimdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FSQRT_asimdmisc_R( Q: ::aarchmrs_types::BitValue<1>, @@ -1857,6 +3477,24 @@ pub mod BF1CVTL_asimdmisc_V { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BF1CVTL_asimdmisc_V"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BF1CVTL_asimdmisc_V( Q: ::aarchmrs_types::BitValue<1>, @@ -1881,6 +3519,24 @@ pub mod BF2CVTL_asimdmisc_V { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BF2CVTL_asimdmisc_V"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BF2CVTL_asimdmisc_V( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdmiscfp16.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdmiscfp16.rs index b45ac51f..099d9f89 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdmiscfp16.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdmiscfp16.rs @@ -12,6 +12,24 @@ pub mod FRINTN_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTN_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTN_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -36,6 +54,24 @@ pub mod FRINTM_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTM_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTM_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -60,6 +96,24 @@ pub mod FCVTNS_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTNS_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -84,6 +138,24 @@ pub mod FCVTMS_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTMS_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -108,6 +180,24 @@ pub mod FCVTAS_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTAS_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -132,6 +222,24 @@ pub mod SCVTF_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SCVTF_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -156,6 +264,24 @@ pub mod FCMGT_asimdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asimdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGT_asimdmiscfp16_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -180,6 +306,24 @@ pub mod FCMEQ_asimdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asimdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMEQ_asimdmiscfp16_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -204,6 +348,24 @@ pub mod FCMLT_asimdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLT_asimdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLT_asimdmiscfp16_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -228,6 +390,24 @@ pub mod FABS_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABS_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FABS_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -252,6 +432,24 @@ pub mod FRINTP_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTP_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTP_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -276,6 +474,24 @@ pub mod FRINTZ_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTZ_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTZ_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -300,6 +516,24 @@ pub mod FCVTPS_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTPS_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -324,6 +558,24 @@ pub mod FCVTZS_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZS_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -348,6 +600,24 @@ pub mod FRECPE_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPE_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRECPE_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -372,6 +642,24 @@ pub mod FRINTA_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTA_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTA_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -396,6 +684,24 @@ pub mod FRINTX_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTX_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTX_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -420,6 +726,24 @@ pub mod FCVTNU_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTNU_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -444,6 +768,24 @@ pub mod FCVTMU_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTMU_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -468,6 +810,24 @@ pub mod FCVTAU_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTAU_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -492,6 +852,24 @@ pub mod UCVTF_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UCVTF_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -516,6 +894,24 @@ pub mod FCMGE_asimdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asimdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGE_asimdmiscfp16_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -540,6 +936,24 @@ pub mod FCMLE_asimdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLE_asimdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLE_asimdmiscfp16_FZ( Q: ::aarchmrs_types::BitValue<1>, @@ -564,6 +978,24 @@ pub mod FNEG_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNEG_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FNEG_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -588,6 +1020,24 @@ pub mod FRINTI_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTI_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRINTI_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -612,6 +1062,24 @@ pub mod FCVTPU_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTPU_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -636,6 +1104,24 @@ pub mod FCVTZU_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZU_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -660,6 +1146,24 @@ pub mod FRSQRTE_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTE_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRSQRTE_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, @@ -684,6 +1188,24 @@ pub mod FSQRT_asimdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSQRT_asimdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FSQRT_asimdmiscfp16_R( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdperm.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdperm.rs index 31292741..89e5d55d 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdperm.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdperm.rs @@ -12,6 +12,36 @@ pub mod UZP1_asimdperm_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UZP1_asimdperm_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UZP1_asimdperm_only( Q: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,36 @@ pub mod TRN1_asimdperm_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TRN1_asimdperm_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TRN1_asimdperm_only( Q: ::aarchmrs_types::BitValue<1>, @@ -72,6 +132,36 @@ pub mod ZIP1_asimdperm_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ZIP1_asimdperm_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ZIP1_asimdperm_only( Q: ::aarchmrs_types::BitValue<1>, @@ -102,6 +192,36 @@ pub mod UZP2_asimdperm_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UZP2_asimdperm_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UZP2_asimdperm_only( Q: ::aarchmrs_types::BitValue<1>, @@ -132,6 +252,36 @@ pub mod TRN2_asimdperm_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TRN2_asimdperm_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TRN2_asimdperm_only( Q: ::aarchmrs_types::BitValue<1>, @@ -162,6 +312,36 @@ pub mod ZIP2_asimdperm_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ZIP2_asimdperm_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ZIP2_asimdperm_only( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdsame.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdsame.rs index fb85cab2..ec06c610 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdsame.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdsame.rs @@ -12,6 +12,36 @@ pub mod SHADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SHADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,36 @@ pub mod SQADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -72,6 +132,36 @@ pub mod SRHADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRHADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SRHADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -102,6 +192,36 @@ pub mod SHSUB_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHSUB_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SHSUB_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -132,6 +252,36 @@ pub mod SQSUB_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSUB_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQSUB_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -162,6 +312,36 @@ pub mod CMGT_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGT_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMGT_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -192,6 +372,36 @@ pub mod CMGE_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGE_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMGE_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -222,6 +432,36 @@ pub mod SSHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SSHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -252,6 +492,36 @@ pub mod SQSHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQSHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -282,6 +552,36 @@ pub mod SRSHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SRSHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -312,6 +612,36 @@ pub mod SQRSHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRSHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRSHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -342,6 +672,36 @@ pub mod SMAX_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMAX_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMAX_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -372,6 +732,36 @@ pub mod SMIN_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMIN_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMIN_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -402,6 +792,36 @@ pub mod SABD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SABD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SABD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -432,6 +852,36 @@ pub mod SABA_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SABA_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SABA_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -462,6 +912,36 @@ pub mod ADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -492,6 +972,36 @@ pub mod CMTST_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMTST_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMTST_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -522,6 +1032,36 @@ pub mod MLA_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLA_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MLA_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -552,6 +1092,36 @@ pub mod MUL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MUL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MUL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -582,6 +1152,36 @@ pub mod SMAXP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMAXP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMAXP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -612,6 +1212,36 @@ pub mod SMINP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMINP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SMINP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -642,6 +1272,36 @@ pub mod SQDMULH_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULH_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQDMULH_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -672,6 +1332,36 @@ pub mod ADDP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ADDP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -702,6 +1392,36 @@ pub mod FMAXNM_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNM_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXNM_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -732,6 +1452,36 @@ pub mod FMLA_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLA_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLA_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -762,6 +1512,36 @@ pub mod FADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -792,6 +1572,36 @@ pub mod FMULX_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMULX_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -822,6 +1632,36 @@ pub mod FCMEQ_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMEQ_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -852,6 +1692,36 @@ pub mod FMAX_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAX_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAX_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -882,6 +1752,36 @@ pub mod FRECPS_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPS_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRECPS_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -912,6 +1812,30 @@ pub mod AND_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn AND_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -939,6 +1863,30 @@ pub mod FMLAL_asimdsame_F { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLAL_asimdsame_F"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLAL_asimdsame_F( Q: ::aarchmrs_types::BitValue<1>, @@ -966,6 +1914,30 @@ pub mod BIC_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BIC_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -993,6 +1965,36 @@ pub mod FMINNM_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNM_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINNM_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1023,6 +2025,36 @@ pub mod FMLS_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLS_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLS_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1053,6 +2085,36 @@ pub mod FSUB_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSUB_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FSUB_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1083,6 +2145,36 @@ pub mod FAMAX_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FAMAX_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FAMAX_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1113,6 +2205,36 @@ pub mod FMIN_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMIN_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMIN_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1143,6 +2265,36 @@ pub mod FRSQRTS_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTS_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRSQRTS_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1173,6 +2325,30 @@ pub mod ORR_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ORR_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1200,6 +2376,30 @@ pub mod FMLSL_asimdsame_F { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLSL_asimdsame_F"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLSL_asimdsame_F( Q: ::aarchmrs_types::BitValue<1>, @@ -1227,6 +2427,30 @@ pub mod ORN_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORN_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn ORN_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1254,6 +2478,36 @@ pub mod UHADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UHADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1284,6 +2538,36 @@ pub mod UQADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1314,6 +2598,36 @@ pub mod URHADD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URHADD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn URHADD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1344,6 +2658,36 @@ pub mod UHSUB_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHSUB_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UHSUB_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1374,6 +2718,36 @@ pub mod UQSUB_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSUB_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQSUB_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1404,6 +2778,36 @@ pub mod CMHI_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMHI_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMHI_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1434,6 +2838,36 @@ pub mod CMHS_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMHS_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMHS_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1464,6 +2898,36 @@ pub mod USHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1494,6 +2958,36 @@ pub mod UQSHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQSHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1524,6 +3018,36 @@ pub mod URSHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URSHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn URSHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1554,6 +3078,36 @@ pub mod UQRSHL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQRSHL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQRSHL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1584,6 +3138,36 @@ pub mod UMAX_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAX_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMAX_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1614,6 +3198,36 @@ pub mod UMIN_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMIN_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMIN_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1644,6 +3258,36 @@ pub mod UABD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UABD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UABD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1674,6 +3318,36 @@ pub mod UABA_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UABA_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UABA_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1704,6 +3378,36 @@ pub mod SUB_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SUB_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1734,6 +3438,36 @@ pub mod CMEQ_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMEQ_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn CMEQ_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1764,6 +3498,36 @@ pub mod MLS_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLS_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn MLS_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1794,6 +3558,36 @@ pub mod PMUL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PMUL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn PMUL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1824,6 +3618,36 @@ pub mod UMAXP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAXP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMAXP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1854,6 +3678,36 @@ pub mod UMINP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMINP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UMINP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1884,6 +3738,36 @@ pub mod SQRDMULH_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMULH_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRDMULH_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1914,6 +3798,36 @@ pub mod FMAXNMP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNMP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXNMP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1944,6 +3858,36 @@ pub mod FADDP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADDP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FADDP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -1974,6 +3918,36 @@ pub mod FMUL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMUL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2004,6 +3978,36 @@ pub mod FCMGE_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGE_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2034,6 +4038,36 @@ pub mod FACGE_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGE_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FACGE_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2064,6 +4098,36 @@ pub mod FMAXP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2094,6 +4158,36 @@ pub mod FDIV_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDIV_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDIV_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2124,6 +4218,30 @@ pub mod EOR_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn EOR_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2151,6 +4269,30 @@ pub mod FMLAL2_asimdsame_F { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLAL2_asimdsame_F"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLAL2_asimdsame_F( Q: ::aarchmrs_types::BitValue<1>, @@ -2178,6 +4320,30 @@ pub mod BSL_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BSL_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BSL_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2205,6 +4371,36 @@ pub mod FMINNMP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNMP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINNMP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2235,6 +4431,36 @@ pub mod FABD_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABD_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FABD_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2265,6 +4491,36 @@ pub mod FAMIN_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FAMIN_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FAMIN_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2295,6 +4551,36 @@ pub mod FCMGT_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGT_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2325,6 +4611,36 @@ pub mod FACGT_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGT_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FACGT_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2355,6 +4671,36 @@ pub mod FMINP_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINP_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINP_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2385,6 +4731,36 @@ pub mod FSCALE_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSCALE_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FSCALE_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2415,6 +4791,30 @@ pub mod BIT_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIT_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BIT_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, @@ -2442,6 +4842,30 @@ pub mod FMLSL2_asimdsame_F { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLSL2_asimdsame_F"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLSL2_asimdsame_F( Q: ::aarchmrs_types::BitValue<1>, @@ -2469,6 +4893,30 @@ pub mod BIF_asimdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIF_asimdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BIF_asimdsame_only( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdsame2.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdsame2.rs index 92f0c87e..5a5fd420 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdsame2.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdsame2.rs @@ -12,6 +12,36 @@ pub mod SDOT_asimdsame2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SDOT_asimdsame2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SDOT_asimdsame2_D( Q: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,30 @@ pub mod FCVTN_asimdsame2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTN_asimdsame2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTN_asimdsame2_H( Q: ::aarchmrs_types::BitValue<1>, @@ -69,6 +123,30 @@ pub mod FDOT_asimdsame2_DD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDOT_asimdsame2_DD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDOT_asimdsame2_DD( Q: ::aarchmrs_types::BitValue<1>, @@ -96,6 +174,30 @@ pub mod FCVTN_asimdsame2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTN_asimdsame2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTN_asimdsame2_D( Q: ::aarchmrs_types::BitValue<1>, @@ -123,6 +225,30 @@ pub mod FDOT_asimdsame2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDOT_asimdsame2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDOT_asimdsame2_D( Q: ::aarchmrs_types::BitValue<1>, @@ -150,6 +276,30 @@ pub mod USDOT_asimdsame2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USDOT_asimdsame2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USDOT_asimdsame2_D( Q: ::aarchmrs_types::BitValue<1>, @@ -177,6 +327,30 @@ pub mod FDOT_asimdsame2_FP16FP32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDOT_asimdsame2_FP16FP32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDOT_asimdsame2_FP16FP32( Q: ::aarchmrs_types::BitValue<1>, @@ -204,6 +378,36 @@ pub mod SQRDMLAH_asimdsame2_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLAH_asimdsame2_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRDMLAH_asimdsame2_only( Q: ::aarchmrs_types::BitValue<1>, @@ -234,6 +438,36 @@ pub mod SQRDMLSH_asimdsame2_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLSH_asimdsame2_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRDMLSH_asimdsame2_only( Q: ::aarchmrs_types::BitValue<1>, @@ -264,6 +498,36 @@ pub mod UDOT_asimdsame2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDOT_asimdsame2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UDOT_asimdsame2_D( Q: ::aarchmrs_types::BitValue<1>, @@ -294,6 +558,42 @@ pub mod FCMLA_asimdsame2_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLA_asimdsame2_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLA_asimdsame2_C( Q: ::aarchmrs_types::BitValue<1>, @@ -327,6 +627,42 @@ pub mod FCADD_asimdsame2_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCADD_asimdsame2_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCADD_asimdsame2_C( Q: ::aarchmrs_types::BitValue<1>, @@ -360,6 +696,30 @@ pub mod BFDOT_asimdsame2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFDOT_asimdsame2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BFDOT_asimdsame2_D( Q: ::aarchmrs_types::BitValue<1>, @@ -387,6 +747,30 @@ pub mod BFMLAL_asimdsame2_F_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFMLAL_asimdsame2_F_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn BFMLAL_asimdsame2_F_( Q: ::aarchmrs_types::BitValue<1>, @@ -414,6 +798,24 @@ pub mod FMLALLBB_asimdsame2_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLBB_asimdsame2_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMLALLBB_asimdsame2_G( Rm: ::aarchmrs_types::BitValue<5>, @@ -438,6 +840,24 @@ pub mod FMLALLBT_asimdsame2_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLBT_asimdsame2_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMLALLBT_asimdsame2_G( Rm: ::aarchmrs_types::BitValue<5>, @@ -462,6 +882,24 @@ pub mod FMLALB_asimdsame2_J { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALB_asimdsame2_J"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMLALB_asimdsame2_J( Rm: ::aarchmrs_types::BitValue<5>, @@ -486,6 +924,24 @@ pub mod FMLALLTB_asimdsame2_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLTB_asimdsame2_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMLALLTB_asimdsame2_G( Rm: ::aarchmrs_types::BitValue<5>, @@ -510,6 +966,24 @@ pub mod FMLALLTT_asimdsame2_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALLTT_asimdsame2_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMLALLTT_asimdsame2_G( Rm: ::aarchmrs_types::BitValue<5>, @@ -534,6 +1008,24 @@ pub mod SMMLA_asimdsame2_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLA_asimdsame2_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SMMLA_asimdsame2_G( Rm: ::aarchmrs_types::BitValue<5>, @@ -558,6 +1050,24 @@ pub mod USMMLA_asimdsame2_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USMMLA_asimdsame2_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn USMMLA_asimdsame2_G( Rm: ::aarchmrs_types::BitValue<5>, @@ -582,6 +1092,24 @@ pub mod FMMLA_asimd_FP16FP16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMMLA_asimd_FP16FP16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMMLA_asimd_FP16FP16( Rm: ::aarchmrs_types::BitValue<5>, @@ -606,6 +1134,24 @@ pub mod FMLALT_asimdsame2_J { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLALT_asimdsame2_J"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMLALT_asimdsame2_J( Rm: ::aarchmrs_types::BitValue<5>, @@ -630,6 +1176,24 @@ pub mod FMMLA_asimd_FP8FP16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMMLA_asimd_FP8FP16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMMLA_asimd_FP8FP16( Rm: ::aarchmrs_types::BitValue<5>, @@ -654,6 +1218,24 @@ pub mod FMMLA_asimd_FP16FP32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMMLA_asimd_FP16FP32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMMLA_asimd_FP16FP32( Rm: ::aarchmrs_types::BitValue<5>, @@ -678,6 +1260,24 @@ pub mod BFMMLA_asimdsame2_E { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFMMLA_asimdsame2_E"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn BFMMLA_asimdsame2_E( Rm: ::aarchmrs_types::BitValue<5>, @@ -702,6 +1302,24 @@ pub mod FMMLA_asimd_FP8FP32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMMLA_asimd_FP8FP32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMMLA_asimd_FP8FP32( Rm: ::aarchmrs_types::BitValue<5>, @@ -726,6 +1344,24 @@ pub mod UMMLA_asimdsame2_G { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMMLA_asimdsame2_G"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn UMMLA_asimdsame2_G( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdsamefp16.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdsamefp16.rs index c2c69985..a1d2f524 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdsamefp16.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdsamefp16.rs @@ -12,6 +12,30 @@ pub mod FMAXNM_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNM_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXNM_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod FMLA_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLA_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLA_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod FADD_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADD_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FADD_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -93,6 +165,30 @@ pub mod FMULX_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMULX_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -120,6 +216,30 @@ pub mod FCMEQ_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMEQ_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -147,6 +267,30 @@ pub mod FMAX_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAX_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAX_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -174,6 +318,30 @@ pub mod FRECPS_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPS_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRECPS_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -201,6 +369,30 @@ pub mod FMINNM_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNM_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINNM_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -228,6 +420,30 @@ pub mod FMLS_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLS_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMLS_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -255,6 +471,30 @@ pub mod FSUB_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSUB_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FSUB_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -282,6 +522,30 @@ pub mod FAMAX_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FAMAX_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FAMAX_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -309,6 +573,30 @@ pub mod FMIN_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMIN_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMIN_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -336,6 +624,30 @@ pub mod FRSQRTS_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTS_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FRSQRTS_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -363,6 +675,30 @@ pub mod FMAXNMP_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNMP_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXNMP_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -390,6 +726,30 @@ pub mod FADDP_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADDP_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FADDP_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -417,6 +777,30 @@ pub mod FMUL_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMUL_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -444,6 +828,30 @@ pub mod FCMGE_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGE_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -471,6 +879,30 @@ pub mod FACGE_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGE_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FACGE_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -498,6 +930,30 @@ pub mod FMAXP_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXP_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXP_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -525,6 +981,30 @@ pub mod FDIV_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDIV_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FDIV_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -552,6 +1032,30 @@ pub mod FMINNMP_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNMP_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINNMP_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -579,6 +1083,30 @@ pub mod FABD_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABD_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FABD_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -606,6 +1134,30 @@ pub mod FAMIN_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FAMIN_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FAMIN_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -633,6 +1185,30 @@ pub mod FCMGT_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGT_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -660,6 +1236,30 @@ pub mod FACGT_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGT_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FACGT_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -687,6 +1287,30 @@ pub mod FMINP_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINP_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FMINP_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, @@ -714,6 +1338,30 @@ pub mod FSCALE_asimdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSCALE_asimdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FSCALE_asimdsamefp16_only( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdshf.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdshf.rs index 4dfbc049..dceb4ffd 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdshf.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdshf.rs @@ -12,6 +12,36 @@ pub mod SSHR_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSHR_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SSHR_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod SSRA_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSRA_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SSRA_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod SRSHR_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSHR_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SRSHR_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod SRSRA_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSRA_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SRSRA_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod SHL_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHL_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SHL_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -157,6 +307,36 @@ pub mod SQSHL_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHL_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQSHL_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod SHRN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHRN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SHRN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -215,6 +425,36 @@ pub mod RSHRN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSHRN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn RSHRN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -244,6 +484,36 @@ pub mod SQSHRN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHRN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQSHRN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -273,6 +543,36 @@ pub mod SQRSHRN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRSHRN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRSHRN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -302,6 +602,36 @@ pub mod SSHLL_asimdshf_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSHLL_asimdshf_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SSHLL_asimdshf_L( Q: ::aarchmrs_types::BitValue<1>, @@ -331,6 +661,36 @@ pub mod SCVTF_asimdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_asimdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SCVTF_asimdshf_C( Q: ::aarchmrs_types::BitValue<1>, @@ -360,6 +720,36 @@ pub mod FCVTZS_asimdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_asimdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZS_asimdshf_C( Q: ::aarchmrs_types::BitValue<1>, @@ -389,6 +779,36 @@ pub mod USHR_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USHR_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USHR_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -418,6 +838,36 @@ pub mod USRA_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USRA_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USRA_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -447,6 +897,36 @@ pub mod URSHR_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URSHR_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn URSHR_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -476,6 +956,36 @@ pub mod URSRA_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URSRA_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn URSRA_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -505,6 +1015,36 @@ pub mod SRI_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRI_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SRI_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -534,6 +1074,36 @@ pub mod SLI_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SLI_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SLI_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -563,6 +1133,36 @@ pub mod SQSHLU_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHLU_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQSHLU_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -592,6 +1192,36 @@ pub mod UQSHL_asimdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSHL_asimdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQSHL_asimdshf_R( Q: ::aarchmrs_types::BitValue<1>, @@ -621,6 +1251,36 @@ pub mod SQSHRUN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHRUN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQSHRUN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -650,6 +1310,36 @@ pub mod SQRSHRUN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRSHRUN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn SQRSHRUN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -679,6 +1369,36 @@ pub mod UQSHRN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSHRN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQSHRN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -708,6 +1428,36 @@ pub mod UQRSHRN_asimdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQRSHRN_asimdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UQRSHRN_asimdshf_N( Q: ::aarchmrs_types::BitValue<1>, @@ -737,6 +1487,36 @@ pub mod USHLL_asimdshf_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USHLL_asimdshf_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn USHLL_asimdshf_L( Q: ::aarchmrs_types::BitValue<1>, @@ -766,6 +1546,36 @@ pub mod UCVTF_asimdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_asimdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn UCVTF_asimdshf_C( Q: ::aarchmrs_types::BitValue<1>, @@ -795,6 +1605,36 @@ pub mod FCVTZU_asimdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_asimdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZU_asimdshf_C( Q: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asimdtbl.rs b/aarchmrs-instructions/src/A64/simd_dp/asimdtbl.rs index 012783aa..e7a5e623 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asimdtbl.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asimdtbl.rs @@ -12,6 +12,30 @@ pub mod TBL_asimdtbl_L1_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBL_asimdtbl_L1_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBL_asimdtbl_L1_1( Q: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod TBX_asimdtbl_L1_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBX_asimdtbl_L1_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBX_asimdtbl_L1_1( Q: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod TBL_asimdtbl_L2_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBL_asimdtbl_L2_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBL_asimdtbl_L2_2( Q: ::aarchmrs_types::BitValue<1>, @@ -93,6 +165,30 @@ pub mod TBX_asimdtbl_L2_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBX_asimdtbl_L2_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBX_asimdtbl_L2_2( Q: ::aarchmrs_types::BitValue<1>, @@ -120,6 +216,30 @@ pub mod TBL_asimdtbl_L3_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBL_asimdtbl_L3_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBL_asimdtbl_L3_3( Q: ::aarchmrs_types::BitValue<1>, @@ -147,6 +267,30 @@ pub mod TBX_asimdtbl_L3_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBX_asimdtbl_L3_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBX_asimdtbl_L3_3( Q: ::aarchmrs_types::BitValue<1>, @@ -174,6 +318,30 @@ pub mod TBL_asimdtbl_L4_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBL_asimdtbl_L4_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBL_asimdtbl_L4_4( Q: ::aarchmrs_types::BitValue<1>, @@ -201,6 +369,30 @@ pub mod TBX_asimdtbl_L4_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBX_asimdtbl_L4_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 30u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; #[inline] pub const fn TBX_asimdtbl_L4_4( Q: ::aarchmrs_types::BitValue<1>, @@ -228,6 +420,30 @@ pub mod LUTI4_asimdtbl_L7 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LUTI4_asimdtbl_L7"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LUTI4_asimdtbl_L7( Rm: ::aarchmrs_types::BitValue<5>, @@ -255,6 +471,30 @@ pub mod LUTI4_asimdtbl_L5 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LUTI4_asimdtbl_L5"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LUTI4_asimdtbl_L5( Rm: ::aarchmrs_types::BitValue<5>, @@ -282,6 +522,30 @@ pub mod LUTI2_asimdtbl_L5 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LUTI2_asimdtbl_L5"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LUTI2_asimdtbl_L5( Rm: ::aarchmrs_types::BitValue<5>, @@ -309,6 +573,36 @@ pub mod LUTI2_asimdtbl_L6 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LUTI2_asimdtbl_L6"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn LUTI2_asimdtbl_L6( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisddiff.rs b/aarchmrs-instructions/src/A64/simd_dp/asisddiff.rs index 345c92d9..07ac1c02 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisddiff.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisddiff.rs @@ -12,6 +12,30 @@ pub mod SQDMLAL_asisddiff_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLAL_asisddiff_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMLAL_asisddiff_only( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod SQDMLSL_asisddiff_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLSL_asisddiff_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMLSL_asisddiff_only( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod SQDMULL_asisddiff_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULL_asisddiff_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMULL_asisddiff_only( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdelem.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdelem.rs index 13b7a133..4aac872a 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdelem.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdelem.rs @@ -12,6 +12,48 @@ pub mod SQDMLAL_asisdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLAL_asisdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMLAL_asisdelem_L( size: ::aarchmrs_types::BitValue<2>, @@ -45,6 +87,48 @@ pub mod SQDMLSL_asisdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMLSL_asisdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMLSL_asisdelem_L( size: ::aarchmrs_types::BitValue<2>, @@ -78,6 +162,48 @@ pub mod SQDMULL_asisdelem_L { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULL_asisdelem_L"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMULL_asisdelem_L( size: ::aarchmrs_types::BitValue<2>, @@ -111,6 +237,48 @@ pub mod SQDMULH_asisdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULH_asisdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMULH_asisdelem_R( size: ::aarchmrs_types::BitValue<2>, @@ -144,6 +312,48 @@ pub mod SQRDMULH_asisdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMULH_asisdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQRDMULH_asisdelem_R( size: ::aarchmrs_types::BitValue<2>, @@ -177,6 +387,42 @@ pub mod FMLA_asisdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLA_asisdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLA_asisdelem_RH_H( L: ::aarchmrs_types::BitValue<1>, @@ -208,6 +454,42 @@ pub mod FMLS_asisdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLS_asisdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMLS_asisdelem_RH_H( L: ::aarchmrs_types::BitValue<1>, @@ -239,6 +521,42 @@ pub mod FMUL_asisdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_asisdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMUL_asisdelem_RH_H( L: ::aarchmrs_types::BitValue<1>, @@ -270,6 +588,48 @@ pub mod FMLA_asisdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLA_asisdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMLA_asisdelem_R_SD( sz: ::aarchmrs_types::BitValue<1>, @@ -303,6 +663,48 @@ pub mod FMLS_asisdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMLS_asisdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMLS_asisdelem_R_SD( sz: ::aarchmrs_types::BitValue<1>, @@ -336,6 +738,48 @@ pub mod FMUL_asisdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_asisdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMUL_asisdelem_R_SD( sz: ::aarchmrs_types::BitValue<1>, @@ -369,6 +813,48 @@ pub mod SQRDMLAH_asisdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLAH_asisdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQRDMLAH_asisdelem_R( size: ::aarchmrs_types::BitValue<2>, @@ -402,6 +888,48 @@ pub mod SQRDMLSH_asisdelem_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLSH_asisdelem_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQRDMLSH_asisdelem_R( size: ::aarchmrs_types::BitValue<2>, @@ -435,6 +963,42 @@ pub mod FMULX_asisdelem_RH_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asisdelem_RH_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; #[inline] pub const fn FMULX_asisdelem_RH_H( L: ::aarchmrs_types::BitValue<1>, @@ -466,6 +1030,48 @@ pub mod FMULX_asisdelem_R_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asisdelem_R_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMULX_asisdelem_R_SD( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdmisc.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdmisc.rs index ec36186b..04f3dd7d 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdmisc.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdmisc.rs @@ -12,6 +12,24 @@ pub mod SUQADD_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUQADD_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SUQADD_asisdmisc_R( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod SQABS_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQABS_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQABS_asisdmisc_R( size: ::aarchmrs_types::BitValue<2>, @@ -60,6 +96,18 @@ pub mod CMGT_asisdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGT_asisdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CMGT_asisdmisc_Z( Rn: ::aarchmrs_types::BitValue<5>, @@ -81,6 +129,18 @@ pub mod CMEQ_asisdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMEQ_asisdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CMEQ_asisdmisc_Z( Rn: ::aarchmrs_types::BitValue<5>, @@ -102,6 +162,18 @@ pub mod CMLT_asisdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMLT_asisdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CMLT_asisdmisc_Z( Rn: ::aarchmrs_types::BitValue<5>, @@ -123,6 +195,18 @@ pub mod ABS_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ABS_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn ABS_asisdmisc_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -144,6 +228,24 @@ pub mod SQXTN_asisdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQXTN_asisdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQXTN_asisdmisc_N( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +270,24 @@ pub mod FCVTNS_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTNS_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -192,6 +312,24 @@ pub mod FCVTMS_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTMS_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -216,6 +354,24 @@ pub mod FCVTAS_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTAS_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -240,6 +396,24 @@ pub mod SCVTF_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn SCVTF_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -264,6 +438,24 @@ pub mod FCMGT_asisdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asisdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGT_asisdmisc_FZ( sz: ::aarchmrs_types::BitValue<1>, @@ -288,6 +480,24 @@ pub mod FCMEQ_asisdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asisdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMEQ_asisdmisc_FZ( sz: ::aarchmrs_types::BitValue<1>, @@ -312,6 +522,24 @@ pub mod FCMLT_asisdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLT_asisdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLT_asisdmisc_FZ( sz: ::aarchmrs_types::BitValue<1>, @@ -336,6 +564,24 @@ pub mod FCVTPS_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTPS_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -360,6 +606,24 @@ pub mod FCVTZS_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZS_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -384,6 +648,24 @@ pub mod FRECPE_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPE_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FRECPE_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -408,6 +690,24 @@ pub mod FRECPX_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPX_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FRECPX_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -432,6 +732,24 @@ pub mod USQADD_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USQADD_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn USQADD_asisdmisc_R( size: ::aarchmrs_types::BitValue<2>, @@ -456,6 +774,24 @@ pub mod SQNEG_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQNEG_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQNEG_asisdmisc_R( size: ::aarchmrs_types::BitValue<2>, @@ -480,6 +816,18 @@ pub mod CMGE_asisdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGE_asisdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CMGE_asisdmisc_Z( Rn: ::aarchmrs_types::BitValue<5>, @@ -501,6 +849,18 @@ pub mod CMLE_asisdmisc_Z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMLE_asisdmisc_Z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn CMLE_asisdmisc_Z( Rn: ::aarchmrs_types::BitValue<5>, @@ -522,6 +882,18 @@ pub mod NEG_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "NEG_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn NEG_asisdmisc_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -543,6 +915,24 @@ pub mod SQXTUN_asisdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQXTUN_asisdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQXTUN_asisdmisc_N( size: ::aarchmrs_types::BitValue<2>, @@ -567,6 +957,24 @@ pub mod UQXTN_asisdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQXTN_asisdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn UQXTN_asisdmisc_N( size: ::aarchmrs_types::BitValue<2>, @@ -591,6 +999,18 @@ pub mod FCVTXN_asisdmisc_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTXN_asisdmisc_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTXN_asisdmisc_N( Rn: ::aarchmrs_types::BitValue<5>, @@ -612,6 +1032,24 @@ pub mod FCVTNU_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTNU_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -636,6 +1074,24 @@ pub mod FCVTMU_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTMU_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -660,6 +1116,24 @@ pub mod FCVTAU_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTAU_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -684,6 +1158,24 @@ pub mod UCVTF_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn UCVTF_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -708,6 +1200,24 @@ pub mod FCMGE_asisdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asisdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGE_asisdmisc_FZ( sz: ::aarchmrs_types::BitValue<1>, @@ -732,6 +1242,24 @@ pub mod FCMLE_asisdmisc_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLE_asisdmisc_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMLE_asisdmisc_FZ( sz: ::aarchmrs_types::BitValue<1>, @@ -756,6 +1284,24 @@ pub mod FCVTPU_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTPU_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -780,6 +1326,24 @@ pub mod FCVTZU_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCVTZU_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, @@ -804,6 +1368,24 @@ pub mod FRSQRTE_asisdmisc_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTE_asisdmisc_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FRSQRTE_asisdmisc_R( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdmiscfp16.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdmiscfp16.rs index 496092c3..5e68ce3a 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdmiscfp16.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdmiscfp16.rs @@ -12,6 +12,18 @@ pub mod FCVTNS_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod FCVTMS_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod FCVTAS_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod SCVTF_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -96,6 +144,18 @@ pub mod FCMGT_asisdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asisdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMGT_asisdmiscfp16_FZ( Rn: ::aarchmrs_types::BitValue<5>, @@ -117,6 +177,18 @@ pub mod FCMEQ_asisdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asisdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMEQ_asisdmiscfp16_FZ( Rn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +210,18 @@ pub mod FCMLT_asisdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLT_asisdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMLT_asisdmiscfp16_FZ( Rn: ::aarchmrs_types::BitValue<5>, @@ -159,6 +243,18 @@ pub mod FCVTPS_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -180,6 +276,18 @@ pub mod FCVTZS_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -201,6 +309,18 @@ pub mod FRECPE_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPE_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRECPE_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -222,6 +342,18 @@ pub mod FRECPX_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPX_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRECPX_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -243,6 +375,18 @@ pub mod FCVTNU_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -264,6 +408,18 @@ pub mod FCVTMU_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -285,6 +441,18 @@ pub mod FCVTAU_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -306,6 +474,18 @@ pub mod UCVTF_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -327,6 +507,18 @@ pub mod FCMGE_asisdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asisdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMGE_asisdmiscfp16_FZ( Rn: ::aarchmrs_types::BitValue<5>, @@ -348,6 +540,18 @@ pub mod FCMLE_asisdmiscfp16_FZ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMLE_asisdmiscfp16_FZ"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMLE_asisdmiscfp16_FZ( Rn: ::aarchmrs_types::BitValue<5>, @@ -369,6 +573,18 @@ pub mod FCVTPU_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -390,6 +606,18 @@ pub mod FCVTZU_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, @@ -411,6 +639,18 @@ pub mod FRSQRTE_asisdmiscfp16_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTE_asisdmiscfp16_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRSQRTE_asisdmiscfp16_R( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdone.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdone.rs index 56bc69e1..26245c09 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdone.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdone.rs @@ -12,6 +12,24 @@ pub mod DUP_asisdone_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DUP_asisdone_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn DUP_asisdone_only( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdpair.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdpair.rs index 4322b6df..4dc688af 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdpair.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdpair.rs @@ -12,6 +12,18 @@ pub mod ADDP_asisdpair_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDP_asisdpair_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn ADDP_asisdpair_only( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod FMAXNMP_asisdpair_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNMP_asisdpair_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMAXNMP_asisdpair_only_H( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod FADDP_asisdpair_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADDP_asisdpair_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FADDP_asisdpair_only_H( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod FMAXP_asisdpair_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXP_asisdpair_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMAXP_asisdpair_only_H( Rn: ::aarchmrs_types::BitValue<5>, @@ -96,6 +144,18 @@ pub mod FMINNMP_asisdpair_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNMP_asisdpair_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMINNMP_asisdpair_only_H( Rn: ::aarchmrs_types::BitValue<5>, @@ -117,6 +177,18 @@ pub mod FMINP_asisdpair_only_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINP_asisdpair_only_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMINP_asisdpair_only_H( Rn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +210,24 @@ pub mod FMAXNMP_asisdpair_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNMP_asisdpair_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXNMP_asisdpair_only_SD( sz: ::aarchmrs_types::BitValue<1>, @@ -162,6 +252,24 @@ pub mod FADDP_asisdpair_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADDP_asisdpair_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FADDP_asisdpair_only_SD( sz: ::aarchmrs_types::BitValue<1>, @@ -186,6 +294,24 @@ pub mod FMAXP_asisdpair_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXP_asisdpair_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMAXP_asisdpair_only_SD( sz: ::aarchmrs_types::BitValue<1>, @@ -210,6 +336,24 @@ pub mod FMINNMP_asisdpair_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNMP_asisdpair_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMINNMP_asisdpair_only_SD( sz: ::aarchmrs_types::BitValue<1>, @@ -234,6 +378,24 @@ pub mod FMINP_asisdpair_only_SD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINP_asisdpair_only_SD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMINP_asisdpair_only_SD( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdsame.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdsame.rs index ab8d7d2e..cf1ed428 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdsame.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdsame.rs @@ -12,6 +12,30 @@ pub mod SQADD_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQADD_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQADD_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod SQSUB_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSUB_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQSUB_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,24 @@ pub mod CMGT_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGT_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CMGT_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +156,24 @@ pub mod CMGE_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMGE_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CMGE_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -114,6 +198,24 @@ pub mod SSHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SSHL_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -138,6 +240,30 @@ pub mod SQSHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQSHL_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -165,6 +291,24 @@ pub mod SRSHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SRSHL_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -189,6 +333,30 @@ pub mod SQRSHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRSHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQRSHL_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -216,6 +384,24 @@ pub mod ADD_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ADD_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -240,6 +426,24 @@ pub mod CMTST_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMTST_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CMTST_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -264,6 +468,30 @@ pub mod SQDMULH_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQDMULH_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQDMULH_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -291,6 +519,30 @@ pub mod FMULX_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FMULX_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -318,6 +570,30 @@ pub mod FCMEQ_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMEQ_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -345,6 +621,30 @@ pub mod FRECPS_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPS_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FRECPS_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -372,6 +672,30 @@ pub mod FRSQRTS_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTS_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FRSQRTS_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -399,6 +723,30 @@ pub mod UQADD_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQADD_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn UQADD_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -426,6 +774,30 @@ pub mod UQSUB_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSUB_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn UQSUB_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -453,6 +825,24 @@ pub mod CMHI_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMHI_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CMHI_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -477,6 +867,24 @@ pub mod CMHS_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMHS_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CMHS_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -501,6 +909,24 @@ pub mod USHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn USHL_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -525,6 +951,30 @@ pub mod UQSHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn UQSHL_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -552,6 +1002,24 @@ pub mod URSHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URSHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn URSHL_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -576,6 +1044,30 @@ pub mod UQRSHL_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQRSHL_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn UQRSHL_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -603,6 +1095,24 @@ pub mod SUB_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SUB_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -627,6 +1137,24 @@ pub mod CMEQ_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMEQ_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn CMEQ_asisdsame_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -651,6 +1179,30 @@ pub mod SQRDMULH_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMULH_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQRDMULH_asisdsame_only( size: ::aarchmrs_types::BitValue<2>, @@ -678,6 +1230,30 @@ pub mod FCMGE_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGE_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -705,6 +1281,30 @@ pub mod FACGE_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGE_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FACGE_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -732,6 +1332,30 @@ pub mod FABD_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABD_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FABD_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -759,6 +1383,30 @@ pub mod FCMGT_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FCMGT_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, @@ -786,6 +1434,30 @@ pub mod FACGT_asisdsame_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGT_asisdsame_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn FACGT_asisdsame_only( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdsame2.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdsame2.rs index df4506b8..92e1c43a 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdsame2.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdsame2.rs @@ -12,6 +12,30 @@ pub mod SQRDMLAH_asisdsame2_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLAH_asisdsame2_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQRDMLAH_asisdsame2_only( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod SQRDMLSH_asisdsame2_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRDMLSH_asisdsame2_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn SQRDMLSH_asisdsame2_only( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdsamefp16.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdsamefp16.rs index 89a7915e..eb582682 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdsamefp16.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdsamefp16.rs @@ -12,6 +12,24 @@ pub mod FMULX_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMULX_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMULX_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod FCMEQ_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMEQ_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMEQ_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod FRECPS_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRECPS_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FRECPS_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod FRSQRTS_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRSQRTS_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FRSQRTS_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod FCMGE_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGE_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMGE_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod FACGE_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGE_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FACGE_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod FABD_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABD_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FABD_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod FCMGT_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMGT_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMGT_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod FACGT_asisdsamefp16_only { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FACGT_asisdsamefp16_only"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FACGT_asisdsamefp16_only( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/asisdshf.rs b/aarchmrs-instructions/src/A64/simd_dp/asisdshf.rs index 1ecee05f..d0059cb1 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/asisdshf.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/asisdshf.rs @@ -12,6 +12,30 @@ pub mod SSHR_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSHR_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn SSHR_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -38,6 +62,30 @@ pub mod SSRA_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSRA_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn SSRA_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -64,6 +112,30 @@ pub mod SRSHR_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSHR_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn SRSHR_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -90,6 +162,30 @@ pub mod SRSRA_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRSRA_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn SRSRA_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -116,6 +212,30 @@ pub mod SHL_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHL_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn SHL_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -142,6 +262,30 @@ pub mod SQSHL_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHL_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn SQSHL_asisdshf_R( immh: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod SQSHRN_asisdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHRN_asisdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn SQSHRN_asisdshf_N( immh: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod SQRSHRN_asisdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRSHRN_asisdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn SQRSHRN_asisdshf_N( immh: ::aarchmrs_types::BitValue<4>, @@ -220,6 +412,30 @@ pub mod SCVTF_asisdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_asisdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn SCVTF_asisdshf_C( immh: ::aarchmrs_types::BitValue<4>, @@ -246,6 +462,30 @@ pub mod FCVTZS_asisdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_asisdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn FCVTZS_asisdshf_C( immh: ::aarchmrs_types::BitValue<4>, @@ -272,6 +512,30 @@ pub mod USHR_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USHR_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn USHR_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -298,6 +562,30 @@ pub mod USRA_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USRA_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn USRA_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -324,6 +612,30 @@ pub mod URSHR_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URSHR_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn URSHR_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -350,6 +662,30 @@ pub mod URSRA_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "URSRA_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn URSRA_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -376,6 +712,30 @@ pub mod SRI_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRI_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn SRI_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -402,6 +762,30 @@ pub mod SLI_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SLI_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 3u32; #[inline] pub const fn SLI_asisdshf_R( immh: ::aarchmrs_types::BitValue<3>, @@ -428,6 +812,30 @@ pub mod SQSHLU_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHLU_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn SQSHLU_asisdshf_R( immh: ::aarchmrs_types::BitValue<4>, @@ -454,6 +862,30 @@ pub mod UQSHL_asisdshf_R { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSHL_asisdshf_R"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn UQSHL_asisdshf_R( immh: ::aarchmrs_types::BitValue<4>, @@ -480,6 +912,30 @@ pub mod SQSHRUN_asisdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQSHRUN_asisdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn SQSHRUN_asisdshf_N( immh: ::aarchmrs_types::BitValue<4>, @@ -506,6 +962,30 @@ pub mod SQRSHRUN_asisdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SQRSHRUN_asisdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn SQRSHRUN_asisdshf_N( immh: ::aarchmrs_types::BitValue<4>, @@ -532,6 +1012,30 @@ pub mod UQSHRN_asisdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSHRN_asisdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn UQSHRN_asisdshf_N( immh: ::aarchmrs_types::BitValue<4>, @@ -558,6 +1062,30 @@ pub mod UQRSHRN_asisdshf_N { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQRSHRN_asisdshf_N"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn UQRSHRN_asisdshf_N( immh: ::aarchmrs_types::BitValue<4>, @@ -584,6 +1112,30 @@ pub mod UCVTF_asisdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_asisdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn UCVTF_asisdshf_C( immh: ::aarchmrs_types::BitValue<4>, @@ -610,6 +1162,30 @@ pub mod FCVTZU_asisdshf_C { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_asisdshf_C"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immb_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_immh_WIDTH: u32 = 4u32; #[inline] pub const fn FCVTZU_asisdshf_C( immh: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm2.rs b/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm2.rs index 3618de01..7dca48e4 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm2.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm2.rs @@ -12,6 +12,30 @@ pub mod SM3TT1A_VVV4_crypto3_imm2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM3TT1A_VVV4_crypto3_imm2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM3TT1A_VVV4_crypto3_imm2( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod SM3TT1B_VVV4_crypto3_imm2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM3TT1B_VVV4_crypto3_imm2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM3TT1B_VVV4_crypto3_imm2( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod SM3TT2A_VVV4_crypto3_imm2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM3TT2A_VVV4_crypto3_imm2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM3TT2A_VVV4_crypto3_imm2( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod SM3TT2B_VVV_crypto3_imm2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM3TT2B_VVV_crypto3_imm2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM3TT2B_VVV_crypto3_imm2( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm6.rs b/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm6.rs index 1697ed99..682c5c9b 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm6.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/crypto3_imm6.rs @@ -12,6 +12,30 @@ pub mod XAR_VVV2_crypto3_imm6 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "XAR_VVV2_crypto3_imm6"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn XAR_VVV2_crypto3_imm6( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/crypto4.rs b/aarchmrs-instructions/src/A64/simd_dp/crypto4.rs index 7caa39b8..78778440 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/crypto4.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/crypto4.rs @@ -12,6 +12,30 @@ pub mod EOR3_VVV16_crypto4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR3_VVV16_crypto4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn EOR3_VVV16_crypto4( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod BCAX_VVV16_crypto4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BCAX_VVV16_crypto4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn BCAX_VVV16_crypto4( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod SM3SS1_VVV4_crypto4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM3SS1_VVV4_crypto4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM3SS1_VVV4_crypto4( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/cryptoaes.rs b/aarchmrs-instructions/src/A64/simd_dp/cryptoaes.rs index 24e6dd7c..24ad71c0 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/cryptoaes.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/cryptoaes.rs @@ -12,6 +12,18 @@ pub mod AESE_B_cryptoaes { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESE_B_cryptoaes"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AESE_B_cryptoaes( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod AESD_B_cryptoaes { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESD_B_cryptoaes"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AESD_B_cryptoaes( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod AESMC_B_cryptoaes { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESMC_B_cryptoaes"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AESMC_B_cryptoaes( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod AESIMC_B_cryptoaes { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESIMC_B_cryptoaes"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn AESIMC_B_cryptoaes( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/cryptosha2.rs b/aarchmrs-instructions/src/A64/simd_dp/cryptosha2.rs index 5ea2b50c..f9d62c13 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/cryptosha2.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/cryptosha2.rs @@ -12,6 +12,18 @@ pub mod SHA1H_SS_cryptosha2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1H_SS_cryptosha2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SHA1H_SS_cryptosha2( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod SHA1SU1_VV_cryptosha2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1SU1_VV_cryptosha2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SHA1SU1_VV_cryptosha2( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod SHA256SU0_VV_cryptosha2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256SU0_VV_cryptosha2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SHA256SU0_VV_cryptosha2( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/cryptosha3.rs b/aarchmrs-instructions/src/A64/simd_dp/cryptosha3.rs index 8dc53304..c6892162 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/cryptosha3.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/cryptosha3.rs @@ -12,6 +12,24 @@ pub mod SHA1C_QSV_cryptosha3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1C_QSV_cryptosha3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA1C_QSV_cryptosha3( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod SHA1P_QSV_cryptosha3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1P_QSV_cryptosha3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA1P_QSV_cryptosha3( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod SHA1M_QSV_cryptosha3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1M_QSV_cryptosha3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA1M_QSV_cryptosha3( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod SHA1SU0_VVV_cryptosha3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1SU0_VVV_cryptosha3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA1SU0_VVV_cryptosha3( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod SHA256H_QQV_cryptosha3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256H_QQV_cryptosha3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA256H_QQV_cryptosha3( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod SHA256H2_QQV_cryptosha3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256H2_QQV_cryptosha3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA256H2_QQV_cryptosha3( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod SHA256SU1_VVV_cryptosha3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256SU1_VVV_cryptosha3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA256SU1_VVV_cryptosha3( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_2.rs b/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_2.rs index 7c92b3e1..e13cab53 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_2.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_2.rs @@ -12,6 +12,18 @@ pub mod SHA512SU0_VV2_cryptosha512_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA512SU0_VV2_cryptosha512_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SHA512SU0_VV2_cryptosha512_2( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod SM4E_VV4_cryptosha512_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM4E_VV4_cryptosha512_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SM4E_VV4_cryptosha512_2( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_3.rs b/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_3.rs index b63e034e..ec45ac68 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_3.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/cryptosha512_3.rs @@ -12,6 +12,24 @@ pub mod SHA512H_QQV_cryptosha512_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA512H_QQV_cryptosha512_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA512H_QQV_cryptosha512_3( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod SHA512H2_QQV_cryptosha512_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA512H2_QQV_cryptosha512_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA512H2_QQV_cryptosha512_3( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod SHA512SU1_VVV2_cryptosha512_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA512SU1_VVV2_cryptosha512_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SHA512SU1_VVV2_cryptosha512_3( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod RAX1_VVV2_cryptosha512_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RAX1_VVV2_cryptosha512_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn RAX1_VVV2_cryptosha512_3( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod SM3PARTW1_VVV4_cryptosha512_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM3PARTW1_VVV4_cryptosha512_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM3PARTW1_VVV4_cryptosha512_3( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod SM3PARTW2_VVV4_cryptosha512_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM3PARTW2_VVV4_cryptosha512_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM3PARTW2_VVV4_cryptosha512_3( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod SM4EKEY_VVV4_cryptosha512_3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SM4EKEY_VVV4_cryptosha512_3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn SM4EKEY_VVV4_cryptosha512_3( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/float2fix.rs b/aarchmrs-instructions/src/A64/simd_dp/float2fix.rs index cf4144f5..26489a18 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/float2fix.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/float2fix.rs @@ -12,6 +12,24 @@ pub mod SCVTF_S32_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_S32_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn SCVTF_S32_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -35,6 +53,24 @@ pub mod UCVTF_S32_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_S32_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn UCVTF_S32_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -58,6 +94,24 @@ pub mod FCVTZS_32S_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_32S_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZS_32S_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -81,6 +135,24 @@ pub mod FCVTZU_32S_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_32S_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZU_32S_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -104,6 +176,24 @@ pub mod SCVTF_D32_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_D32_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn SCVTF_D32_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -127,6 +217,24 @@ pub mod UCVTF_D32_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_D32_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn UCVTF_D32_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -150,6 +258,24 @@ pub mod FCVTZS_32D_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_32D_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZS_32D_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -173,6 +299,24 @@ pub mod FCVTZU_32D_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_32D_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZU_32D_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -196,6 +340,24 @@ pub mod SCVTF_H32_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_H32_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn SCVTF_H32_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -219,6 +381,24 @@ pub mod UCVTF_H32_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_H32_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn UCVTF_H32_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -242,6 +422,24 @@ pub mod FCVTZS_32H_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_32H_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZS_32H_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -265,6 +463,24 @@ pub mod FCVTZU_32H_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_32H_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZU_32H_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -288,6 +504,24 @@ pub mod SCVTF_S64_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_S64_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn SCVTF_S64_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -311,6 +545,24 @@ pub mod UCVTF_S64_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_S64_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn UCVTF_S64_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -334,6 +586,24 @@ pub mod FCVTZS_64S_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_64S_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZS_64S_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -357,6 +627,24 @@ pub mod FCVTZU_64S_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_64S_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZU_64S_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -380,6 +668,24 @@ pub mod SCVTF_D64_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_D64_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn SCVTF_D64_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -403,6 +709,24 @@ pub mod UCVTF_D64_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_D64_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn UCVTF_D64_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -426,6 +750,24 @@ pub mod FCVTZS_64D_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_64D_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZS_64D_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -449,6 +791,24 @@ pub mod FCVTZU_64D_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_64D_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZU_64D_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -472,6 +832,24 @@ pub mod SCVTF_H64_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_H64_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn SCVTF_H64_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -495,6 +873,24 @@ pub mod UCVTF_H64_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_H64_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn UCVTF_H64_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -518,6 +914,24 @@ pub mod FCVTZS_64H_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_64H_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZS_64H_float2fix( scale: ::aarchmrs_types::BitValue<6>, @@ -541,6 +955,24 @@ pub mod FCVTZU_64H_float2fix { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_64H_float2fix"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_scale_WIDTH: u32 = 6u32; #[inline] pub const fn FCVTZU_64H_float2fix( scale: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/float2int.rs b/aarchmrs-instructions/src/A64/simd_dp/float2int.rs index 1eb24520..e296a785 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/float2int.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/float2int.rs @@ -12,6 +12,18 @@ pub mod FCVTNS_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod FCVTNU_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod SCVTF_S32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_S32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_S32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod UCVTF_S32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_S32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_S32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -96,6 +144,18 @@ pub mod FCVTAS_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -117,6 +177,18 @@ pub mod FCVTAU_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +210,18 @@ pub mod FMOV_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -159,6 +243,18 @@ pub mod FMOV_S32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_S32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_S32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -180,6 +276,18 @@ pub mod FCVTPS_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -201,6 +309,18 @@ pub mod FCVTPU_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -222,6 +342,18 @@ pub mod FCVTMS_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -243,6 +375,18 @@ pub mod FCVTMU_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -264,6 +408,18 @@ pub mod FCVTZS_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -285,6 +441,18 @@ pub mod FCVTZU_32S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_32S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_32S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -306,6 +474,18 @@ pub mod FCVTNS_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -327,6 +507,18 @@ pub mod FCVTNU_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -348,6 +540,18 @@ pub mod SCVTF_D32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_D32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_D32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -369,6 +573,18 @@ pub mod UCVTF_D32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_D32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_D32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -390,6 +606,18 @@ pub mod FCVTAS_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -411,6 +639,18 @@ pub mod FCVTAU_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -432,6 +672,18 @@ pub mod FCVTPS_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -453,6 +705,18 @@ pub mod FCVTPU_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -474,6 +738,18 @@ pub mod FCVTMS_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -495,6 +771,18 @@ pub mod FCVTMU_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -516,6 +804,18 @@ pub mod FCVTZS_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -537,6 +837,18 @@ pub mod FCVTZU_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -558,6 +870,18 @@ pub mod FJCVTZS_32D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FJCVTZS_32D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FJCVTZS_32D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -579,6 +903,18 @@ pub mod FCVTNS_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -600,6 +936,18 @@ pub mod FCVTNU_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -621,6 +969,18 @@ pub mod SCVTF_H32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_H32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_H32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -642,6 +1002,18 @@ pub mod UCVTF_H32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_H32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_H32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -663,6 +1035,18 @@ pub mod FCVTAS_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -684,6 +1068,18 @@ pub mod FCVTAU_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -705,6 +1101,18 @@ pub mod FMOV_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -726,6 +1134,18 @@ pub mod FMOV_H32_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_H32_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_H32_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -747,6 +1167,18 @@ pub mod FCVTPS_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -768,6 +1200,18 @@ pub mod FCVTPU_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -789,6 +1233,18 @@ pub mod FCVTMS_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -810,6 +1266,18 @@ pub mod FCVTMU_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -831,6 +1299,18 @@ pub mod FCVTZS_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -852,6 +1332,18 @@ pub mod FCVTZU_32H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_32H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_32H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -873,6 +1365,18 @@ pub mod FCVTNS_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -894,6 +1398,18 @@ pub mod FCVTNU_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -915,6 +1431,18 @@ pub mod SCVTF_S64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_S64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_S64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -936,6 +1464,18 @@ pub mod UCVTF_S64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_S64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_S64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -957,6 +1497,18 @@ pub mod FCVTAS_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -978,6 +1530,18 @@ pub mod FCVTAU_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -999,6 +1563,18 @@ pub mod FCVTPS_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1020,6 +1596,18 @@ pub mod FCVTPU_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1041,6 +1629,18 @@ pub mod FCVTMS_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1062,6 +1662,18 @@ pub mod FCVTMU_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1083,6 +1695,18 @@ pub mod FCVTZS_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1104,6 +1728,18 @@ pub mod FCVTZU_64S_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_64S_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_64S_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1125,6 +1761,18 @@ pub mod FCVTNS_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1146,6 +1794,18 @@ pub mod FCVTNU_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1167,6 +1827,18 @@ pub mod SCVTF_D64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_D64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_D64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1188,6 +1860,18 @@ pub mod UCVTF_D64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_D64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_D64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1209,6 +1893,18 @@ pub mod FCVTAS_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1230,6 +1926,18 @@ pub mod FCVTAU_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1251,6 +1959,18 @@ pub mod FMOV_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1272,6 +1992,18 @@ pub mod FMOV_D64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_D64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_D64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1293,6 +2025,18 @@ pub mod FCVTPS_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1314,6 +2058,18 @@ pub mod FCVTPU_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1335,6 +2091,18 @@ pub mod FCVTMS_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1356,6 +2124,18 @@ pub mod FCVTMU_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1377,6 +2157,18 @@ pub mod FCVTZS_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1398,6 +2190,18 @@ pub mod FCVTZU_64D_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_64D_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_64D_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1419,6 +2223,18 @@ pub mod FMOV_64VX_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_64VX_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_64VX_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1440,6 +2256,18 @@ pub mod FMOV_V64I_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_V64I_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_V64I_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1461,6 +2289,18 @@ pub mod FCVTNS_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1482,6 +2322,18 @@ pub mod FCVTNU_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1503,6 +2355,18 @@ pub mod SCVTF_H64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_H64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_H64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1524,6 +2388,18 @@ pub mod UCVTF_H64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_H64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_H64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1545,6 +2421,18 @@ pub mod FCVTAS_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1566,6 +2454,18 @@ pub mod FCVTAU_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1587,6 +2487,18 @@ pub mod FMOV_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1608,6 +2520,18 @@ pub mod FMOV_H64_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_H64_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_H64_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1629,6 +2553,18 @@ pub mod FCVTPS_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1650,6 +2586,18 @@ pub mod FCVTPU_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1671,6 +2619,18 @@ pub mod FCVTMS_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1692,6 +2652,18 @@ pub mod FCVTMU_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1713,6 +2685,18 @@ pub mod FCVTZS_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1734,6 +2718,18 @@ pub mod FCVTZU_64H_float2int { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_64H_float2int"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_64H_float2int( Rn: ::aarchmrs_types::BitValue<5>, @@ -1755,6 +2751,18 @@ pub mod FCVTNS_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1776,6 +2784,18 @@ pub mod FCVTAS_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1797,6 +2817,18 @@ pub mod FCVTPS_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1818,6 +2850,18 @@ pub mod FCVTMS_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1839,6 +2883,18 @@ pub mod FCVTZS_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1860,6 +2916,18 @@ pub mod SCVTF_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1881,6 +2949,18 @@ pub mod FCVTNU_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1902,6 +2982,18 @@ pub mod FCVTAU_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1923,6 +3015,18 @@ pub mod FCVTPU_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1944,6 +3048,18 @@ pub mod FCVTMU_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1965,6 +3081,18 @@ pub mod FCVTZU_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -1986,6 +3114,18 @@ pub mod UCVTF_sisd_32D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_sisd_32D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_sisd_32D( Rn: ::aarchmrs_types::BitValue<5>, @@ -2007,6 +3147,18 @@ pub mod FCVTNS_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2028,6 +3180,18 @@ pub mod FCVTAS_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2049,6 +3213,18 @@ pub mod FCVTPS_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2070,6 +3246,18 @@ pub mod FCVTMS_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2091,6 +3279,18 @@ pub mod FCVTZS_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2112,6 +3312,18 @@ pub mod SCVTF_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2133,6 +3345,18 @@ pub mod FCVTNU_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2154,6 +3378,18 @@ pub mod FCVTAU_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2175,6 +3411,18 @@ pub mod FCVTPU_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2196,6 +3444,18 @@ pub mod FCVTMU_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2217,6 +3477,18 @@ pub mod FCVTZU_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2238,6 +3510,18 @@ pub mod UCVTF_sisd_32H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_sisd_32H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_sisd_32H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2259,6 +3543,18 @@ pub mod FCVTNS_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2280,6 +3576,18 @@ pub mod FCVTAS_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2301,6 +3609,18 @@ pub mod FCVTPS_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2322,6 +3642,18 @@ pub mod FCVTMS_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2343,6 +3675,18 @@ pub mod FCVTZS_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2364,6 +3708,18 @@ pub mod SCVTF_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2385,6 +3741,18 @@ pub mod FCVTNU_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2406,6 +3774,18 @@ pub mod FCVTAU_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2427,6 +3807,18 @@ pub mod FCVTPU_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2448,6 +3840,18 @@ pub mod FCVTMU_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2469,6 +3873,18 @@ pub mod FCVTZU_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2490,6 +3906,18 @@ pub mod UCVTF_sisd_64H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_sisd_64H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_sisd_64H( Rn: ::aarchmrs_types::BitValue<5>, @@ -2511,6 +3939,18 @@ pub mod FCVTNS_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNS_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNS_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2532,6 +3972,18 @@ pub mod FCVTAS_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAS_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAS_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2553,6 +4005,18 @@ pub mod FCVTPS_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPS_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPS_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2574,6 +4038,18 @@ pub mod FCVTMS_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMS_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMS_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2595,6 +4071,18 @@ pub mod FCVTZS_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZS_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZS_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2616,6 +4104,18 @@ pub mod SCVTF_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SCVTF_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn SCVTF_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2637,6 +4137,18 @@ pub mod FCVTNU_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTNU_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTNU_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2658,6 +4170,18 @@ pub mod FCVTAU_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTAU_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTAU_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2679,6 +4203,18 @@ pub mod FCVTPU_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTPU_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTPU_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2700,6 +4236,18 @@ pub mod FCVTMU_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTMU_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTMU_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2721,6 +4269,18 @@ pub mod FCVTZU_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVTZU_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVTZU_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, @@ -2742,6 +4302,18 @@ pub mod UCVTF_sisd_64S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UCVTF_sisd_64S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn UCVTF_sisd_64S( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/floatccmp.rs b/aarchmrs-instructions/src/A64/simd_dp/floatccmp.rs index 3b32d58e..164f4a22 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/floatccmp.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/floatccmp.rs @@ -12,6 +12,30 @@ pub mod FCCMP_S_floatccmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCCMP_S_floatccmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCCMP_S_floatccmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod FCCMPE_S_floatccmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCCMPE_S_floatccmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCCMPE_S_floatccmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod FCCMP_D_floatccmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCCMP_D_floatccmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCCMP_D_floatccmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod FCCMPE_D_floatccmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCCMPE_D_floatccmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCCMPE_D_floatccmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -120,6 +216,30 @@ pub mod FCCMP_H_floatccmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCCMP_H_floatccmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCCMP_H_floatccmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -147,6 +267,30 @@ pub mod FCCMPE_H_floatccmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCCMPE_H_floatccmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_nzcv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCCMPE_H_floatccmp( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/floatcmp.rs b/aarchmrs-instructions/src/A64/simd_dp/floatcmp.rs index ec0d81f9..d3e0f72d 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/floatcmp.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/floatcmp.rs @@ -12,6 +12,18 @@ pub mod FCMP_S_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMP_S_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMP_S_floatcmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -35,6 +47,12 @@ pub mod FCMP_SZ_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMP_SZ_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMP_SZ_floatcmp( Rn: ::aarchmrs_types::BitValue<5>, @@ -53,6 +71,18 @@ pub mod FCMPE_S_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMPE_S_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMPE_S_floatcmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -76,6 +106,12 @@ pub mod FCMPE_SZ_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMPE_SZ_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMPE_SZ_floatcmp( Rn: ::aarchmrs_types::BitValue<5>, @@ -94,6 +130,18 @@ pub mod FCMP_D_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMP_D_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMP_D_floatcmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -117,6 +165,12 @@ pub mod FCMP_DZ_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMP_DZ_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMP_DZ_floatcmp( Rn: ::aarchmrs_types::BitValue<5>, @@ -135,6 +189,18 @@ pub mod FCMPE_D_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMPE_D_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMPE_D_floatcmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -158,6 +224,12 @@ pub mod FCMPE_DZ_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMPE_DZ_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMPE_DZ_floatcmp( Rn: ::aarchmrs_types::BitValue<5>, @@ -176,6 +248,18 @@ pub mod FCMP_H_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMP_H_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMP_H_floatcmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -199,6 +283,12 @@ pub mod FCMP_HZ_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMP_HZ_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMP_HZ_floatcmp( Rn: ::aarchmrs_types::BitValue<5>, @@ -217,6 +307,18 @@ pub mod FCMPE_H_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMPE_H_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCMPE_H_floatcmp( Rm: ::aarchmrs_types::BitValue<5>, @@ -240,6 +342,12 @@ pub mod FCMPE_HZ_floatcmp { pub const SHOULD_BE_MASK: u32 = 0b00000000000111110000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCMPE_HZ_floatcmp"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCMPE_HZ_floatcmp( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/floatdp1.rs b/aarchmrs-instructions/src/A64/simd_dp/floatdp1.rs index 9c4fe7d5..00576998 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/floatdp1.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/floatdp1.rs @@ -12,6 +12,18 @@ pub mod FMOV_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod FABS_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABS_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FABS_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod FNEG_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNEG_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FNEG_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod FSQRT_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSQRT_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FSQRT_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -96,6 +144,18 @@ pub mod FCVT_DS_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVT_DS_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVT_DS_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -117,6 +177,18 @@ pub mod FCVT_HS_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVT_HS_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVT_HS_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +210,18 @@ pub mod FRINTN_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTN_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTN_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -159,6 +243,18 @@ pub mod FRINTP_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTP_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTP_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -180,6 +276,18 @@ pub mod FRINTM_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTM_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTM_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -201,6 +309,18 @@ pub mod FRINTZ_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTZ_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTZ_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -222,6 +342,18 @@ pub mod FRINTA_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTA_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTA_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -243,6 +375,18 @@ pub mod FRINTX_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTX_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTX_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -264,6 +408,18 @@ pub mod FRINTI_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTI_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTI_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -285,6 +441,18 @@ pub mod FRINT32Z_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT32Z_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT32Z_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -306,6 +474,18 @@ pub mod FRINT32X_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT32X_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT32X_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -327,6 +507,18 @@ pub mod FRINT64Z_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT64Z_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT64Z_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -348,6 +540,18 @@ pub mod FRINT64X_S_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT64X_S_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT64X_S_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -369,6 +573,18 @@ pub mod FMOV_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -390,6 +606,18 @@ pub mod FABS_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABS_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FABS_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -411,6 +639,18 @@ pub mod FNEG_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNEG_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FNEG_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -432,6 +672,18 @@ pub mod FSQRT_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSQRT_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FSQRT_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -453,6 +705,18 @@ pub mod FCVT_SD_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVT_SD_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVT_SD_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -474,6 +738,18 @@ pub mod BFCVT_BS_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFCVT_BS_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn BFCVT_BS_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -495,6 +771,18 @@ pub mod FCVT_HD_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVT_HD_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVT_HD_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -516,6 +804,18 @@ pub mod FRINTN_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTN_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTN_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -537,6 +837,18 @@ pub mod FRINTP_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTP_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTP_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -558,6 +870,18 @@ pub mod FRINTM_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTM_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTM_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -579,6 +903,18 @@ pub mod FRINTZ_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTZ_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTZ_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -600,6 +936,18 @@ pub mod FRINTA_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTA_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTA_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -621,6 +969,18 @@ pub mod FRINTX_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTX_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTX_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -642,6 +1002,18 @@ pub mod FRINTI_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTI_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTI_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -663,6 +1035,18 @@ pub mod FRINT32Z_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT32Z_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT32Z_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -684,6 +1068,18 @@ pub mod FRINT32X_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT32X_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT32X_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -705,6 +1101,18 @@ pub mod FRINT64Z_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT64Z_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT64Z_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -726,6 +1134,18 @@ pub mod FRINT64X_D_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINT64X_D_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINT64X_D_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -747,6 +1167,18 @@ pub mod FMOV_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FMOV_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -768,6 +1200,18 @@ pub mod FABS_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FABS_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FABS_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -789,6 +1233,18 @@ pub mod FNEG_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNEG_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FNEG_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -810,6 +1266,18 @@ pub mod FSQRT_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSQRT_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FSQRT_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -831,6 +1299,18 @@ pub mod FCVT_SH_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVT_SH_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVT_SH_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -852,6 +1332,18 @@ pub mod FCVT_DH_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCVT_DH_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FCVT_DH_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -873,6 +1365,18 @@ pub mod FRINTN_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTN_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTN_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -894,6 +1398,18 @@ pub mod FRINTP_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTP_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTP_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -915,6 +1431,18 @@ pub mod FRINTM_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTM_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTM_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -936,6 +1464,18 @@ pub mod FRINTZ_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTZ_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTZ_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -957,6 +1497,18 @@ pub mod FRINTA_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTA_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTA_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -978,6 +1530,18 @@ pub mod FRINTX_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTX_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTX_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, @@ -999,6 +1563,18 @@ pub mod FRINTI_H_floatdp1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FRINTI_H_floatdp1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn FRINTI_H_floatdp1( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/floatdp2.rs b/aarchmrs-instructions/src/A64/simd_dp/floatdp2.rs index 8a1e1607..20c1067b 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/floatdp2.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/floatdp2.rs @@ -12,6 +12,24 @@ pub mod FMUL_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMUL_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod FDIV_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDIV_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FDIV_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod FADD_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADD_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FADD_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod FSUB_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSUB_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FSUB_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod FMAX_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAX_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMAX_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod FMIN_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMIN_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMIN_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod FMAXNM_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNM_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMAXNM_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod FMINNM_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNM_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMINNM_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -204,6 +348,24 @@ pub mod FNMUL_S_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMUL_S_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMUL_S_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -228,6 +390,24 @@ pub mod FMUL_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMUL_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -252,6 +432,24 @@ pub mod FDIV_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDIV_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FDIV_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -276,6 +474,24 @@ pub mod FADD_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADD_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FADD_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -300,6 +516,24 @@ pub mod FSUB_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSUB_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FSUB_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -324,6 +558,24 @@ pub mod FMAX_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAX_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMAX_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -348,6 +600,24 @@ pub mod FMIN_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMIN_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMIN_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -372,6 +642,24 @@ pub mod FMAXNM_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNM_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMAXNM_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -396,6 +684,24 @@ pub mod FMINNM_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNM_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMINNM_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -420,6 +726,24 @@ pub mod FNMUL_D_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMUL_D_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMUL_D_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -444,6 +768,24 @@ pub mod FMUL_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMUL_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMUL_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -468,6 +810,24 @@ pub mod FDIV_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FDIV_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FDIV_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -492,6 +852,24 @@ pub mod FADD_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FADD_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FADD_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -516,6 +894,24 @@ pub mod FSUB_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSUB_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FSUB_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -540,6 +936,24 @@ pub mod FMAX_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAX_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMAX_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -564,6 +978,24 @@ pub mod FMIN_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMIN_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMIN_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -588,6 +1020,24 @@ pub mod FMAXNM_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMAXNM_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMAXNM_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -612,6 +1062,24 @@ pub mod FMINNM_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMINNM_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMINNM_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, @@ -636,6 +1104,24 @@ pub mod FNMUL_H_floatdp2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMUL_H_floatdp2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMUL_H_floatdp2( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/floatdp3.rs b/aarchmrs-instructions/src/A64/simd_dp/floatdp3.rs index 24599fff..8614cf9d 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/floatdp3.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/floatdp3.rs @@ -12,6 +12,30 @@ pub mod FMADD_S_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMADD_S_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMADD_S_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod FMSUB_S_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMSUB_S_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMSUB_S_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod FNMADD_S_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMADD_S_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMADD_S_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod FNMSUB_S_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMSUB_S_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMSUB_S_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod FMADD_D_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMADD_D_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMADD_D_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod FMSUB_D_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMSUB_D_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMSUB_D_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod FNMADD_D_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMADD_D_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMADD_D_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod FNMSUB_D_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMSUB_D_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMSUB_D_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod FMADD_H_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMADD_H_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMADD_H_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod FMSUB_H_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMSUB_H_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FMSUB_H_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -272,6 +512,30 @@ pub mod FNMADD_H_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMADD_H_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMADD_H_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, @@ -298,6 +562,30 @@ pub mod FNMSUB_H_floatdp3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FNMSUB_H_floatdp3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FNMSUB_H_floatdp3( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/floatimm.rs b/aarchmrs-instructions/src/A64/simd_dp/floatimm.rs index cfca561b..062df623 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/floatimm.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/floatimm.rs @@ -12,6 +12,18 @@ pub mod FMOV_S_floatimm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_S_floatimm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn FMOV_S_floatimm( imm8: ::aarchmrs_types::BitValue<8>, @@ -34,6 +46,18 @@ pub mod FMOV_D_floatimm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_D_floatimm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn FMOV_D_floatimm( imm8: ::aarchmrs_types::BitValue<8>, @@ -56,6 +80,18 @@ pub mod FMOV_H_floatimm { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FMOV_H_floatimm"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn FMOV_H_floatimm( imm8: ::aarchmrs_types::BitValue<8>, diff --git a/aarchmrs-instructions/src/A64/simd_dp/floatsel.rs b/aarchmrs-instructions/src/A64/simd_dp/floatsel.rs index 1502d874..1ff22b75 100644 --- a/aarchmrs-instructions/src/A64/simd_dp/floatsel.rs +++ b/aarchmrs-instructions/src/A64/simd_dp/floatsel.rs @@ -12,6 +12,30 @@ pub mod FCSEL_S_floatsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCSEL_S_floatsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCSEL_S_floatsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod FCSEL_D_floatsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCSEL_D_floatsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCSEL_D_floatsel( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod FCSEL_H_floatsel { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FCSEL_H_floatsel"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn FCSEL_H_floatsel( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_f64f64_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_f64f64_prod4.rs index d3948a1e..4a72c9cc 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_f64f64_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_f64f64_prod4.rs @@ -12,6 +12,24 @@ pub mod fmop4a_za_zz_d1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_d1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_d1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod fmop4s_za_zz_d1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_d1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_d1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod fmop4a_za_zz_d1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_d1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_d1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod fmop4s_za_zz_d1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_d1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_d1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod fmop4a_za_zz_d2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_d2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_d2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod fmop4s_za_zz_d2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_d2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_d2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod fmop4a_za_zz_d2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_d2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_d2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod fmop4s_za_zz_d2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_d2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_d2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_i16i64_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_i16i64_prod4.rs index 9e1d53c4..cb61b7ce 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_i16i64_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_64bit_prod4/mortlach_i16i64_prod4.rs @@ -12,6 +12,24 @@ pub mod smop4a_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod sumop4a_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod usmop4a_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod umop4a_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod smop4s_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod sumop4s_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod usmop4s_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod umop4s_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -212,6 +356,24 @@ pub mod smop4a_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -237,6 +399,24 @@ pub mod sumop4a_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -262,6 +442,24 @@ pub mod usmop4a_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -287,6 +485,24 @@ pub mod umop4a_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -312,6 +528,24 @@ pub mod smop4s_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -337,6 +571,24 @@ pub mod sumop4s_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -362,6 +614,24 @@ pub mod usmop4s_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -387,6 +657,24 @@ pub mod umop4s_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -412,6 +700,24 @@ pub mod smop4a_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -437,6 +743,24 @@ pub mod sumop4a_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -462,6 +786,24 @@ pub mod usmop4a_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -487,6 +829,24 @@ pub mod umop4a_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -512,6 +872,24 @@ pub mod smop4s_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -537,6 +915,24 @@ pub mod sumop4s_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -562,6 +958,24 @@ pub mod usmop4s_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -587,6 +1001,24 @@ pub mod umop4s_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -612,6 +1044,24 @@ pub mod smop4a_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -637,6 +1087,24 @@ pub mod sumop4a_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -662,6 +1130,24 @@ pub mod usmop4a_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -687,6 +1173,24 @@ pub mod umop4a_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -712,6 +1216,24 @@ pub mod smop4s_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -737,6 +1259,24 @@ pub mod sumop4s_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -762,6 +1302,24 @@ pub mod usmop4s_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -787,6 +1345,24 @@ pub mod umop4s_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_b16b16_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_b16b16_prod.rs index c6d624d5..fccf4fc9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_b16b16_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_b16b16_prod.rs @@ -12,6 +12,36 @@ pub mod bfmopa_za_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmopa_za_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmopa_za_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod bfmops_za_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmops_za_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmops_za_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_bini32_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_bini32_prod.rs index 722dff76..7c0f5b5a 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_bini32_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_bini32_prod.rs @@ -12,6 +12,36 @@ pub mod bmopa_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bmopa_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bmopa_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod bmops_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bmops_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bmops_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f16f16_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f16f16_prod.rs index a09d0551..34a43839 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f16f16_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f16f16_prod.rs @@ -12,6 +12,36 @@ pub mod fmopa_za_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmopa_za_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmopa_za_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod fmops_za_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmops_za_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmops_za_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f8f16_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f8f16_prod.rs index 7b9c5bd9..6a3ff994 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f8f16_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_misc_prod/mortlach_f8f16_prod.rs @@ -12,6 +12,36 @@ pub mod fmopa_za16_pp_z8z8_8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmopa_za16_pp_z8z8_8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmopa_za16_pp_z8z8_8( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16b16_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16b16_prod4.rs index c88650a4..5c4910c4 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16b16_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16b16_prod4.rs @@ -12,6 +12,24 @@ pub mod bfmop4a_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod bfmop4s_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod bfmop4a_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod bfmop4s_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod bfmop4a_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod bfmop4s_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod bfmop4a_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod bfmop4s_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16f32_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16f32_prod4.rs index 94df634a..7dc5ed3f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16f32_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_b16f32_prod4.rs @@ -12,6 +12,24 @@ pub mod bfmop4a_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod bfmop4s_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod bfmop4a_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod bfmop4s_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod bfmop4a_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod bfmop4s_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod bfmop4a_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4a_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4a_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod bfmop4s_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmop4s_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmop4s_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f16_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f16_prod4.rs index 76ea5965..b497adb0 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f16_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f16_prod4.rs @@ -12,6 +12,24 @@ pub mod fmop4a_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod fmop4s_za_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod fmop4a_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod fmop4s_za_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod fmop4a_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod fmop4s_za_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod fmop4a_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod fmop4s_za_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f32_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f32_prod4.rs index cdba1a80..258051bd 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f32_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f16f32_prod4.rs @@ -12,6 +12,24 @@ pub mod fmop4a_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod fmop4s_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod fmop4a_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod fmop4s_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod fmop4a_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod fmop4s_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod fmop4a_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod fmop4s_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f32f32_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f32f32_prod4.rs index 6eb9f005..91689a86 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f32f32_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f32f32_prod4.rs @@ -12,6 +12,24 @@ pub mod fmop4a_za_zz_s1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_s1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_s1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod fmop4s_za_zz_s1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_s1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_s1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod fmop4a_za_zz_s1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_s1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_s1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod fmop4s_za_zz_s1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_s1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_s1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod fmop4a_za_zz_s2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_s2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_s2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod fmop4s_za_zz_s2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_s2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_s2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod fmop4a_za_zz_s2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za_zz_s2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za_zz_s2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod fmop4s_za_zz_s2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4s_za_zz_s2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4s_za_zz_s2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f16_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f16_prod4.rs index 4bba852c..8c697ed2 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f16_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f16_prod4.rs @@ -12,6 +12,24 @@ pub mod fmop4a_za16_z8z8_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za16_z8z8_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za16_z8z8_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod fmop4a_za16_z8z8_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za16_z8z8_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za16_z8z8_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod fmop4a_za16_z8z8_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za16_z8z8_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za16_z8z8_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod fmop4a_za16_z8z8_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za16_z8z8_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za16_z8z8_b2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f32_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f32_prod4.rs index 5aaf35ee..37135266 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f32_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_f8f32_prod4.rs @@ -12,6 +12,24 @@ pub mod fmop4a_za32_z8z8_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_z8z8_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_z8z8_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod fmop4a_za32_z8z8_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_z8z8_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_z8z8_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod fmop4a_za32_z8z8_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_z8z8_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_z8z8_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod fmop4a_za32_z8z8_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmop4a_za32_z8z8_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmop4a_za32_z8z8_b2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i16i32_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i16i32_prod4.rs index 67c03ddd..3061a9b7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i16i32_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i16i32_prod4.rs @@ -12,6 +12,24 @@ pub mod smop4a_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod umop4a_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod smop4s_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod umop4s_za32_zz_h1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za32_zz_h1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za32_zz_h1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod smop4a_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod umop4a_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod smop4s_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod umop4s_za32_zz_h1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za32_zz_h1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za32_zz_h1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -212,6 +356,24 @@ pub mod smop4a_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -237,6 +399,24 @@ pub mod umop4a_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -262,6 +442,24 @@ pub mod smop4s_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -287,6 +485,24 @@ pub mod umop4s_za32_zz_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za32_zz_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za32_zz_h2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -312,6 +528,24 @@ pub mod smop4a_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -337,6 +571,24 @@ pub mod umop4a_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -362,6 +614,24 @@ pub mod smop4s_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -387,6 +657,24 @@ pub mod umop4s_za32_zz_h2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za32_zz_h2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za32_zz_h2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i8i32_prod4.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i8i32_prod4.rs index e184ddf5..8722fdba 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i8i32_prod4.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_prod4/mortlach_i8i32_prod4.rs @@ -12,6 +12,24 @@ pub mod smop4a_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -37,6 +55,24 @@ pub mod sumop4a_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod usmop4a_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -87,6 +141,24 @@ pub mod umop4a_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,24 @@ pub mod smop4s_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -137,6 +227,24 @@ pub mod sumop4s_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -162,6 +270,24 @@ pub mod usmop4s_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -187,6 +313,24 @@ pub mod umop4s_za_zz_b1x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_b1x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_b1x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -212,6 +356,24 @@ pub mod smop4a_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -237,6 +399,24 @@ pub mod sumop4a_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -262,6 +442,24 @@ pub mod usmop4a_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -287,6 +485,24 @@ pub mod umop4a_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -312,6 +528,24 @@ pub mod smop4s_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -337,6 +571,24 @@ pub mod sumop4s_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -362,6 +614,24 @@ pub mod usmop4s_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -387,6 +657,24 @@ pub mod umop4s_za_zz_b1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_b1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_b1x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -412,6 +700,24 @@ pub mod smop4a_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -437,6 +743,24 @@ pub mod sumop4a_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -462,6 +786,24 @@ pub mod usmop4a_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -487,6 +829,24 @@ pub mod umop4a_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -512,6 +872,24 @@ pub mod smop4s_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -537,6 +915,24 @@ pub mod sumop4s_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -562,6 +958,24 @@ pub mod usmop4s_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -587,6 +1001,24 @@ pub mod umop4s_za_zz_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_b2x1( Zm: ::aarchmrs_types::BitValue<3>, @@ -612,6 +1044,24 @@ pub mod smop4a_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4a_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4a_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -637,6 +1087,24 @@ pub mod sumop4a_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4a_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4a_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -662,6 +1130,24 @@ pub mod usmop4a_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4a_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4a_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -687,6 +1173,24 @@ pub mod umop4a_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4a_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4a_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -712,6 +1216,24 @@ pub mod smop4s_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smop4s_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smop4s_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -737,6 +1259,24 @@ pub mod sumop4s_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumop4s_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sumop4s_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -762,6 +1302,24 @@ pub mod usmop4s_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmop4s_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmop4s_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, @@ -787,6 +1345,24 @@ pub mod umop4s_za_zz_b2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umop4s_za_zz_b2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umop4s_za_zz_b2x2( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16b16_1in2ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16b16_1in2ss_prod.rs index a645f644..0e101ea6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16b16_1in2ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16b16_1in2ss_prod.rs @@ -12,6 +12,42 @@ pub mod bftmopa_za_zzzi_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bftmopa_za_zzzi_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bftmopa_za_zzzi_h2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16f32_2in4ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16f32_2in4ss_prod.rs index f024089d..cd81d21e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16f32_2in4ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_b16f32_2in4ss_prod.rs @@ -12,6 +12,42 @@ pub mod bftmopa_za32_zzzi_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bftmopa_za32_zzzi_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bftmopa_za32_zzzi_h2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f16_1in2ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f16_1in2ss_prod.rs index 1731b873..0f6af89f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f16_1in2ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f16_1in2ss_prod.rs @@ -12,6 +12,42 @@ pub mod ftmopa_za_zzzi_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftmopa_za_zzzi_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ftmopa_za_zzzi_h2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f32_2in4ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f32_2in4ss_prod.rs index e6a7fb53..b84a1b42 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f32_2in4ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f16f32_2in4ss_prod.rs @@ -12,6 +12,42 @@ pub mod ftmopa_za32_zzzi_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftmopa_za32_zzzi_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ftmopa_za32_zzzi_h2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f32f32_1in2ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f32f32_1in2ss_prod.rs index 7a11ebe9..669e6143 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f32f32_1in2ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f32f32_1in2ss_prod.rs @@ -12,6 +12,42 @@ pub mod ftmopa_za_zzzi_s2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftmopa_za_zzzi_s2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ftmopa_za_zzzi_s2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f16_2in4ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f16_2in4ss_prod.rs index 600edbad..12e833ef 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f16_2in4ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f16_2in4ss_prod.rs @@ -12,6 +12,42 @@ pub mod ftmopa_za16_z8z8zi_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftmopa_za16_z8z8zi_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ftmopa_za16_z8z8zi_b2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f32_2in4ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f32_2in4ss_prod.rs index f8fa7197..b44eba48 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f32_2in4ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_f8f32_2in4ss_prod.rs @@ -12,6 +12,42 @@ pub mod ftmopa_za32_z8z8zi_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftmopa_za32_z8z8zi_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ftmopa_za32_z8z8zi_b2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i16i32_2in4ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i16i32_2in4ss_prod.rs index 66e263d6..bdfe9952 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i16i32_2in4ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i16i32_2in4ss_prod.rs @@ -12,6 +12,42 @@ pub mod stmopa_za32_zzzi_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stmopa_za32_zzzi_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn stmopa_za32_zzzi_h2x1( Zm: ::aarchmrs_types::BitValue<5>, @@ -43,6 +79,42 @@ pub mod utmopa_za32_zzzi_h2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "utmopa_za32_zzzi_h2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn utmopa_za32_zzzi_h2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i8i32_2in4ss_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i8i32_2in4ss_prod.rs index 42716f84..f0b509e9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i8i32_2in4ss_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach2_ss_prod/mortlach_i8i32_2in4ss_prod.rs @@ -12,6 +12,42 @@ pub mod stmopa_za_zzzi_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stmopa_za_zzzi_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn stmopa_za_zzzi_b2x1( Zm: ::aarchmrs_types::BitValue<5>, @@ -43,6 +79,42 @@ pub mod sutmopa_za_zzzi_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sutmopa_za_zzzi_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sutmopa_za_zzzi_b2x1( Zm: ::aarchmrs_types::BitValue<5>, @@ -74,6 +146,42 @@ pub mod ustmopa_za_zzzi_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ustmopa_za_zzzi_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ustmopa_za_zzzi_b2x1( Zm: ::aarchmrs_types::BitValue<5>, @@ -105,6 +213,42 @@ pub mod utmopa_za_zzzi_b2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "utmopa_za_zzzi_b2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_K_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn utmopa_za_zzzi_b2x1( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_b16f32_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_b16f32_prod.rs index dd934214..c4e9d0d8 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_b16f32_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_b16f32_prod.rs @@ -12,6 +12,36 @@ pub mod bfmopa_za32_pp_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmopa_za32_pp_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmopa_za32_pp_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod bfmops_za32_pp_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmops_za32_pp_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmops_za32_pp_zz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f16f32_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f16f32_prod.rs index 802b3562..81e0a108 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f16f32_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f16f32_prod.rs @@ -12,6 +12,36 @@ pub mod fmopa_za32_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmopa_za32_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmopa_za32_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod fmops_za32_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmops_za32_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmops_za32_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f32f32_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f32f32_prod.rs index 8755b1cd..435fdb07 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f32f32_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f32f32_prod.rs @@ -12,6 +12,36 @@ pub mod fmopa_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmopa_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmopa_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod fmops_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmops_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmops_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f8f32_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f8f32_prod.rs index 0ff7ae06..3b1c82bb 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f8f32_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_fp_prod/mortlach_f8f32_prod.rs @@ -12,6 +12,36 @@ pub mod fmopa_za32_pp_z8z8_8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmopa_za32_pp_z8z8_8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmopa_za32_pp_z8z8_8( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i16i32_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i16i32_prod.rs index 405bdaa0..2f38b3d9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i16i32_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i16i32_prod.rs @@ -12,6 +12,36 @@ pub mod smopa_za32_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smopa_za32_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn smopa_za32_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod umopa_za32_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umopa_za32_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn umopa_za32_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, @@ -68,6 +128,36 @@ pub mod smops_za32_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smops_za32_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn smops_za32_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, @@ -96,6 +186,36 @@ pub mod umops_za32_pp_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umops_za32_pp_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn umops_za32_pp_zz_16( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i8i32_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i8i32_prod.rs index a36f42ff..06bd692c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i8i32_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_32bit_int_prod/mortlach_i8i32_prod.rs @@ -12,6 +12,36 @@ pub mod smopa_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smopa_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn smopa_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod sumopa_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumopa_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sumopa_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -68,6 +128,36 @@ pub mod usmopa_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmopa_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn usmopa_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -96,6 +186,36 @@ pub mod umopa_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umopa_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn umopa_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -124,6 +244,36 @@ pub mod smops_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smops_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn smops_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -152,6 +302,36 @@ pub mod sumops_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumops_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sumops_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +360,36 @@ pub mod usmops_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmops_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn usmops_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, @@ -208,6 +418,36 @@ pub mod umops_za_pp_zz_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umops_za_pp_zz_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn umops_za_pp_zz_32( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_f64f64_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_f64f64_prod.rs index cb2e7cf7..c9f92ba6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_f64f64_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_f64f64_prod.rs @@ -12,6 +12,36 @@ pub mod fmopa_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmopa_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmopa_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod fmops_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmops_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmops_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_i16i64_prod.rs b/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_i16i64_prod.rs index f51c7d02..a65eb25c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_i16i64_prod.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_64bit_prod/mortlach_i16i64_prod.rs @@ -12,6 +12,36 @@ pub mod smopa_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smopa_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn smopa_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -40,6 +70,36 @@ pub mod sumopa_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumopa_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sumopa_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -68,6 +128,36 @@ pub mod usmopa_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmopa_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn usmopa_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -96,6 +186,36 @@ pub mod umopa_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umopa_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn umopa_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -124,6 +244,36 @@ pub mod smops_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smops_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn smops_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -152,6 +302,36 @@ pub mod sumops_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumops_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sumops_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +360,36 @@ pub mod usmops_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmops_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn usmops_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, @@ -208,6 +418,36 @@ pub mod umops_za_pp_zz_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umops_za_pp_zz_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn umops_za_pp_zz_64( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_pred.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_pred.rs index 82ec9a7b..6e64fff9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_pred.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_pred.rs @@ -12,6 +12,36 @@ pub mod mova_z_p_rza_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_z_p_rza_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_z_p_rza_b( V: ::aarchmrs_types::BitValue<1>, @@ -40,6 +70,42 @@ pub mod mova_z_p_rza_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_z_p_rza_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_z_p_rza_h( V: ::aarchmrs_types::BitValue<1>, @@ -70,6 +136,42 @@ pub mod mova_z_p_rza_w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_z_p_rza_w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_z_p_rza_w( V: ::aarchmrs_types::BitValue<1>, @@ -100,6 +202,42 @@ pub mod mova_z_p_rza_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_z_p_rza_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_z_p_rza_d( V: ::aarchmrs_types::BitValue<1>, @@ -130,6 +268,36 @@ pub mod mova_z_p_rza_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_z_p_rza_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_z_p_rza_q( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_zero.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_zero.rs index cb8715c7..0833f6e4 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_zero.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_extract_zero.rs @@ -12,6 +12,30 @@ pub mod movaz_z_rza_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_z_rza_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_z_rza_b( V: ::aarchmrs_types::BitValue<1>, @@ -38,6 +62,36 @@ pub mod movaz_z_rza_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_z_rza_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_z_rza_h( V: ::aarchmrs_types::BitValue<1>, @@ -66,6 +120,36 @@ pub mod movaz_z_rza_w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_z_rza_w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_z_rza_w( V: ::aarchmrs_types::BitValue<1>, @@ -94,6 +178,36 @@ pub mod movaz_z_rza_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_z_rza_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_z_rza_d( V: ::aarchmrs_types::BitValue<1>, @@ -122,6 +236,30 @@ pub mod movaz_z_rza_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_z_rza_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_z_rza_q( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_ctg.rs index 4790418a..aaaf2170 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_ctg.rs @@ -12,6 +12,30 @@ pub mod mova_mz2_za_b1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz2_za_b1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz2_za_b1( V: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,36 @@ pub mod mova_mz2_za_h1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz2_za_h1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz2_za_h1( V: ::aarchmrs_types::BitValue<1>, @@ -68,6 +122,36 @@ pub mod mova_mz2_za_w1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz2_za_w1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz2_za_w1( V: ::aarchmrs_types::BitValue<1>, @@ -97,6 +181,30 @@ pub mod mova_mz2_za_d1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz2_za_d1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz2_za_d1( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_zero.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_zero.rs index a07b1639..29f49565 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_zero.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_extract_zero.rs @@ -12,6 +12,30 @@ pub mod movaz_mz2_za_b1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz2_za_b1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz2_za_b1( V: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,36 @@ pub mod movaz_mz2_za_h1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz2_za_h1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz2_za_h1( V: ::aarchmrs_types::BitValue<1>, @@ -68,6 +122,36 @@ pub mod movaz_mz2_za_w1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz2_za_w1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz2_za_w1( V: ::aarchmrs_types::BitValue<1>, @@ -97,6 +181,30 @@ pub mod movaz_mz2_za_d1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz2_za_d1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz2_za_d1( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_ctg.rs index b7951c15..3cba11de 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_ctg.rs @@ -12,6 +12,24 @@ pub mod mova_mz_za2_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz_za2_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn mova_mz_za2_1( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_zero.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_zero.rs index 167fcbb3..f3b538a8 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_zero.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi2_za_extract_zero.rs @@ -12,6 +12,24 @@ pub mod movaz_mz_za2_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz_za2_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn movaz_mz_za2_1( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_ctg.rs index 3e327d1b..06bd54f0 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_ctg.rs @@ -12,6 +12,30 @@ pub mod mova_mz4_za_b1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz4_za_b1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz4_za_b1( V: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,36 @@ pub mod mova_mz4_za_h1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz4_za_h1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz4_za_h1( V: ::aarchmrs_types::BitValue<1>, @@ -68,6 +122,30 @@ pub mod mova_mz4_za_w1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz4_za_w1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz4_za_w1( V: ::aarchmrs_types::BitValue<1>, @@ -95,6 +173,30 @@ pub mod mova_mz4_za_d1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz4_za_d1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_mz4_za_d1( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_zero.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_zero.rs index c1dcd3e3..54b08203 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_zero.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_extract_zero.rs @@ -12,6 +12,30 @@ pub mod movaz_mz4_za_b1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz4_za_b1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz4_za_b1( V: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,36 @@ pub mod movaz_mz4_za_h1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz4_za_h1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz4_za_h1( V: ::aarchmrs_types::BitValue<1>, @@ -68,6 +122,30 @@ pub mod movaz_mz4_za_w1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz4_za_w1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz4_za_w1( V: ::aarchmrs_types::BitValue<1>, @@ -95,6 +173,30 @@ pub mod movaz_mz4_za_d1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz4_za_d1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn movaz_mz4_za_d1( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_ctg.rs index 58297980..66c6d582 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_ctg.rs @@ -12,6 +12,24 @@ pub mod mova_mz_za4_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_mz_za4_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn mova_mz_za4_1( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_zero.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_zero.rs index 876b05fd..f10527d6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_zero.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ext/mortlach_multi4_za_extract_zero.rs @@ -12,6 +12,24 @@ pub mod movaz_mz_za4_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movaz_mz_za4_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn movaz_mz_za4_1( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_hvadd/mortlach_addhv.rs b/aarchmrs-instructions/src/A64/sme/mortlach_hvadd/mortlach_addhv.rs index 1b7ac8f9..fbbff15f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_hvadd/mortlach_addhv.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_hvadd/mortlach_addhv.rs @@ -12,6 +12,30 @@ pub mod addha_za_pp_z_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addha_za_pp_z_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; #[inline] pub const fn addha_za_pp_z_32( Pm: ::aarchmrs_types::BitValue<3>, @@ -38,6 +62,30 @@ pub mod addha_za_pp_z_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addha_za_pp_z_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; #[inline] pub const fn addha_za_pp_z_64( Pm: ::aarchmrs_types::BitValue<3>, @@ -64,6 +112,30 @@ pub mod addva_za_pp_z_32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addva_za_pp_z_32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; #[inline] pub const fn addva_za_pp_z_32( Pm: ::aarchmrs_types::BitValue<3>, @@ -90,6 +162,30 @@ pub mod addva_za_pp_z_64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addva_za_pp_z_64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAda_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 3u32; #[inline] pub const fn addva_za_pp_z_64( Pm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_insert_pred.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_insert_pred.rs index d844eb35..05a5bf17 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_insert_pred.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_insert_pred.rs @@ -12,6 +12,36 @@ pub mod mova_za_p_rz_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za_p_rz_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za_p_rz_b( V: ::aarchmrs_types::BitValue<1>, @@ -40,6 +70,42 @@ pub mod mova_za_p_rz_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za_p_rz_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za_p_rz_h( V: ::aarchmrs_types::BitValue<1>, @@ -70,6 +136,42 @@ pub mod mova_za_p_rz_w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za_p_rz_w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za_p_rz_w( V: ::aarchmrs_types::BitValue<1>, @@ -100,6 +202,42 @@ pub mod mova_za_p_rz_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za_p_rz_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za_p_rz_d( V: ::aarchmrs_types::BitValue<1>, @@ -130,6 +268,36 @@ pub mod mova_za_p_rz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za_p_rz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za_p_rz_q( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_insert_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_insert_ctg.rs index ecb2c05b..35ba6cbe 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_insert_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_insert_ctg.rs @@ -12,6 +12,30 @@ pub mod mova_za2_z_b1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za2_z_b1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za2_z_b1( V: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,36 @@ pub mod mova_za2_z_h1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za2_z_h1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za2_z_h1( V: ::aarchmrs_types::BitValue<1>, @@ -68,6 +122,36 @@ pub mod mova_za2_z_w1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za2_z_w1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za2_z_w1( V: ::aarchmrs_types::BitValue<1>, @@ -97,6 +181,30 @@ pub mod mova_za2_z_d1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za2_z_d1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za2_z_d1( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_za_insert_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_za_insert_ctg.rs index b5f2676e..48a5f0a6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_za_insert_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi2_za_insert_ctg.rs @@ -12,6 +12,24 @@ pub mod mova_za_mz2_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za_mz2_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn mova_za_mz2_1( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_insert_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_insert_ctg.rs index 240e6aa7..1aaae3a9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_insert_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_insert_ctg.rs @@ -12,6 +12,30 @@ pub mod mova_za4_z_b1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za4_z_b1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za4_z_b1( V: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,36 @@ pub mod mova_za4_z_h1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za4_z_h1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za4_z_h1( V: ::aarchmrs_types::BitValue<1>, @@ -68,6 +122,30 @@ pub mod mova_za4_z_w1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za4_z_w1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za4_z_w1( V: ::aarchmrs_types::BitValue<1>, @@ -95,6 +173,30 @@ pub mod mova_za4_z_d1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za4_z_d1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; #[inline] pub const fn mova_za4_z_d1( V: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_za_insert_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_za_insert_ctg.rs index eb7ac47e..404658ba 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_za_insert_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_ins/mortlach_multi4_za_insert_ctg.rs @@ -12,6 +12,24 @@ pub mod mova_za_mz4_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mova_za_mz4_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn mova_za_mz4_1( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_load.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_load.rs index 1938592a..e0bc5a72 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_load.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_load.rs @@ -12,6 +12,42 @@ pub mod ld1b_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, @@ -42,6 +78,48 @@ pub mod ld1h_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, @@ -74,6 +152,48 @@ pub mod ld1w_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, @@ -106,6 +226,48 @@ pub mod ld1d_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qload.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qload.rs index fc715d09..50996a29 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qload.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qload.rs @@ -12,6 +12,42 @@ pub mod ld1q_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1q_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1q_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qstore.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qstore.rs index 9f02e425..d11be354 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qstore.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_qstore.rs @@ -12,6 +12,42 @@ pub mod st1q_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1q_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1q_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_store.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_store.rs index 27f34c35..b32d9bc8 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_store.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_contig_store.rs @@ -12,6 +12,42 @@ pub mod st1b_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, @@ -42,6 +78,48 @@ pub mod st1h_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, @@ -74,6 +152,48 @@ pub mod st1w_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, @@ -106,6 +226,48 @@ pub mod st1d_za_p_rrr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_za_p_rrr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_ZAt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_V_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_za_p_rrr_( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_ctxt_ldst.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_ctxt_ldst.rs index 706f44bf..72010d60 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_ctxt_ldst.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_ctxt_ldst.rs @@ -12,6 +12,24 @@ pub mod ldr_za_ri_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldr_za_ri_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn ldr_za_ri_( Rv: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod str_za_ri_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "str_za_ri_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn str_za_ri_( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_zt_ldst.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_zt_ldst.rs index 60423a6f..b8470a6c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_zt_ldst.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mem/mortlach_zt_ldst.rs @@ -12,6 +12,12 @@ pub mod ldr_zt_br_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldr_zt_br_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn ldr_zt_br_( Rn: ::aarchmrs_types::BitValue<5>, @@ -30,6 +36,12 @@ pub mod str_zt_br_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "str_zt_br_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn str_zt_br_( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_extract_zt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_extract_zt.rs index f33994dc..3621f4b0 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_extract_zt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_extract_zt.rs @@ -12,6 +12,18 @@ pub mod movt_r_zt_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movt_r_zt_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; #[inline] pub const fn movt_r_zt_( off3: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_insert_zt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_insert_zt.rs index ad01f265..bcf9028f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_insert_zt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_insert_zt.rs @@ -12,6 +12,18 @@ pub mod movt_zt_r_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movt_zt_r_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; #[inline] pub const fn movt_zt_r_( off3: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_move_to_zt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_move_to_zt.rs index 2af7b622..a1f4e27d 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_move_to_zt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_mov_zt/mortlach_move_to_zt.rs @@ -12,6 +12,18 @@ pub mod movt_zt_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movt_zt_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; #[inline] pub const fn movt_zt_z_( off2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_fma_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_fma_long_sm.rs index 62b45d4f..2802bdc1 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_fma_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_fma_long_sm.rs @@ -12,6 +12,30 @@ pub mod bfmlal_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlal_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod fmlal_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod bfmlsl_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlsl_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod fmlsl_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlsl_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_long_sm.rs index 0419d47e..97224880 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_long_sm.rs @@ -12,6 +12,36 @@ pub mod smlall_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlall_za_zzv_1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,30 @@ pub mod usmlall_za_zzv_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzv_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usmlall_za_zzv_s( Zm: ::aarchmrs_types::BitValue<4>, @@ -71,6 +125,36 @@ pub mod smlsll_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlsll_za_zzv_1( sz: ::aarchmrs_types::BitValue<1>, @@ -102,6 +186,36 @@ pub mod umlall_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlall_za_zzv_1( sz: ::aarchmrs_types::BitValue<1>, @@ -133,6 +247,36 @@ pub mod umlsll_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlsll_za_zzv_1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_sm.rs index 984a1aa9..961ec910 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi1_zz_za_mla_long_sm.rs @@ -12,6 +12,30 @@ pub mod smlal_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlal_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod smlsl_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsl_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod umlal_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlal_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod umlsl_za_zzv_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzv_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsl_za_zzv_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_2way_dot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_2way_dot_sm.rs index 4594049f..afb77ec5 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_2way_dot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_2way_dot_sm.rs @@ -12,6 +12,30 @@ pub mod sdot_za32_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za32_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za32_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod udot_za32_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za32_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za32_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_4way_dot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_4way_dot_sm.rs index 9f601192..1a765ba8 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_4way_dot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_4way_dot_sm.rs @@ -12,6 +12,36 @@ pub mod sdot_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sdot_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod udot_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn udot_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_fpdot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_fpdot_sm.rs index 6ead6406..a9bf1f5c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_fpdot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_fpdot_sm.rs @@ -12,6 +12,30 @@ pub mod fdot_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod bfdot_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfdot_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fdot_za_z8z8v_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_z8z8v_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_z8z8v_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod fdot_za32_z8z8v_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za32_z8z8v_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za32_z8z8v_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_mixed_dot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_mixed_dot_sm.rs index 3cb356c1..2938f82a 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_mixed_dot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_z_za_mixed_dot_sm.rs @@ -12,6 +12,30 @@ pub mod usdot_za_zzv_s2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_za_zzv_s2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usdot_za_zzv_s2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod sudot_za_zzv_s2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sudot_za_zzv_s2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sudot_za_zzv_s2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_f16_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_f16_sm.rs index ab34c520..b7dc8445 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_f16_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_f16_sm.rs @@ -12,6 +12,30 @@ pub mod fmla_za_zzv_2x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzv_2x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzv_2x1_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod bfmla_za_zzv_2x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_za_zzv_2x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmla_za_zzv_2x1_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fmls_za_zzv_2x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzv_2x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzv_2x1_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod bfmls_za_zzv_2x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_za_zzv_2x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmls_za_zzv_2x1_16( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_float_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_float_sm.rs index 6706fcc1..aa6d0e72 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_float_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_float_sm.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmla_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod fmls_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmls_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fma_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fma_long_sm.rs index e24780d5..e9a7bef7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fma_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fma_long_sm.rs @@ -12,6 +12,30 @@ pub mod bfmlal_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlal_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod fmlal_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fmlal_za_z8z8v_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8v_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_z8z8v_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod bfmlsl_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlsl_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -124,6 +220,30 @@ pub mod fmlsl_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlsl_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fp8_fma_long_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fp8_fma_long_long_sm.rs index 47047716..2178b4a8 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fp8_fma_long_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_fp8_fma_long_long_sm.rs @@ -12,6 +12,30 @@ pub mod fmlall_za32_z8z8v_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8v_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlall_za32_z8z8v_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_int_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_int_sm.rs index f5b41fb6..0182688f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_int_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_int_sm.rs @@ -12,6 +12,36 @@ pub mod add_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn add_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod sub_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sub_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_long_sm.rs index 026f8ab0..4fd76268 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_long_sm.rs @@ -12,6 +12,36 @@ pub mod smlall_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlall_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,30 @@ pub mod usmlall_za_zzv_s2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzv_s2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usmlall_za_zzv_s2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -71,6 +125,36 @@ pub mod smlsll_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlsll_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, @@ -102,6 +186,36 @@ pub mod umlall_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlall_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, @@ -133,6 +247,30 @@ pub mod sumlall_za_zzv_s2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumlall_za_zzv_s2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sumlall_za_zzv_s2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -161,6 +299,36 @@ pub mod umlsll_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlsll_za_zzv_2x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_sm.rs index 125af62c..6bd90daa 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1a/mortlach_multi2_zz_za_mla_long_sm.rs @@ -12,6 +12,30 @@ pub mod smlal_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlal_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod smlsl_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsl_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod umlal_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlal_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod umlsl_za_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsl_za_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_long_sm.rs index 3b665dea..3bb4e229 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_long_sm.rs @@ -12,6 +12,30 @@ pub mod fmlall_za32_z8z8v_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8v_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlall_za32_z8z8v_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_sm.rs index 9c78e4cf..749a0a8f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi1_zz_za_fp8_fma_long_sm.rs @@ -12,6 +12,30 @@ pub mod fmlal_za_z8z8v_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8v_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_z8z8v_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_2way_dot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_2way_dot_sm.rs index 647f25c5..4f8dfe84 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_2way_dot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_2way_dot_sm.rs @@ -12,6 +12,30 @@ pub mod sdot_za32_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za32_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za32_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod udot_za32_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za32_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za32_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_4way_dot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_4way_dot_sm.rs index 55cdad30..134ada9b 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_4way_dot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_4way_dot_sm.rs @@ -12,6 +12,36 @@ pub mod sdot_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sdot_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod udot_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn udot_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_fpdot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_fpdot_sm.rs index 3cab3544..7150313f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_fpdot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_fpdot_sm.rs @@ -12,6 +12,30 @@ pub mod fdot_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod bfdot_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfdot_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fdot_za_z8z8v_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_z8z8v_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_z8z8v_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod fdot_za32_z8z8v_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za32_z8z8v_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za32_z8z8v_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_mixed_dot_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_mixed_dot_sm.rs index c729b2ba..9d6c0d61 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_mixed_dot_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_z_za_mixed_dot_sm.rs @@ -12,6 +12,30 @@ pub mod usdot_za_zzv_s4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_za_zzv_s4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usdot_za_zzv_s4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod sudot_za_zzv_s4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sudot_za_zzv_s4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sudot_za_zzv_s4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_f16_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_f16_sm.rs index 58b4ca12..677f57bd 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_f16_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_f16_sm.rs @@ -12,6 +12,30 @@ pub mod fmla_za_zzv_4x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzv_4x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzv_4x1_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod bfmla_za_zzv_4x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_za_zzv_4x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmla_za_zzv_4x1_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fmls_za_zzv_4x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzv_4x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzv_4x1_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod bfmls_za_zzv_4x1_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_za_zzv_4x1_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmls_za_zzv_4x1_16( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_float_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_float_sm.rs index 76497763..f2da053d 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_float_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_float_sm.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmla_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod fmls_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmls_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fma_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fma_long_sm.rs index 90f87655..01fc337a 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fma_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fma_long_sm.rs @@ -12,6 +12,30 @@ pub mod bfmlal_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlal_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod fmlal_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fmlal_za_z8z8v_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8v_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_z8z8v_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod bfmlsl_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlsl_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -124,6 +220,30 @@ pub mod fmlsl_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlsl_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fp8_fma_long_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fp8_fma_long_long_sm.rs index dbbfd0d0..f5d3fe15 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fp8_fma_long_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_fp8_fma_long_long_sm.rs @@ -12,6 +12,30 @@ pub mod fmlall_za32_z8z8v_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8v_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlall_za32_z8z8v_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_int_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_int_sm.rs index f26a5bc0..372ab0d4 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_int_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_int_sm.rs @@ -12,6 +12,36 @@ pub mod add_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn add_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod sub_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sub_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_long_sm.rs index d6e1ef6f..9fee8330 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_long_sm.rs @@ -12,6 +12,36 @@ pub mod smlall_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlall_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,30 @@ pub mod usmlall_za_zzv_s4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzv_s4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usmlall_za_zzv_s4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -71,6 +125,36 @@ pub mod smlsll_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlsll_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, @@ -102,6 +186,36 @@ pub mod umlall_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlall_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, @@ -133,6 +247,30 @@ pub mod sumlall_za_zzv_s4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumlall_za_zzv_s4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sumlall_za_zzv_s4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -161,6 +299,36 @@ pub mod umlsll_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlsll_za_zzv_4x1( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_sm.rs index 778e6620..38672db2 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_1b/mortlach_multi4_zz_za_mla_long_sm.rs @@ -12,6 +12,30 @@ pub mod smlal_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlal_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod smlsl_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsl_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod umlal_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlal_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod umlsl_za_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsl_za_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_2way_dot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_2way_dot_mm.rs index ed918d24..82787c5e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_2way_dot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_2way_dot_mm.rs @@ -12,6 +12,30 @@ pub mod sdot_za32_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za32_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za32_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod udot_za32_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za32_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za32_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_4way_dot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_4way_dot_mm.rs index 4ddb48fc..c40bdd12 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_4way_dot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_4way_dot_mm.rs @@ -12,6 +12,36 @@ pub mod sdot_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sdot_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod udot_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn udot_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_f16_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_f16_mm.rs index c0f624f0..a6274206 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_f16_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_f16_mm.rs @@ -12,6 +12,24 @@ pub mod fadd_za_zw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadd_za_zw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn fadd_za_zw_2x2_16( Rv: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod bfadd_za_zw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfadd_za_zw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn bfadd_za_zw_2x2_16( Rv: ::aarchmrs_types::BitValue<2>, @@ -62,6 +98,24 @@ pub mod fsub_za_zw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsub_za_zw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn fsub_za_zw_2x2_16( Rv: ::aarchmrs_types::BitValue<2>, @@ -87,6 +141,24 @@ pub mod bfsub_za_zw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfsub_za_zw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn bfsub_za_zw_2x2_16( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_float_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_float_mm.rs index c16246a7..ad3a49a7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_float_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_float_mm.rs @@ -12,6 +12,30 @@ pub mod fadd_za_zw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadd_za_zw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fadd_za_zw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod fsub_za_zw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsub_za_zw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fsub_za_zw_2x2( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_fpdot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_fpdot_mm.rs index c1933239..1dcf40eb 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_fpdot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_fpdot_mm.rs @@ -12,6 +12,30 @@ pub mod fdot_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod bfdot_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfdot_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fdot_za_z8z8w_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_z8z8w_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_z8z8w_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod fdot_za32_z8z8w_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za32_z8z8w_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za32_z8z8w_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_int_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_int_mm.rs index fc623da6..101bc2b2 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_int_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_int_mm.rs @@ -12,6 +12,30 @@ pub mod add_za_zw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_za_zw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn add_za_zw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod sub_za_zw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_za_zw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sub_za_zw_2x2( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_mixed_dot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_mixed_dot_mm.rs index 0f1eadc2..c7e88220 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_mixed_dot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_z_za_mixed_dot_mm.rs @@ -12,6 +12,30 @@ pub mod usdot_za_zzw_s2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_za_zzw_s2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usdot_za_zzw_s2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_f16_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_f16_mm.rs index 813d8982..20e425af 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_f16_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_f16_mm.rs @@ -12,6 +12,30 @@ pub mod fmla_za_zzw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzw_2x2_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod bfmla_za_zzw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_za_zzw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmla_za_zzw_2x2_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod fmls_za_zzw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzw_2x2_16( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod bfmls_za_zzw_2x2_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_za_zzw_2x2_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmls_za_zzw_2x2_16( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_float_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_float_mm.rs index a314efe7..b428bb68 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_float_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_float_mm.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmla_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod fmls_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmls_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fma_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fma_long_mm.rs index b859a258..79f2bc8b 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fma_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fma_long_mm.rs @@ -12,6 +12,30 @@ pub mod bfmlal_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlal_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod fmlal_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod bfmlsl_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlsl_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod fmlsl_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlsl_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_long_mm.rs index 5e015245..066bf35a 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_long_mm.rs @@ -12,6 +12,30 @@ pub mod fmlall_za32_z8z8w_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8w_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlall_za32_z8z8w_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_mm.rs index 12294db6..901b3f65 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_fp8_fma_long_mm.rs @@ -12,6 +12,30 @@ pub mod fmlal_za_z8z8w_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8w_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_z8z8w_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_int_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_int_mm.rs index f615d4dd..301eef7f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_int_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_int_mm.rs @@ -12,6 +12,36 @@ pub mod add_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn add_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod sub_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sub_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_long_mm.rs index ad47f95b..bbcd12fc 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_long_mm.rs @@ -12,6 +12,36 @@ pub mod smlall_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlall_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,30 @@ pub mod usmlall_za_zzw_s2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzw_s2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usmlall_za_zzw_s2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -71,6 +125,36 @@ pub mod smlsll_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlsll_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -102,6 +186,36 @@ pub mod umlall_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlall_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, @@ -133,6 +247,36 @@ pub mod umlsll_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlsll_za_zzw_2x2( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_mm.rs index b69623c8..b50eee79 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2a/mortlach_multi2_zz_za_mla_long_mm.rs @@ -12,6 +12,30 @@ pub mod smlal_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlal_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod smlsl_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsl_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod umlal_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlal_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod umlsl_za_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsl_za_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_2way_dot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_2way_dot_mm.rs index acc29cf3..506afef1 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_2way_dot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_2way_dot_mm.rs @@ -12,6 +12,30 @@ pub mod sdot_za32_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za32_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn sdot_za32_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -40,6 +64,30 @@ pub mod udot_za32_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za32_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn udot_za32_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_4way_dot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_4way_dot_mm.rs index 13d5aff7..907a0937 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_4way_dot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_4way_dot_mm.rs @@ -12,6 +12,36 @@ pub mod sdot_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sdot_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod udot_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn udot_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_f16_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_f16_mm.rs index fb0a36c1..801e87e7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_f16_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_f16_mm.rs @@ -12,6 +12,24 @@ pub mod fadd_za_zw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadd_za_zw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn fadd_za_zw_4x4_16( Rv: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod bfadd_za_zw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfadd_za_zw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn bfadd_za_zw_4x4_16( Rv: ::aarchmrs_types::BitValue<2>, @@ -62,6 +98,24 @@ pub mod fsub_za_zw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsub_za_zw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn fsub_za_zw_4x4_16( Rv: ::aarchmrs_types::BitValue<2>, @@ -87,6 +141,24 @@ pub mod bfsub_za_zw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfsub_za_zw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn bfsub_za_zw_4x4_16( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_float_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_float_mm.rs index a08dba08..403efbf1 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_float_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_float_mm.rs @@ -12,6 +12,30 @@ pub mod fadd_za_zw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadd_za_zw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fadd_za_zw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod fsub_za_zw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsub_za_zw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fsub_za_zw_4x4( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_fpdot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_fpdot_mm.rs index 53308b02..8ecec73c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_fpdot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_fpdot_mm.rs @@ -12,6 +12,30 @@ pub mod fdot_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fdot_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -40,6 +64,30 @@ pub mod bfdot_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfdot_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -68,6 +116,30 @@ pub mod fdot_za_z8z8w_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_z8z8w_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fdot_za_z8z8w_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -96,6 +168,30 @@ pub mod fdot_za32_z8z8w_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za32_z8z8w_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fdot_za32_z8z8w_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_int_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_int_mm.rs index 5829aaec..2e8c3f1c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_int_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_int_mm.rs @@ -12,6 +12,30 @@ pub mod add_za_zw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_za_zw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn add_za_zw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod sub_za_zw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_za_zw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sub_za_zw_4x4( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_mixed_dot_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_mixed_dot_mm.rs index f3ff9c5f..67e75a61 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_mixed_dot_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_z_za_mixed_dot_mm.rs @@ -12,6 +12,30 @@ pub mod usdot_za_zzw_s4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_za_zzw_s4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usdot_za_zzw_s4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_f16_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_f16_mm.rs index 8d21dc5b..1bb78ec6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_f16_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_f16_mm.rs @@ -12,6 +12,30 @@ pub mod fmla_za_zzw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmla_za_zzw_4x4_16( Zm: ::aarchmrs_types::BitValue<3>, @@ -40,6 +64,30 @@ pub mod bfmla_za_zzw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_za_zzw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmla_za_zzw_4x4_16( Zm: ::aarchmrs_types::BitValue<3>, @@ -68,6 +116,30 @@ pub mod fmls_za_zzw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmls_za_zzw_4x4_16( Zm: ::aarchmrs_types::BitValue<3>, @@ -96,6 +168,30 @@ pub mod bfmls_za_zzw_4x4_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_za_zzw_4x4_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmls_za_zzw_4x4_16( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_float_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_float_mm.rs index 75adc67b..a1facaea 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_float_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_float_mm.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmla_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod fmls_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn fmls_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fma_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fma_long_mm.rs index 158fc5ca..aa7c6a14 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fma_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fma_long_mm.rs @@ -12,6 +12,30 @@ pub mod bfmlal_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmlal_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -40,6 +64,30 @@ pub mod fmlal_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmlal_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -68,6 +116,30 @@ pub mod bfmlsl_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmlsl_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -96,6 +168,30 @@ pub mod fmlsl_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmlsl_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_long_mm.rs index 5efdcb4e..f7f3ebc1 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_long_mm.rs @@ -12,6 +12,30 @@ pub mod fmlall_za32_z8z8w_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8w_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmlall_za32_z8z8w_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_mm.rs index a9002b24..3d2a71ca 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_fp8_fma_long_mm.rs @@ -12,6 +12,30 @@ pub mod fmlal_za_z8z8w_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8w_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn fmlal_za_z8z8w_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_int_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_int_mm.rs index de01d272..54c405fb 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_int_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_int_mm.rs @@ -12,6 +12,36 @@ pub mod add_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn add_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod sub_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sub_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_long_mm.rs index 1ca558c2..2c35600e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_long_mm.rs @@ -12,6 +12,36 @@ pub mod smlall_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlall_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,30 @@ pub mod usmlall_za_zzw_s4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzw_s4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn usmlall_za_zzw_s4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -71,6 +125,36 @@ pub mod smlsll_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn smlsll_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -102,6 +186,36 @@ pub mod umlall_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlall_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, @@ -133,6 +247,36 @@ pub mod umlsll_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn umlsll_za_zzw_4x4( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_mm.rs index c90f64e2..777e10e4 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_array_2b/mortlach_multi4_zz_za_mla_long_mm.rs @@ -12,6 +12,30 @@ pub mod smlal_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smlal_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -40,6 +64,30 @@ pub mod smlsl_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn smlsl_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -68,6 +116,30 @@ pub mod umlal_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umlal_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -96,6 +168,30 @@ pub mod umlsl_za_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn umlsl_za_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fma_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fma_long_idx.rs index 755c2126..421072c0 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fma_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fma_long_idx.rs @@ -12,6 +12,42 @@ pub mod bfmlal_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlal_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -43,6 +79,42 @@ pub mod fmlal_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -74,6 +146,42 @@ pub mod bfmlsl_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlsl_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -105,6 +213,42 @@ pub mod fmlsl_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlsl_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_idx.rs index 20d1b087..9e2761f0 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_idx.rs @@ -12,6 +12,48 @@ pub mod fmlal_za_z8z8i_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8i_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4C_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4C_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4B_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4B_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4A_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4A_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_z8z8i_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_long_idx.rs index ea344aa4..8dc80ee3 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_fp8_fma_long_long_idx.rs @@ -12,6 +12,42 @@ pub mod fmlall_za32_z8z8i_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8i_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlall_za32_z8z8i_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_idx.rs index fd0c9cbc..3fc27b7d 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_idx.rs @@ -12,6 +12,42 @@ pub mod smlal_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlal_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -43,6 +79,42 @@ pub mod smlsl_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsl_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -74,6 +146,42 @@ pub mod umlal_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlal_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, @@ -105,6 +213,42 @@ pub mod umlsl_za_zzi_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzi_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsl_za_zzi_1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_d.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_d.rs index abe6ebae..9a4e2d94 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_d.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_d.rs @@ -12,6 +12,42 @@ pub mod smlall_za_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlall_za_zzi_d( Zm: ::aarchmrs_types::BitValue<4>, @@ -43,6 +79,42 @@ pub mod smlsll_za_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsll_za_zzi_d( Zm: ::aarchmrs_types::BitValue<4>, @@ -74,6 +146,42 @@ pub mod umlall_za_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlall_za_zzi_d( Zm: ::aarchmrs_types::BitValue<4>, @@ -105,6 +213,42 @@ pub mod umlsll_za_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsll_za_zzi_d( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_s.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_s.rs index c39ba586..65bd7479 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_s.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_1/mortlach_multi1_mla_long_long_idx_s.rs @@ -12,6 +12,42 @@ pub mod smlall_za_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlall_za_zzi_s( Zm: ::aarchmrs_types::BitValue<4>, @@ -42,6 +78,42 @@ pub mod usmlall_za_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usmlall_za_zzi_s( Zm: ::aarchmrs_types::BitValue<4>, @@ -72,6 +144,42 @@ pub mod smlsll_za_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsll_za_zzi_s( Zm: ::aarchmrs_types::BitValue<4>, @@ -102,6 +210,42 @@ pub mod umlall_za_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlall_za_zzi_s( Zm: ::aarchmrs_types::BitValue<4>, @@ -132,6 +276,42 @@ pub mod sumlall_za_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumlall_za_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sumlall_za_zzi_s( Zm: ::aarchmrs_types::BitValue<4>, @@ -162,6 +342,42 @@ pub mod umlsll_za_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsll_za_zzi_s( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fma_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fma_long_idx.rs index 69a363c1..c0900386 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fma_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fma_long_idx.rs @@ -12,6 +12,42 @@ pub mod bfmlal_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlal_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod fmlal_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod bfmlsl_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlsl_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod fmlsl_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlsl_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fdot_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fdot_idx.rs index 21941fdb..3ed20908 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fdot_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fdot_idx.rs @@ -12,6 +12,42 @@ pub mod fdot_za_z8z8i_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_z8z8i_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_z8z8i_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod fvdot_za_z8z8i_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fvdot_za_z8z8i_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fvdot_za_z8z8i_2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_idx.rs index b8f798cd..93d86240 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_idx.rs @@ -12,6 +12,42 @@ pub mod fmlal_za_z8z8i_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8i_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_z8z8i_2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_long_idx.rs index 413e0c5c..0ecd751b 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fma_long_long_idx.rs @@ -12,6 +12,42 @@ pub mod fmlall_za32_z8z8i_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8i_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlall_za32_z8z8i_2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fvdot_idx_s.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fvdot_idx_s.rs index dfe42ace..1d20b2de 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fvdot_idx_s.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_fp8_fvdot_idx_s.rs @@ -12,6 +12,42 @@ pub mod fvdotb_za32_z8z8i_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fvdotb_za32_z8z8i_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fvdotb_za32_z8z8i_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod fvdott_za32_z8z8i_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fvdott_za32_z8z8i_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fvdott_za32_z8z8i_2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_idx.rs index a7e6751c..c99402a6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_idx.rs @@ -12,6 +12,42 @@ pub mod smlal_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlal_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod smlsl_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsl_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod umlal_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlal_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod umlsl_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsl_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_d.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_d.rs index 0c22c040..dcdb571c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_d.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_d.rs @@ -12,6 +12,42 @@ pub mod smlall_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlall_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod smlsll_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsll_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod umlall_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlall_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod umlsll_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsll_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_s.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_s.rs index 6cab29fe..4c65729f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_s.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_mla_long_long_idx_s.rs @@ -12,6 +12,42 @@ pub mod smlall_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlall_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod usmlall_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usmlall_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod smlsll_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsll_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod umlall_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlall_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -140,6 +284,42 @@ pub mod sumlall_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumlall_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sumlall_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -172,6 +352,42 @@ pub mod umlsll_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsll_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_d.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_d.rs index 0f2aee2b..40c14524 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_d.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_d.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -42,6 +72,36 @@ pub mod sdot_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -72,6 +132,36 @@ pub mod fmls_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -102,6 +192,36 @@ pub mod udot_za_zzi_d2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzi_d2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za_zzi_d2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_h.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_h.rs index 62a6a668..7f95129f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_h.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_h.rs @@ -12,6 +12,42 @@ pub mod fmla_za_zzi_h2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzi_h2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzi_h2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod bfmla_za_zzi_h2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_za_zzi_h2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmla_za_zzi_h2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod fmls_za_zzi_h2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzi_h2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzi_h2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod bfmls_za_zzi_h2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_za_zzi_h2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmls_za_zzi_h2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_s.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_s.rs index e3dcf9e3..c731a0c7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_s.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_2/mortlach_multi2_zza_idx_s.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -42,6 +72,36 @@ pub mod fvdot_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fvdot_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fvdot_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -72,6 +132,36 @@ pub mod bfvdot_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfvdot_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfvdot_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -102,6 +192,36 @@ pub mod svdot_za32_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "svdot_za32_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn svdot_za32_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -132,6 +252,36 @@ pub mod fdot_za32_z8z8i_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za32_z8z8i_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za32_z8z8i_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -162,6 +312,36 @@ pub mod sdot_za32_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za32_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za32_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -192,6 +372,36 @@ pub mod fdot_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -222,6 +432,36 @@ pub mod bfdot_za_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_za_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfdot_za_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -252,6 +492,36 @@ pub mod sdot_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -282,6 +552,36 @@ pub mod usdot_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usdot_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -312,6 +612,36 @@ pub mod fmls_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -342,6 +672,36 @@ pub mod uvdot_za32_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uvdot_za32_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn uvdot_za32_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -372,6 +732,36 @@ pub mod udot_za32_zzi_2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za32_zzi_2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za32_zzi_2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -402,6 +792,36 @@ pub mod udot_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -432,6 +852,36 @@ pub mod sudot_za_zzi_s2xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sudot_za_zzi_s2xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sudot_za_zzi_s2xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fma_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fma_long_idx.rs index d229b850..19a82411 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fma_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fma_long_idx.rs @@ -12,6 +12,42 @@ pub mod bfmlal_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlal_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlal_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod fmlal_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod bfmlsl_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlsl_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmlsl_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod fmlsl_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlsl_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlsl_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fdot_idx_h.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fdot_idx_h.rs index 577ed709..72a1c3e1 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fdot_idx_h.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fdot_idx_h.rs @@ -12,6 +12,42 @@ pub mod fdot_za_z8z8i_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_z8z8i_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_z8z8i_4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_idx.rs index 012a0f38..1aa6cb46 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_idx.rs @@ -12,6 +12,42 @@ pub mod fmlal_za_z8z8i_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlal_za_z8z8i_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlal_za_z8z8i_4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_long_idx.rs index f8da1e0c..84b59fb1 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_fp8_fma_long_long_idx.rs @@ -12,6 +12,42 @@ pub mod fmlall_za32_z8z8i_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlall_za32_z8z8i_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmlall_za32_z8z8i_4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_idx.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_idx.rs index 0b50fbf3..984e5689 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_idx.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_idx.rs @@ -12,6 +12,42 @@ pub mod smlal_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlal_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlal_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod smlsl_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsl_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsl_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod umlal_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlal_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlal_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod umlsl_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsl_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsl_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_d.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_d.rs index b990534f..c1e457b2 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_d.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_d.rs @@ -12,6 +12,42 @@ pub mod smlall_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlall_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod smlsll_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsll_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod umlall_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlall_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod umlsll_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsll_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_s.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_s.rs index 257cc89d..bd8c9108 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_s.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_mla_long_long_idx_s.rs @@ -12,6 +12,42 @@ pub mod smlall_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlall_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlall_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod usmlall_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmlall_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usmlall_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod smlsll_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlsll_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn smlsll_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod umlall_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlall_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlall_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -140,6 +284,42 @@ pub mod sumlall_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sumlall_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sumlall_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -172,6 +352,42 @@ pub mod umlsll_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlsll_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn umlsll_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_d.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_d.rs index f18cc06f..b4f787ca 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_d.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_d.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -42,6 +72,36 @@ pub mod sdot_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -72,6 +132,36 @@ pub mod svdot_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "svdot_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn svdot_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -102,6 +192,36 @@ pub mod fmls_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -132,6 +252,36 @@ pub mod udot_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -162,6 +312,36 @@ pub mod uvdot_za_zzi_d4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uvdot_za_zzi_d4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn uvdot_za_zzi_d4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_h.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_h.rs index 7f7d1786..2338adc7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_h.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_h.rs @@ -12,6 +12,42 @@ pub mod fmla_za_zzi_h4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzi_h4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzi_h4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -44,6 +80,42 @@ pub mod bfmla_za_zzi_h4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_za_zzi_h4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmla_za_zzi_h4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -76,6 +148,42 @@ pub mod fmls_za_zzi_h4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzi_h4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzi_h4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -108,6 +216,42 @@ pub mod bfmls_za_zzi_h4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_za_zzi_h4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmls_za_zzi_h4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_s.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_s.rs index 559267a6..c5d3c9cb 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_s.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_indexed_3/mortlach_multi4_zza_idx_s.rs @@ -12,6 +12,36 @@ pub mod fmla_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmla_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -42,6 +72,36 @@ pub mod fdot_za32_z8z8i_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za32_z8z8i_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za32_z8z8i_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -72,6 +132,36 @@ pub mod svdot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "svdot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn svdot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -102,6 +192,36 @@ pub mod usvdot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usvdot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usvdot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -132,6 +252,36 @@ pub mod sdot_za32_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za32_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za32_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -162,6 +312,36 @@ pub mod fdot_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fdot_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -192,6 +372,36 @@ pub mod bfdot_za_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_za_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfdot_za_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -222,6 +432,36 @@ pub mod sdot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sdot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -252,6 +492,36 @@ pub mod usdot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn usdot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -282,6 +552,36 @@ pub mod fmls_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn fmls_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -312,6 +612,36 @@ pub mod uvdot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uvdot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn uvdot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -342,6 +672,36 @@ pub mod suvdot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "suvdot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn suvdot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -372,6 +732,36 @@ pub mod udot_za32_zzi_4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za32_zzi_4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za32_zzi_4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -402,6 +792,36 @@ pub mod udot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn udot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, @@ -432,6 +852,36 @@ pub mod sudot_za_zzi_s4xi { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sudot_za_zzi_s4xi"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn sudot_za_zzi_s4xi( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_si_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_si_ctg.rs index 06d0d7ea..ed351ad9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_si_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_si_ctg.rs @@ -12,6 +12,30 @@ pub mod ld1b_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod ldnt1b_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1b_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,30 @@ pub mod ld1h_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1h_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -93,6 +165,30 @@ pub mod ldnt1h_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1h_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -120,6 +216,30 @@ pub mod ld1w_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1w_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -147,6 +267,30 @@ pub mod ldnt1w_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1w_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -174,6 +318,30 @@ pub mod ld1d_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1d_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -201,6 +369,30 @@ pub mod ldnt1d_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1d_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_ss_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_ss_ctg.rs index 76f08ecb..1a4bc54e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_ss_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cld_cldnt_ss_ctg.rs @@ -12,6 +12,30 @@ pub mod ld1b_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod ldnt1b_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1b_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod ld1h_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod ldnt1h_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1h_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -120,6 +216,30 @@ pub mod ld1w_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -147,6 +267,30 @@ pub mod ldnt1w_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1w_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -174,6 +318,30 @@ pub mod ld1d_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -201,6 +369,30 @@ pub mod ldnt1d_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1d_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_si_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_si_ctg.rs index 244cefe6..fa4adee3 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_si_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_si_ctg.rs @@ -12,6 +12,30 @@ pub mod st1b_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1b_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod stnt1b_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1b_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,30 @@ pub mod st1h_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1h_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -93,6 +165,30 @@ pub mod stnt1h_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1h_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -120,6 +216,30 @@ pub mod st1w_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1w_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -147,6 +267,30 @@ pub mod stnt1w_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1w_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -174,6 +318,30 @@ pub mod st1d_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1d_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, @@ -201,6 +369,30 @@ pub mod stnt1d_mz_p_bi_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mz_p_bi_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1d_mz_p_bi_2( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_ss_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_ss_ctg.rs index 3138c943..09d51c7a 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_ss_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi2_cst_cstnt_ss_ctg.rs @@ -12,6 +12,30 @@ pub mod st1b_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod stnt1b_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1b_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod st1h_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod stnt1h_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1h_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -120,6 +216,30 @@ pub mod st1w_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -147,6 +267,30 @@ pub mod stnt1w_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1w_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -174,6 +318,30 @@ pub mod st1d_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, @@ -201,6 +369,30 @@ pub mod stnt1d_mz_p_br_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mz_p_br_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1d_mz_p_br_2( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_si_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_si_ctg.rs index 07b7ac8a..a39fbf88 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_si_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_si_ctg.rs @@ -12,6 +12,30 @@ pub mod ld1b_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod ldnt1b_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1b_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,30 @@ pub mod ld1h_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1h_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -93,6 +165,30 @@ pub mod ldnt1h_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1h_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -120,6 +216,30 @@ pub mod ld1w_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1w_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -147,6 +267,30 @@ pub mod ldnt1w_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1w_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -174,6 +318,30 @@ pub mod ld1d_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1d_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -201,6 +369,30 @@ pub mod ldnt1d_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1d_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_ss_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_ss_ctg.rs index dd9cec2f..162d5db9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_ss_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cld_cldnt_ss_ctg.rs @@ -12,6 +12,30 @@ pub mod ld1b_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod ldnt1b_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1b_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod ld1h_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod ldnt1h_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1h_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -120,6 +216,30 @@ pub mod ld1w_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -147,6 +267,30 @@ pub mod ldnt1w_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1w_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -174,6 +318,30 @@ pub mod ld1d_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -201,6 +369,30 @@ pub mod ldnt1d_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1d_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_si_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_si_ctg.rs index be4be153..0408db5d 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_si_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_si_ctg.rs @@ -12,6 +12,30 @@ pub mod st1b_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1b_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod stnt1b_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1b_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,30 @@ pub mod st1h_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1h_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -93,6 +165,30 @@ pub mod stnt1h_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1h_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -120,6 +216,30 @@ pub mod st1w_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1w_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -147,6 +267,30 @@ pub mod stnt1w_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1w_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -174,6 +318,30 @@ pub mod st1d_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1d_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, @@ -201,6 +369,30 @@ pub mod stnt1d_mz_p_bi_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mz_p_bi_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1d_mz_p_bi_4( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_ss_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_ss_ctg.rs index 2dc64ce1..4199abaf 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_ss_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_ctg/mortlach_multi4_cst_cstnt_ss_ctg.rs @@ -12,6 +12,30 @@ pub mod st1b_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod stnt1b_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1b_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod st1h_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod stnt1h_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1h_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -120,6 +216,30 @@ pub mod st1w_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -147,6 +267,30 @@ pub mod stnt1w_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1w_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -174,6 +318,30 @@ pub mod st1d_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, @@ -201,6 +369,30 @@ pub mod stnt1d_mz_p_br_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mz_p_br_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1d_mz_p_br_4( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_si_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_si_nctg.rs index 4ebeee03..d4ca7d03 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_si_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_si_nctg.rs @@ -12,6 +12,36 @@ pub mod ld1b_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod ldnt1b_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1b_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,36 @@ pub mod ld1h_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1h_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -99,6 +189,36 @@ pub mod ldnt1h_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1h_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -128,6 +248,36 @@ pub mod ld1w_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1w_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -157,6 +307,36 @@ pub mod ldnt1w_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1w_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -186,6 +366,36 @@ pub mod ld1d_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1d_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -215,6 +425,36 @@ pub mod ldnt1d_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1d_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_ss_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_ss_nctg.rs index fc1390cc..095eb90f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_ss_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cld_cldnt_ss_nctg.rs @@ -12,6 +12,36 @@ pub mod ld1b_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod ldnt1b_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1b_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -70,6 +130,36 @@ pub mod ld1h_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -99,6 +189,36 @@ pub mod ldnt1h_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1h_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -128,6 +248,36 @@ pub mod ld1w_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -157,6 +307,36 @@ pub mod ldnt1w_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1w_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -186,6 +366,36 @@ pub mod ld1d_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -215,6 +425,36 @@ pub mod ldnt1d_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1d_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_si_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_si_nctg.rs index 4e45109a..34d2e627 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_si_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_si_nctg.rs @@ -12,6 +12,36 @@ pub mod st1b_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1b_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod stnt1b_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1b_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,36 @@ pub mod st1h_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1h_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -99,6 +189,36 @@ pub mod stnt1h_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1h_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -128,6 +248,36 @@ pub mod st1w_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1w_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -157,6 +307,36 @@ pub mod stnt1w_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1w_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -186,6 +366,36 @@ pub mod st1d_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1d_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, @@ -215,6 +425,36 @@ pub mod stnt1d_mzx_p_bi_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mzx_p_bi_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1d_mzx_p_bi_2x8( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_ss_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_ss_nctg.rs index ade4dd6c..ff0fb1dd 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_ss_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi2_cst_cstnt_ss_nctg.rs @@ -12,6 +12,36 @@ pub mod st1b_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod stnt1b_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1b_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -70,6 +130,36 @@ pub mod st1h_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -99,6 +189,36 @@ pub mod stnt1h_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1h_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -128,6 +248,36 @@ pub mod st1w_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -157,6 +307,36 @@ pub mod stnt1w_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1w_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -186,6 +366,36 @@ pub mod st1d_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, @@ -215,6 +425,36 @@ pub mod stnt1d_mzx_p_br_2x8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mzx_p_br_2x8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1d_mzx_p_br_2x8( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_si_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_si_nctg.rs index ca0c0e05..89d2eee1 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_si_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_si_nctg.rs @@ -12,6 +12,36 @@ pub mod ld1b_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod ldnt1b_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1b_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,36 @@ pub mod ld1h_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1h_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -99,6 +189,36 @@ pub mod ldnt1h_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1h_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -128,6 +248,36 @@ pub mod ld1w_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1w_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -157,6 +307,36 @@ pub mod ldnt1w_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1w_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -186,6 +366,36 @@ pub mod ld1d_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1d_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -215,6 +425,36 @@ pub mod ldnt1d_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1d_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_ss_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_ss_nctg.rs index b1c8eb42..f55c0fe6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_ss_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cld_cldnt_ss_nctg.rs @@ -12,6 +12,36 @@ pub mod ld1b_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod ldnt1b_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1b_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -70,6 +130,36 @@ pub mod ld1h_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -99,6 +189,36 @@ pub mod ldnt1h_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1h_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -128,6 +248,36 @@ pub mod ld1w_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -157,6 +307,36 @@ pub mod ldnt1w_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1w_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -186,6 +366,36 @@ pub mod ld1d_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -215,6 +425,36 @@ pub mod ldnt1d_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1d_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_si_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_si_nctg.rs index 88677ce0..2e2629bf 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_si_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_si_nctg.rs @@ -12,6 +12,36 @@ pub mod st1b_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1b_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod stnt1b_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1b_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,36 @@ pub mod st1h_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1h_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -99,6 +189,36 @@ pub mod stnt1h_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1h_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -128,6 +248,36 @@ pub mod st1w_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1w_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -157,6 +307,36 @@ pub mod stnt1w_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1w_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -186,6 +366,36 @@ pub mod st1d_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1d_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, @@ -215,6 +425,36 @@ pub mod stnt1d_mzx_p_bi_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mzx_p_bi_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1d_mzx_p_bi_4x4( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_ss_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_ss_nctg.rs index 941764c5..473cb714 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_ss_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_mem_nctg/mortlach_multi4_cst_cstnt_ss_nctg.rs @@ -12,6 +12,36 @@ pub mod st1b_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod stnt1b_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1b_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -70,6 +130,36 @@ pub mod st1h_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -99,6 +189,36 @@ pub mod stnt1h_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1h_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -128,6 +248,36 @@ pub mod st1w_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -157,6 +307,36 @@ pub mod stnt1w_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1w_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -186,6 +366,36 @@ pub mod st1d_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, @@ -215,6 +425,36 @@ pub mod stnt1d_mzx_p_br_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_mzx_p_br_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1d_mzx_p_br_4x4( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi2_select_int.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi2_select_int.rs index 07a66bab..a020f7b3 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi2_select_int.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi2_select_int.rs @@ -12,6 +12,36 @@ pub mod sel_mz_p_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sel_mz_p_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNv_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNv_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sel_mz_p_zz_2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi4_select_int.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi4_select_int.rs index ba6f0d12..36b39a60 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi4_select_int.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_1/mortlach_multi4_select_int.rs @@ -12,6 +12,36 @@ pub mod sel_mz_p_zz_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sel_mz_p_zz_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNv_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNv_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sel_mz_p_zz_4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_add_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_add_sm.rs index 339b3449..124e1578 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_add_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_add_sm.rs @@ -12,6 +12,24 @@ pub mod add_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn add_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fminmax_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fminmax_sm.rs index 6f1683e0..1ec6d8dd 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fminmax_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fminmax_sm.rs @@ -12,6 +12,24 @@ pub mod fmax_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmax_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmax_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfmax_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmax_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmax_mz_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -61,6 +91,24 @@ pub mod fmin_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmin_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmin_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -87,6 +135,18 @@ pub mod bfmin_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmin_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmin_mz_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -110,6 +170,24 @@ pub mod fmaxnm_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnm_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnm_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -136,6 +214,18 @@ pub mod bfmaxnm_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmaxnm_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmaxnm_mz_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -159,6 +249,24 @@ pub mod fminnm_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnm_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnm_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -185,6 +293,18 @@ pub mod bfminnm_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfminnm_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfminnm_mz_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fscale_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fscale_sm.rs index 1fea0d67..c988bc66 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fscale_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_fscale_sm.rs @@ -12,6 +12,24 @@ pub mod fscale_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fscale_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fscale_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfscale_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfscale_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfscale_mz_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_minmax_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_minmax_sm.rs index d6c09ef4..688948e2 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_minmax_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_minmax_sm.rs @@ -12,6 +12,24 @@ pub mod smax_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smax_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smax_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod smin_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smin_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smin_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +100,24 @@ pub mod umax_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umax_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umax_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +144,24 @@ pub mod umin_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umin_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umin_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_shift_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_shift_sm.rs index fbda0ac9..ac1315e7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_shift_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_shift_sm.rs @@ -12,6 +12,24 @@ pub mod srshl_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srshl_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn srshl_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod urshl_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urshl_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urshl_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_sqdmulh_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_sqdmulh_sm.rs index cc5632cf..2d341bf3 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_sqdmulh_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2a/mortlach_multi2_z_z_sqdmulh_sm.rs @@ -12,6 +12,24 @@ pub mod sqdmulh_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmulh_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_add_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_add_sm.rs index 7cfc82be..210b88ee 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_add_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_add_sm.rs @@ -12,6 +12,24 @@ pub mod add_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn add_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fminmax_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fminmax_sm.rs index 4f00b49c..6e184382 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fminmax_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fminmax_sm.rs @@ -12,6 +12,24 @@ pub mod fmax_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmax_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmax_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfmax_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmax_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmax_mz_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -61,6 +91,24 @@ pub mod fmin_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmin_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmin_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -87,6 +135,18 @@ pub mod bfmin_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmin_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmin_mz_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -110,6 +170,24 @@ pub mod fmaxnm_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnm_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnm_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -136,6 +214,18 @@ pub mod bfmaxnm_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmaxnm_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmaxnm_mz_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, @@ -159,6 +249,24 @@ pub mod fminnm_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnm_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnm_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -185,6 +293,18 @@ pub mod bfminnm_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfminnm_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfminnm_mz_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fscale_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fscale_sm.rs index e1e5241c..04c07517 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fscale_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_fscale_sm.rs @@ -12,6 +12,24 @@ pub mod fscale_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fscale_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fscale_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfscale_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfscale_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfscale_mz_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_minmax_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_minmax_sm.rs index 83677165..515e08b8 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_minmax_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_minmax_sm.rs @@ -12,6 +12,24 @@ pub mod smax_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smax_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smax_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod smin_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smin_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smin_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +100,24 @@ pub mod umax_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umax_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umax_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +144,24 @@ pub mod umin_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umin_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umin_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_shift_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_shift_sm.rs index cec45d2a..84e320bd 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_shift_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_shift_sm.rs @@ -12,6 +12,24 @@ pub mod srshl_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srshl_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn srshl_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod urshl_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urshl_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urshl_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_sqdmulh_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_sqdmulh_sm.rs index c2f75035..e5b8c680 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_sqdmulh_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2b/mortlach_multi4_z_z_sqdmulh_sm.rs @@ -12,6 +12,24 @@ pub mod sqdmulh_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmulh_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fminmax_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fminmax_mm.rs index 2fd19ade..dbd6ac7e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fminmax_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fminmax_mm.rs @@ -12,6 +12,24 @@ pub mod fmax_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmax_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmax_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfmax_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmax_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmax_mz_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -61,6 +91,24 @@ pub mod fmin_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmin_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmin_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -87,6 +135,18 @@ pub mod bfmin_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmin_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmin_mz_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -110,6 +170,24 @@ pub mod fmaxnm_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnm_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnm_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -136,6 +214,18 @@ pub mod bfmaxnm_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmaxnm_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmaxnm_mz_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -159,6 +249,24 @@ pub mod fminnm_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnm_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnm_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -185,6 +293,18 @@ pub mod bfminnm_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfminnm_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfminnm_mz_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, @@ -208,6 +328,24 @@ pub mod famax_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "famax_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn famax_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -234,6 +372,24 @@ pub mod famin_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "famin_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn famin_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fscale_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fscale_mm.rs index 8127448b..340079aa 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fscale_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_fscale_mm.rs @@ -12,6 +12,24 @@ pub mod fscale_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fscale_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fscale_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfscale_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfscale_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfscale_mz_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_minmax_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_minmax_mm.rs index 99dda602..adacf641 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_minmax_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_minmax_mm.rs @@ -12,6 +12,24 @@ pub mod smax_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smax_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smax_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod smin_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smin_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smin_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +100,24 @@ pub mod umax_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umax_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umax_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +144,24 @@ pub mod umin_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umin_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umin_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_shift_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_shift_mm.rs index e2b8cab3..e6e3aa40 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_shift_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c0/mortlach_multi2_z_z_shift_mm.rs @@ -12,6 +12,24 @@ pub mod srshl_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srshl_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn srshl_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod urshl_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urshl_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urshl_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c1/mortlach_multi2_z_z_sqdmulh_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c1/mortlach_multi2_z_z_sqdmulh_mm.rs index e5b4e1d0..81e375c6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c1/mortlach_multi2_z_z_sqdmulh_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2c1/mortlach_multi2_z_z_sqdmulh_mm.rs @@ -12,6 +12,24 @@ pub mod sqdmulh_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmulh_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fminmax_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fminmax_mm.rs index a8eebb3a..4e493d64 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fminmax_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fminmax_mm.rs @@ -12,6 +12,24 @@ pub mod fmax_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmax_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmax_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfmax_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmax_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmax_mz_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -61,6 +91,24 @@ pub mod fmin_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmin_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmin_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -87,6 +135,18 @@ pub mod bfmin_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmin_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmin_mz_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -110,6 +170,24 @@ pub mod fmaxnm_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnm_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnm_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -136,6 +214,18 @@ pub mod bfmaxnm_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmaxnm_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmaxnm_mz_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -159,6 +249,24 @@ pub mod fminnm_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnm_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnm_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -185,6 +293,18 @@ pub mod bfminnm_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfminnm_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfminnm_mz_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, @@ -208,6 +328,24 @@ pub mod famax_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "famax_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn famax_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -234,6 +372,24 @@ pub mod famin_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "famin_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn famin_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fscale_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fscale_mm.rs index de62ff24..b14aefb0 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fscale_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_fscale_mm.rs @@ -12,6 +12,24 @@ pub mod fscale_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fscale_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fscale_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,18 @@ pub mod bfscale_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfscale_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfscale_mz_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_minmax_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_minmax_mm.rs index d578201f..efcd0d24 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_minmax_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_minmax_mm.rs @@ -12,6 +12,24 @@ pub mod smax_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smax_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smax_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod smin_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smin_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smin_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +100,24 @@ pub mod umax_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umax_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umax_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +144,24 @@ pub mod umin_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umin_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umin_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_shift_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_shift_mm.rs index 82ab4f2c..b93cd45e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_shift_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d0/mortlach_multi4_z_z_shift_mm.rs @@ -12,6 +12,24 @@ pub mod srshl_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srshl_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn srshl_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod urshl_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urshl_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urshl_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d1/mortlach_multi4_z_z_sqdmulh_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d1/mortlach_multi4_z_z_sqdmulh_mm.rs index d91c5f11..8f35ad3e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d1/mortlach_multi4_z_z_sqdmulh_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_2d1/mortlach_multi4_z_z_sqdmulh_mm.rs @@ -12,6 +12,24 @@ pub mod sqdmulh_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmulh_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_clamp_int.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_clamp_int.rs index b4de6685..4fd78f0f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_clamp_int.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_clamp_int.rs @@ -12,6 +12,30 @@ pub mod sclamp_mz_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sclamp_mz_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sclamp_mz_zz_2( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod uclamp_mz_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uclamp_mz_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uclamp_mz_zz_2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_fclamp.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_fclamp.rs index d66f7707..ab9eecb6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_fclamp.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_fclamp.rs @@ -12,6 +12,30 @@ pub mod fclamp_mz_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fclamp_mz_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fclamp_mz_zz_2( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,24 @@ pub mod bfclamp_mz_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfclamp_mz_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfclamp_mz_zz_2( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_qrshr.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_qrshr.rs index 7a677bab..0bc44a52 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_qrshr.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_qrshr.rs @@ -12,6 +12,24 @@ pub mod sqrshr_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshr_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqrshr_z_mz2_( imm4: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,24 @@ pub mod sqrshru_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshru_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqrshru_z_mz2_( imm4: ::aarchmrs_types::BitValue<4>, @@ -62,6 +98,24 @@ pub mod uqrshr_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshr_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqrshr_z_mz2_( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_long_zip.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_long_zip.rs index cae1874a..87cedbfd 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_long_zip.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_long_zip.rs @@ -12,6 +12,24 @@ pub mod zip_mz_zz_2q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip_mz_zz_2q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn zip_mz_zz_2q( Zm: ::aarchmrs_types::BitValue<5>, @@ -37,6 +55,24 @@ pub mod uzp_mz_zz_2q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp_mz_zz_2q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn uzp_mz_zz_2q( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_zip.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_zip.rs index a0ad11e1..1baba1bf 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_zip.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi2_z_z_zip.rs @@ -12,6 +12,30 @@ pub mod zip_mz_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip_mz_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zip_mz_zz_2( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod uzp_mz_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp_mz_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzp_mz_zz_2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_clamp_int.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_clamp_int.rs index 0f870a29..15bd9a43 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_clamp_int.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_clamp_int.rs @@ -12,6 +12,30 @@ pub mod sclamp_mz_zz_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sclamp_mz_zz_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sclamp_mz_zz_4( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod uclamp_mz_zz_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uclamp_mz_zz_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uclamp_mz_zz_4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_fclamp.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_fclamp.rs index 58cae94e..e8aa42e6 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_fclamp.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_fclamp.rs @@ -12,6 +12,30 @@ pub mod fclamp_mz_zz_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fclamp_mz_zz_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fclamp_mz_zz_4( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,24 @@ pub mod bfclamp_mz_zz_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfclamp_mz_zz_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfclamp_mz_zz_4( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_qrshr.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_qrshr.rs index 74049581..5cdf1e4e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_qrshr.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_3/mortlach_multi4_qrshr.rs @@ -12,6 +12,30 @@ pub mod sqrshr_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshr_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn sqrshr_z_mz4_( tsize: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod sqrshru_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshru_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn sqrshru_z_mz4_( tsize: ::aarchmrs_types::BitValue<2>, @@ -68,6 +116,30 @@ pub mod sqrshrn_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrn_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn sqrshrn_z_mz4_( tsize: ::aarchmrs_types::BitValue<2>, @@ -96,6 +168,30 @@ pub mod sqrshrun_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrun_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn sqrshrun_z_mz4_( tsize: ::aarchmrs_types::BitValue<2>, @@ -124,6 +220,30 @@ pub mod uqrshr_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshr_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn uqrshr_z_mz4_( tsize: ::aarchmrs_types::BitValue<2>, @@ -152,6 +272,30 @@ pub mod uqrshrn_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshrn_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn uqrshrn_z_mz4_( tsize: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_fpint_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_fpint_cvrt.rs index df601fb0..617b4a2f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_fpint_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_fpint_cvrt.rs @@ -12,6 +12,18 @@ pub mod fcvtzs_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvtzs_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, @@ -35,6 +47,18 @@ pub mod fcvtzu_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvtzu_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_frint.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_frint.rs index 8e20a984..c26dfb9e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_frint.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_frint.rs @@ -12,6 +12,18 @@ pub mod frintn_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintn_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn frintn_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, @@ -35,6 +47,18 @@ pub mod frintp_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintp_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn frintp_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, @@ -58,6 +82,18 @@ pub mod frintm_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintm_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn frintm_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, @@ -81,6 +117,18 @@ pub mod frinta_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frinta_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn frinta_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_intfp_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_intfp_cvrt.rs index 999092dc..6e0bf413 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_intfp_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_intfp_cvrt.rs @@ -12,6 +12,18 @@ pub mod scvtf_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn scvtf_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, @@ -35,6 +47,18 @@ pub mod ucvtf_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn ucvtf_mz_z_2( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp8_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp8_cvrt.rs index 1bc18894..e7c9e591 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp8_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp8_cvrt.rs @@ -12,6 +12,18 @@ pub mod bfcvt_z8_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvt_z8_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn bfcvt_z8_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod fcvt_z8_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z8_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvt_z8_mz2_( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp_cvrt.rs index cc41f869..d8b36d10 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_fp_cvrt.rs @@ -12,6 +12,18 @@ pub mod bfcvt_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvt_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn bfcvt_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod fcvt_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvt_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -56,6 +80,18 @@ pub mod bfcvtn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvtn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn bfcvtn_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -78,6 +114,18 @@ pub mod fcvtn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvtn_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_int_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_int_cvrt.rs index cf81448d..03e9a208 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_int_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_narrow_int_cvrt.rs @@ -12,6 +12,18 @@ pub mod sqcvt_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvt_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn sqcvt_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod sqcvtu_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvtu_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn sqcvtu_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -56,6 +80,18 @@ pub mod uqcvt_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqcvt_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn uqcvt_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp8_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp8_cvrt.rs index d9f8dada..0508d27f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp8_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp8_cvrt.rs @@ -12,6 +12,18 @@ pub mod f1cvt_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f1cvt_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f1cvt_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, @@ -34,6 +46,18 @@ pub mod bf1cvt_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf1cvt_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf1cvt_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, @@ -56,6 +80,18 @@ pub mod f2cvt_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f2cvt_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f2cvt_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, @@ -78,6 +114,18 @@ pub mod bf2cvt_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf2cvt_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf2cvt_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, @@ -100,6 +148,18 @@ pub mod f1cvtl_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f1cvtl_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f1cvtl_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, @@ -122,6 +182,18 @@ pub mod bf1cvtl_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf1cvtl_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf1cvtl_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, @@ -144,6 +216,18 @@ pub mod f2cvtl_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f2cvtl_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f2cvtl_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, @@ -166,6 +250,18 @@ pub mod bf2cvtl_mz2_z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf2cvtl_mz2_z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf2cvtl_mz2_z8_( Zn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp_cvrt.rs index 139ad51c..43236e74 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_fp_cvrt.rs @@ -12,6 +12,18 @@ pub mod fcvt_mz2_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_mz2_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn fcvt_mz2_z_( Zn: ::aarchmrs_types::BitValue<5>, @@ -34,6 +46,18 @@ pub mod fcvtl_mz2_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtl_mz2_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn fcvtl_mz2_z_( Zn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_int.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_int.rs index e68f8a5f..d9560a6a 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_int.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi2_wide_int.rs @@ -12,6 +12,24 @@ pub mod sunpk_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sunpk_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sunpk_mz_z_2( size: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod uunpk_mz_z_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uunpk_mz_z_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uunpk_mz_z_2( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_fpint_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_fpint_cvrt.rs index 4879358d..537faeb2 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_fpint_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_fpint_cvrt.rs @@ -12,6 +12,18 @@ pub mod fcvtzs_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, @@ -35,6 +47,18 @@ pub mod fcvtzu_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_frint.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_frint.rs index 4ff4f1e0..513a1f65 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_frint.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_frint.rs @@ -12,6 +12,18 @@ pub mod frintn_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintn_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn frintn_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, @@ -35,6 +47,18 @@ pub mod frintp_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintp_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn frintp_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, @@ -58,6 +82,18 @@ pub mod frintm_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintm_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn frintm_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, @@ -81,6 +117,18 @@ pub mod frinta_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frinta_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn frinta_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_intfp_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_intfp_cvrt.rs index 2da8321f..d086f907 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_intfp_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_intfp_cvrt.rs @@ -12,6 +12,18 @@ pub mod scvtf_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, @@ -35,6 +47,18 @@ pub mod ucvtf_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_mz_z_4( Zn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_fp8_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_fp8_cvrt.rs index 528437b1..81664bc4 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_fp8_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_fp8_cvrt.rs @@ -12,6 +12,18 @@ pub mod fcvt_z8_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z8_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z8_mz4_( Zn: ::aarchmrs_types::BitValue<3>, @@ -34,6 +46,18 @@ pub mod fcvtn_z8_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtn_z8_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtn_z8_mz4_( Zn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_int_cvrt.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_int_cvrt.rs index 1010fa3a..a118ff8d 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_int_cvrt.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_narrow_int_cvrt.rs @@ -12,6 +12,24 @@ pub mod sqcvt_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvt_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sqcvt_z_mz4_( sz: ::aarchmrs_types::BitValue<1>, @@ -37,6 +55,24 @@ pub mod sqcvtu_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvtu_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sqcvtu_z_mz4_( sz: ::aarchmrs_types::BitValue<1>, @@ -62,6 +98,24 @@ pub mod sqcvtn_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvtn_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sqcvtn_z_mz4_( sz: ::aarchmrs_types::BitValue<1>, @@ -87,6 +141,24 @@ pub mod sqcvtun_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvtun_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sqcvtun_z_mz4_( sz: ::aarchmrs_types::BitValue<1>, @@ -112,6 +184,24 @@ pub mod uqcvt_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqcvt_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn uqcvt_z_mz4_( sz: ::aarchmrs_types::BitValue<1>, @@ -137,6 +227,24 @@ pub mod uqcvtn_z_mz4_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqcvtn_z_mz4_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn uqcvtn_z_mz4_( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_wide_int.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_wide_int.rs index 79b5300f..b1dc6100 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_wide_int.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_wide_int.rs @@ -12,6 +12,24 @@ pub mod sunpk_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sunpk_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sunpk_mz_z_4( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod uunpk_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uunpk_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uunpk_mz_z_4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_long_zip.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_long_zip.rs index fd1bd553..ca3682d9 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_long_zip.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_long_zip.rs @@ -12,6 +12,18 @@ pub mod zip_mz_z_4q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip_mz_z_4q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn zip_mz_z_4q( Zn: ::aarchmrs_types::BitValue<3>, @@ -35,6 +47,18 @@ pub mod uzp_mz_z_4q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp_mz_z_4q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn uzp_mz_z_4q( Zn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_zip.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_zip.rs index 5ccf96f1..ce0e8c6c 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_zip.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_4/mortlach_multi4_z_z_zip.rs @@ -12,6 +12,24 @@ pub mod zip_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zip_mz_z_4( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +56,24 @@ pub mod uzp_mz_z_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp_mz_z_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzp_mz_z_4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi2_fmul_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi2_fmul_mm.rs index 218bd376..dcae682b 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi2_fmul_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi2_fmul_mm.rs @@ -12,6 +12,30 @@ pub mod fmul_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_mz_zzw_2x2( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +65,24 @@ pub mod bfmul_mz_zzw_2x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmul_mz_zzw_2x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmul_mz_zzw_2x2( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi4_fmul_mm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi4_fmul_mm.rs index f12d79c4..90d29c6f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi4_fmul_mm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5a/mortlach_multi4_fmul_mm.rs @@ -12,6 +12,30 @@ pub mod fmul_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_mz_zzw_4x4( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +65,24 @@ pub mod bfmul_mz_zzw_4x4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmul_mz_zzw_4x4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; #[inline] pub const fn bfmul_mz_zzw_4x4( Zm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi2_fmul_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi2_fmul_sm.rs index 78123137..9c069bd7 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi2_fmul_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi2_fmul_sm.rs @@ -12,6 +12,30 @@ pub mod fmul_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_mz_zzv_2x1( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +65,24 @@ pub mod bfmul_mz_zzv_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmul_mz_zzv_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmul_mz_zzv_2x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi4_fmul_sm.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi4_fmul_sm.rs index 9d27f5d4..917bb380 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi4_fmul_sm.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_5b/mortlach_multi4_fmul_sm.rs @@ -12,6 +12,30 @@ pub mod fmul_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_mz_zzv_4x1( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +65,24 @@ pub mod bfmul_mz_zzv_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmul_mz_zzv_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; #[inline] pub const fn bfmul_mz_zzv_4x1( Zm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_ctg.rs index 7ca69311..26a35833 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_ctg.rs @@ -12,6 +12,30 @@ pub mod luti6_mz4_zmz2_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti6_mz4_zmz2_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn luti6_mz4_zmz2_1( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_nctg.rs index d2d8fdb1..1a0bd331 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multi_sve_6/mortlach_multi4_lut6_16_nctg.rs @@ -12,6 +12,36 @@ pub mod luti6_mz4_zmz2_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti6_mz4_zmz2_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn luti6_mz4_zmz2_4( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_multizero/mortlach_multi_zero.rs b/aarchmrs-instructions/src/A64/sme/mortlach_multizero/mortlach_multi_zero.rs index 23f2008f..5434349f 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_multizero/mortlach_multi_zero.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_multizero/mortlach_multi_zero.rs @@ -12,6 +12,18 @@ pub mod zero_za1_ri_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za1_ri_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za1_ri_2( Rv: ::aarchmrs_types::BitValue<2>, @@ -34,6 +46,18 @@ pub mod zero_za1_ri_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za1_ri_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za1_ri_4( Rv: ::aarchmrs_types::BitValue<2>, @@ -56,6 +80,18 @@ pub mod zero_za2_ri_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za2_ri_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za2_ri_1( Rv: ::aarchmrs_types::BitValue<2>, @@ -78,6 +114,18 @@ pub mod zero_za2_ri_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za2_ri_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za2_ri_2( Rv: ::aarchmrs_types::BitValue<2>, @@ -100,6 +148,18 @@ pub mod zero_za2_ri_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za2_ri_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za2_ri_4( Rv: ::aarchmrs_types::BitValue<2>, @@ -122,6 +182,18 @@ pub mod zero_za4_ri_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za4_ri_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_off2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za4_ri_1( Rv: ::aarchmrs_types::BitValue<2>, @@ -144,6 +216,18 @@ pub mod zero_za4_ri_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za4_ri_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za4_ri_2( Rv: ::aarchmrs_types::BitValue<2>, @@ -166,6 +250,18 @@ pub mod zero_za4_ri_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za4_ri_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_o1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; #[inline] pub const fn zero_za4_ri_4( Rv: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zero/mortlach_zero.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zero/mortlach_zero.rs index 9244f517..305c629d 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zero/mortlach_zero.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zero/mortlach_zero.rs @@ -12,6 +12,12 @@ pub mod zero_za_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zero_za_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn zero_za_i_( imm8: ::aarchmrs_types::BitValue<8>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_1dst.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_1dst.rs index a8eff2c1..6805257e 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_1dst.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_1dst.rs @@ -12,6 +12,30 @@ pub mod luti2_z_ztz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti2_z_ztz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4_WIDTH: u32 = 4u32; #[inline] pub const fn luti2_z_ztz_( i4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod luti4_z_ztz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_z_ztz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3_WIDTH: u32 = 3u32; #[inline] pub const fn luti4_z_ztz_( i3: ::aarchmrs_types::BitValue<3>, @@ -64,6 +112,18 @@ pub mod luti6_z_ztz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti6_z_ztz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn luti6_z_ztz_( Zn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_2dst_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_2dst_ctg.rs index d8ebcb43..0a0f6115 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_2dst_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_2dst_ctg.rs @@ -12,6 +12,30 @@ pub mod luti2_mz2_ztz_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti2_mz2_ztz_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3_WIDTH: u32 = 3u32; #[inline] pub const fn luti2_mz2_ztz_1( i3: ::aarchmrs_types::BitValue<3>, @@ -40,6 +64,30 @@ pub mod luti4_mz2_ztz_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_mz2_ztz_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn luti4_mz2_ztz_1( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst2src_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst2src_ctg.rs index 5a081a29..697fde70 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst2src_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst2src_ctg.rs @@ -12,6 +12,24 @@ pub mod luti4_mz4_ztmz2_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_mz4_ztmz2_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn luti4_mz4_ztmz2_1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst3src_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst3src_ctg.rs index c169a316..1ca7cdbb 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst3src_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst3src_ctg.rs @@ -12,6 +12,18 @@ pub mod luti6_mz4_ztmz3_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti6_mz4_ztmz3_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn luti6_mz4_ztmz3_1( Zn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst_ctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst_ctg.rs index f712a3ff..dd062dde 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst_ctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_ctg/mortlach_expand_4dst_ctg.rs @@ -12,6 +12,30 @@ pub mod luti2_mz4_ztz_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti2_mz4_ztz_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn luti2_mz4_ztz_1( i2: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod luti4_mz4_ztz_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_mz4_ztz_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn luti4_mz4_ztz_1( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_2dst_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_2dst_nctg.rs index 54b8ad86..0aa2f2f0 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_2dst_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_2dst_nctg.rs @@ -12,6 +12,36 @@ pub mod luti2_mz2_ztz_8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti2_mz2_ztz_8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3_WIDTH: u32 = 3u32; #[inline] pub const fn luti2_mz2_ztz_8( i3: ::aarchmrs_types::BitValue<3>, @@ -42,6 +72,36 @@ pub mod luti4_mz2_ztz_8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_mz2_ztz_8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn luti4_mz2_ztz_8( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst2src_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst2src_nctg.rs index 28268deb..5e72a2cd 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst2src_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst2src_nctg.rs @@ -12,6 +12,30 @@ pub mod luti4_mz4_ztmz2_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_mz4_ztmz2_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn luti4_mz4_ztmz2_4( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst3src_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst3src_nctg.rs index cb7fa11c..ec5cbb34 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst3src_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst3src_nctg.rs @@ -12,6 +12,24 @@ pub mod luti6_mz4_ztmz3_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti6_mz4_ztmz3_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 3u32; #[inline] pub const fn luti6_mz4_ztmz3_4( Zn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst_nctg.rs b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst_nctg.rs index 7ec5011e..6e123a79 100644 --- a/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst_nctg.rs +++ b/aarchmrs-instructions/src/A64/sme/mortlach_zt_expand_nctg/mortlach_expand_4dst_nctg.rs @@ -12,6 +12,36 @@ pub mod luti2_mz4_ztz_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti2_mz4_ztz_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn luti2_mz4_ztz_4( i2: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,36 @@ pub mod luti4_mz4_ztz_4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_mz4_ztz_4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn luti4_mz4_ztz_4( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_abal/sve_abal.rs b/aarchmrs-instructions/src/A64/sve/sve_abal/sve_abal.rs index 376444eb..90ebffa6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_abal/sve_abal.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_abal/sve_abal.rs @@ -12,6 +12,30 @@ pub mod sabal_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sabal_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sabal_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod uabal_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uabal_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uabal_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_svl.rs b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_svl.rs index 6a3ae08b..7781490f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_svl.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_svl.rs @@ -12,6 +12,24 @@ pub mod addsvl_r_ri_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addsvl_r_ri_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn addsvl_r_ri_( Rn: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod addspl_r_ri_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addspl_r_ri_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn addspl_r_ri_( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_vl.rs b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_vl.rs index f623e965..99b5b0d5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_vl.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_arith_vl.rs @@ -12,6 +12,24 @@ pub mod addvl_r_ri_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addvl_r_ri_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn addvl_r_ri_( Rn: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod addpl_r_ri_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addpl_r_ri_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; #[inline] pub const fn addpl_r_ri_( Rn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_svl_a.rs b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_svl_a.rs index 8279b263..ad0bf7a9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_svl_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_svl_a.rs @@ -12,6 +12,18 @@ pub mod rdsvl_r_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rdsvl_r_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn rdsvl_r_i_( imm6: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_vl_a.rs b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_vl_a.rs index 8e2a317e..d62f747a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_vl_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_alloca/sve_int_read_vl_a.rs @@ -12,6 +12,18 @@ pub mod rdvl_r_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rdvl_r_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn rdvl_r_i_( imm6: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_cterm.rs b/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_cterm.rs index a53f68ae..5bf96f2e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_cterm.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_cterm.rs @@ -12,6 +12,24 @@ pub mod ctermeq_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ctermeq_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn ctermeq_rr_( sz: ::aarchmrs_types::BitValue<1>, @@ -38,6 +56,24 @@ pub mod ctermne_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ctermne_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn ctermne_rr_( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_while_rr.rs b/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_while_rr.rs index 0228b06a..ced1c412 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_while_rr.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_while_rr.rs @@ -12,6 +12,36 @@ pub mod whilege_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilege_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilege_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -43,6 +73,36 @@ pub mod whilehs_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilehs_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilehs_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -74,6 +134,36 @@ pub mod whilegt_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilegt_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilegt_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -105,6 +195,36 @@ pub mod whilehi_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilehi_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilehi_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -136,6 +256,36 @@ pub mod whilelt_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilelt_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilelt_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -167,6 +317,36 @@ pub mod whilelo_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilelo_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilelo_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -198,6 +378,36 @@ pub mod whilele_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilele_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilele_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -229,6 +439,36 @@ pub mod whilels_p_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilels_p_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sf_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilels_p_p_rr_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_whilenc.rs b/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_whilenc.rs index 966f74d2..c628eaa7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_whilenc.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_cmpgpr/sve_int_whilenc.rs @@ -12,6 +12,30 @@ pub mod whilewr_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilewr_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilewr_p_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod whilerw_p_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilerw_p_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilerw_p_rr_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_cmpsimm/sve_int_scmp_vi.rs b/aarchmrs-instructions/src/A64/sve/sve_cmpsimm/sve_int_scmp_vi.rs index 4edd8ad2..95e640af 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_cmpsimm/sve_int_scmp_vi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_cmpsimm/sve_int_scmp_vi.rs @@ -12,6 +12,36 @@ pub mod cmpge_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpge_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpge_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,36 @@ pub mod cmpeq_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpeq_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpeq_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -72,6 +132,36 @@ pub mod cmplt_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmplt_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmplt_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -102,6 +192,36 @@ pub mod cmpgt_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpgt_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpgt_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -132,6 +252,36 @@ pub mod cmpne_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpne_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpne_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -162,6 +312,36 @@ pub mod cmple_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmple_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmple_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_cmpuimm/sve_int_ucmp_vi.rs b/aarchmrs-instructions/src/A64/sve/sve_cmpuimm/sve_int_ucmp_vi.rs index c7788643..c07e6cd6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_cmpuimm/sve_int_ucmp_vi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_cmpuimm/sve_int_ucmp_vi.rs @@ -12,6 +12,36 @@ pub mod cmphs_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmphs_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmphs_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,36 @@ pub mod cmphi_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmphi_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmphi_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -72,6 +132,36 @@ pub mod cmplo_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmplo_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmplo_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -102,6 +192,36 @@ pub mod cmpls_p_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpls_p_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpls_p_p_zi_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_0.rs b/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_0.rs index 26df25f9..00bf730a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_0.rs @@ -12,6 +12,36 @@ pub mod cmphs_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmphs_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmphs_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,36 @@ pub mod cmpge_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpge_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpge_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -72,6 +132,36 @@ pub mod cmpeq_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpeq_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpeq_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -102,6 +192,36 @@ pub mod cmpeq_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpeq_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpeq_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -132,6 +252,36 @@ pub mod cmphi_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmphi_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmphi_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -162,6 +312,36 @@ pub mod cmpgt_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpgt_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpgt_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -192,6 +372,36 @@ pub mod cmpne_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpne_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpne_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -222,6 +432,36 @@ pub mod cmpne_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpne_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpne_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_1.rs b/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_1.rs index 3bef4778..f19c5c8e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_cmpvec/sve_int_cmp_1.rs @@ -12,6 +12,36 @@ pub mod cmpge_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpge_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpge_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,36 @@ pub mod cmphs_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmphs_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmphs_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -72,6 +132,36 @@ pub mod cmpgt_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpgt_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpgt_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -102,6 +192,36 @@ pub mod cmphi_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmphi_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmphi_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -132,6 +252,36 @@ pub mod cmplt_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmplt_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmplt_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -162,6 +312,36 @@ pub mod cmplo_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmplo_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmplo_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -192,6 +372,36 @@ pub mod cmple_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmple_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmple_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -222,6 +432,36 @@ pub mod cmpls_p_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmpls_p_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmpls_p_p_zw_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_count.rs b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_count.rs index 313294eb..c3226d58 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_count.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_count.rs @@ -12,6 +12,24 @@ pub mod cntb_r_s_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cntb_r_s_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn cntb_r_s_( imm4: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod cnth_r_s_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cnth_r_s_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn cnth_r_s_( imm4: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod cntw_r_s_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cntw_r_s_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn cntw_r_s_( imm4: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod cntd_r_s_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cntd_r_s_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn cntd_r_s_( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv0.rs b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv0.rs index 4a245e3c..1089f58e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv0.rs @@ -12,6 +12,24 @@ pub mod sqinch_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqinch_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqinch_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod sqdech_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdech_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdech_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod uqinch_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqinch_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqinch_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod uqdech_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdech_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdech_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -108,6 +180,24 @@ pub mod sqincw_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincw_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincw_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -132,6 +222,24 @@ pub mod sqdecw_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecw_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecw_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -156,6 +264,24 @@ pub mod uqincw_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincw_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincw_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -180,6 +306,24 @@ pub mod uqdecw_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecw_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecw_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -204,6 +348,24 @@ pub mod sqincd_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincd_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincd_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -228,6 +390,24 @@ pub mod sqdecd_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecd_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecd_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -252,6 +432,24 @@ pub mod uqincd_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincd_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincd_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -276,6 +474,24 @@ pub mod uqdecd_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecd_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecd_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv1.rs b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv1.rs index 4f815006..559d511c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_countvlv1.rs @@ -12,6 +12,24 @@ pub mod inch_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "inch_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn inch_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod dech_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "dech_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn dech_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod incw_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "incw_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn incw_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod decw_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "decw_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn decw_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -108,6 +180,24 @@ pub mod incd_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "incd_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn incd_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -132,6 +222,24 @@ pub mod decd_z_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "decd_z_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn decd_z_zs_( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_a.rs b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_a.rs index 88bb24c8..f55ab52d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_a.rs @@ -12,6 +12,24 @@ pub mod incb_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "incb_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn incb_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod decb_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "decb_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn decb_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod inch_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "inch_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn inch_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod dech_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "dech_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn dech_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -108,6 +180,24 @@ pub mod incw_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "incw_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn incw_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -132,6 +222,24 @@ pub mod decw_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "decw_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn decw_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -156,6 +264,24 @@ pub mod incd_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "incd_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn incd_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, @@ -180,6 +306,24 @@ pub mod decd_r_rs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "decd_r_rs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn decd_r_rs_( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_b.rs b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_b.rs index 6aa23245..e309cc35 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_countelt/sve_int_pred_pattern_b.rs @@ -12,6 +12,24 @@ pub mod sqincb_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincb_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincb_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod uqincb_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincb_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincb_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod sqdecb_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecb_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecb_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod uqdecb_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecb_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecb_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -108,6 +180,24 @@ pub mod sqincb_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincb_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincb_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -132,6 +222,24 @@ pub mod sqdecb_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecb_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecb_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -156,6 +264,24 @@ pub mod sqinch_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqinch_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqinch_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -180,6 +306,24 @@ pub mod uqinch_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqinch_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqinch_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -204,6 +348,24 @@ pub mod sqdech_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdech_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdech_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -228,6 +390,24 @@ pub mod uqdech_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdech_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdech_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -252,6 +432,24 @@ pub mod sqinch_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqinch_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqinch_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -276,6 +474,24 @@ pub mod sqdech_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdech_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdech_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -300,6 +516,24 @@ pub mod sqincw_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincw_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincw_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -324,6 +558,24 @@ pub mod uqincw_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincw_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincw_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -348,6 +600,24 @@ pub mod sqdecw_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecw_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecw_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -372,6 +642,24 @@ pub mod uqdecw_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecw_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecw_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -396,6 +684,24 @@ pub mod sqincw_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincw_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincw_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -420,6 +726,24 @@ pub mod sqdecw_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecw_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecw_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -444,6 +768,24 @@ pub mod sqincd_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincd_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincd_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -468,6 +810,24 @@ pub mod uqincd_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincd_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincd_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -492,6 +852,24 @@ pub mod sqdecd_r_rs_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecd_r_rs_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecd_r_rs_sx( imm4: ::aarchmrs_types::BitValue<4>, @@ -516,6 +894,24 @@ pub mod uqdecd_r_rs_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecd_r_rs_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecd_r_rs_uw( imm4: ::aarchmrs_types::BitValue<4>, @@ -540,6 +936,24 @@ pub mod sqincd_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincd_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqincd_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -564,6 +978,24 @@ pub mod sqdecd_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecd_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqdecd_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -588,6 +1020,24 @@ pub mod uqincb_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincb_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincb_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -612,6 +1062,24 @@ pub mod uqdecb_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecb_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecb_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -636,6 +1104,24 @@ pub mod uqinch_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqinch_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqinch_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -660,6 +1146,24 @@ pub mod uqdech_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdech_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdech_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -684,6 +1188,24 @@ pub mod uqincw_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincw_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincw_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -708,6 +1230,24 @@ pub mod uqdecw_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecw_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecw_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -732,6 +1272,24 @@ pub mod uqincd_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincd_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqincd_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, @@ -756,6 +1314,24 @@ pub mod uqdecd_r_rs_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecd_r_rs_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqdecd_r_rs_x( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long.rs b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long.rs index 192e2649..593a8130 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long.rs @@ -12,6 +12,24 @@ pub mod fmlalb_z_z8z8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalb_z_z8z8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlalb_z_z8z8z8_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod fmlalt_z_z8z8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalt_z_z8z8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlalt_z_z8z8z8_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long_long.rs b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long_long.rs index a1f0befc..08dd4d04 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w/sve_fp8_fma_long_long.rs @@ -12,6 +12,24 @@ pub mod fmlallbb_z32_z8z8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlallbb_z32_z8z8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlallbb_z32_z8z8z8_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod fmlallbt_z32_z8z8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlallbt_z32_z8z8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlallbt_z32_z8z8z8_( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod fmlalltb_z32_z8z8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalltb_z32_z8z8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlalltb_z32_z8z8z8_( Zm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod fmlalltt_z32_z8z8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalltt_z32_z8z8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlalltt_z32_z8z8z8_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w_by_indexed_elem/sve_fp8_fma_long_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w_by_indexed_elem/sve_fp8_fma_long_by_indexed_elem.rs index 480f40c1..52cc0083 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w_by_indexed_elem/sve_fp8_fma_long_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_w_by_indexed_elem/sve_fp8_fma_long_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod fmlalb_z_z8z8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalb_z_z8z8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlalb_z_z8z8z8i_( i4h: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod fmlalt_z_z8z8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalt_z_z8z8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlalt_z_z8z8z8i_( i4h: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_ww_by_indexed_elem/sve_fp8_fma_long_long_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_ww_by_indexed_elem/sve_fp8_fma_long_long_by_indexed_elem.rs index eabaafea..d4ba19ce 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_ww_by_indexed_elem/sve_fp8_fma_long_long_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp8_fma_ww_by_indexed_elem/sve_fp8_fma_long_long_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod fmlallbb_z32_z8z8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlallbb_z32_z8z8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlallbb_z32_z8z8z8i_( i4h: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod fmlallbt_z32_z8z8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlallbt_z32_z8z8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlallbt_z32_z8z8z8i_( i4h: ::aarchmrs_types::BitValue<2>, @@ -68,6 +128,36 @@ pub mod fmlalltb_z32_z8z8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalltb_z32_z8z8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlalltb_z32_z8z8z8i_( i4h: ::aarchmrs_types::BitValue<2>, @@ -96,6 +186,36 @@ pub mod fmlalltt_z32_z8z8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalltt_z32_z8z8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i4h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlalltt_z32_z8z8z8i_( i4h: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp8_fmmla/sve_fp8_fmmla.rs b/aarchmrs-instructions/src/A64/sve/sve_fp8_fmmla/sve_fp8_fmmla.rs index ad375cca..ee432ef9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp8_fmmla/sve_fp8_fmmla.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp8_fmmla/sve_fp8_fmmla.rs @@ -12,6 +12,24 @@ pub mod fmmla_z32_zz8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmmla_z32_zz8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmmla_z32_zz8z8_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod fmmla_z16_zz8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmmla_z16_zz8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmmla_z16_zz8z8_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_clamp/sve_fp_clamp.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_clamp/sve_fp_clamp.rs index e2f1a6fe..91b51579 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_clamp/sve_fp_clamp.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_clamp/sve_fp_clamp.rs @@ -12,6 +12,30 @@ pub mod fclamp_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fclamp_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fclamp_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,24 @@ pub mod bfclamp_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfclamp_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfclamp_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_cmpvev/sve_fp_3op_p_pd.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_cmpvev/sve_fp_3op_p_pd.rs index 416368cf..b9b08071 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_cmpvev/sve_fp_3op_p_pd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_cmpvev/sve_fp_3op_p_pd.rs @@ -12,6 +12,36 @@ pub mod fcmge_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmge_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmge_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,36 @@ pub mod fcmuo_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmuo_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmuo_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -72,6 +132,36 @@ pub mod facge_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "facge_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn facge_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -102,6 +192,36 @@ pub mod facgt_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "facgt_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn facgt_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -132,6 +252,36 @@ pub mod fcmgt_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmgt_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmgt_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -162,6 +312,36 @@ pub mod fcmeq_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmeq_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmeq_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -192,6 +372,36 @@ pub mod fcmne_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmne_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmne_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_cmpzero/sve_fp_2op_p_pd.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_cmpzero/sve_fp_2op_p_pd.rs index 19d2f4d1..4529818a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_cmpzero/sve_fp_2op_p_pd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_cmpzero/sve_fp_2op_p_pd.rs @@ -12,6 +12,30 @@ pub mod fcmge_p_p_z0_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmge_p_p_z0_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmge_p_p_z0_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod fcmeq_p_p_z0_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmeq_p_p_z0_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmeq_p_p_z0_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod fcmgt_p_p_z0_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmgt_p_p_z0_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmgt_p_p_z0_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod fcmlt_p_p_z0_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmlt_p_p_z0_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmlt_p_p_z0_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod fcmne_p_p_z0_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmne_p_p_z0_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmne_p_p_z0_( size: ::aarchmrs_types::BitValue<2>, @@ -147,6 +267,30 @@ pub mod fcmle_p_p_z0_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmle_p_p_z0_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmle_p_p_z0_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduce/sve_fp_fast_red.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduce/sve_fp_fast_red.rs index 709241cc..a4dbced4 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduce/sve_fp_fast_red.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduce/sve_fp_fast_red.rs @@ -12,6 +12,30 @@ pub mod faddv_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "faddv_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn faddv_v_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod fmaxnmv_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnmv_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnmv_v_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod fminnmv_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnmv_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnmv_v_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod fmaxv_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxv_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxv_v_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod fminv_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminv_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminv_v_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduceq/sve_fp_fast_redq.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduceq/sve_fp_fast_redq.rs index d1f5a64b..d9202ba2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduceq/sve_fp_fast_redq.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fastreduceq/sve_fp_fast_redq.rs @@ -12,6 +12,30 @@ pub mod faddqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "faddqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn faddqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod fmaxnmqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnmqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnmqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod fminnmqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnmqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnmqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod fmaxqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod fminqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fcadd/sve_fp_fcadd.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fcadd/sve_fp_fcadd.rs index 05472a26..339cb0b1 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fcadd/sve_fp_fcadd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fcadd/sve_fp_fcadd.rs @@ -12,6 +12,36 @@ pub mod fcadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla/sve_fp_fcmla.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla/sve_fp_fcmla.rs index 4c54ec64..aff24aea 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla/sve_fp_fcmla.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla/sve_fp_fcmla.rs @@ -12,6 +12,42 @@ pub mod fcmla_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmla_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcmla_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla_by_indexed_elem/sve_fp_fcmla_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla_by_indexed_elem/sve_fp_fcmla_by_indexed_elem.rs index e9d7dfe9..c6530dc3 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla_by_indexed_elem/sve_fp_fcmla_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fcmla_by_indexed_elem/sve_fp_fcmla_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod fcmla_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmla_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn fcmla_z_zzzi_h( i2: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod fcmla_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcmla_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn fcmla_z_zzzi_s( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2/sve_fp_fcvt2.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2/sve_fp_fcvt2.rs index bc3bab5d..ffcd2495 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2/sve_fp_fcvt2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2/sve_fp_fcvt2.rs @@ -12,6 +12,24 @@ pub mod fcvtxnt_z_p_z_d2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtxnt_z_p_z_d2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtxnt_z_p_z_d2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod fcvtnt_z_p_z_s2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtnt_z_p_z_s2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtnt_z_p_z_s2h( Pg: ::aarchmrs_types::BitValue<3>, @@ -58,6 +94,24 @@ pub mod fcvtlt_z_p_z_h2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtlt_z_p_z_h2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtlt_z_p_z_h2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -81,6 +135,24 @@ pub mod bfcvtnt_z_p_z_s2bf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvtnt_z_p_z_s2bf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfcvtnt_z_p_z_s2bf( Pg: ::aarchmrs_types::BitValue<3>, @@ -104,6 +176,24 @@ pub mod fcvtnt_z_p_z_d2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtnt_z_p_z_d2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtnt_z_p_z_d2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -127,6 +217,24 @@ pub mod fcvtlt_z_p_z_s2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtlt_z_p_z_s2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtlt_z_p_z_s2d( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2z/sve_fp_fcvt2z.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2z/sve_fp_fcvt2z.rs index 5c3b2c22..4e96f88a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2z/sve_fp_fcvt2z.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fcvt2z/sve_fp_fcvt2z.rs @@ -12,6 +12,24 @@ pub mod fcvtxnt_z_p_z_d2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtxnt_z_p_z_d2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtxnt_z_p_z_d2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod fcvtnt_z_p_z_s2hz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtnt_z_p_z_s2hz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtnt_z_p_z_s2hz( Pg: ::aarchmrs_types::BitValue<3>, @@ -58,6 +94,24 @@ pub mod fcvtlt_z_p_z_h2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtlt_z_p_z_h2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtlt_z_p_z_h2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -81,6 +135,24 @@ pub mod bfcvtnt_z_p_z_s2bfz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvtnt_z_p_z_s2bfz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfcvtnt_z_p_z_s2bfz( Pg: ::aarchmrs_types::BitValue<3>, @@ -104,6 +176,24 @@ pub mod fcvtnt_z_p_z_d2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtnt_z_p_z_d2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtnt_z_p_z_d2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -127,6 +217,24 @@ pub mod fcvtlt_z_p_z_s2dz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtlt_z_p_z_s2dz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtlt_z_p_z_s2dz( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_a.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_a.rs index 432fdde0..f60f9612 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_a.rs @@ -12,6 +12,36 @@ pub mod fmla_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmla_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,30 @@ pub mod bfmla_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmla_z_p_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -67,6 +121,36 @@ pub mod fmls_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmls_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -96,6 +180,30 @@ pub mod bfmls_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmls_z_p_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -122,6 +230,36 @@ pub mod fnmla_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fnmla_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fnmla_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -151,6 +289,36 @@ pub mod fnmls_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fnmls_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fnmls_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_b.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_b.rs index 94ad4a1c..8d81e41f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fma/sve_fp_3op_p_zds_b.rs @@ -12,6 +12,36 @@ pub mod fmad_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmad_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmad_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod fmsb_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmsb_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmsb_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -70,6 +130,36 @@ pub mod fnmad_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fnmad_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fnmad_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -99,6 +189,36 @@ pub mod fnmsb_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fnmsb_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fnmsb_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_by_indexed_elem/sve_fp_fma_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_by_indexed_elem/sve_fp_fma_by_indexed_elem.rs index 8e76fd05..2918b7ca 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_by_indexed_elem/sve_fp_fma_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_by_indexed_elem/sve_fp_fma_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod fmla_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn fmla_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod bfmla_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmla_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn bfmla_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,30 @@ pub mod fmla_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn fmla_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -96,6 +180,30 @@ pub mod fmla_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmla_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn fmla_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, @@ -122,6 +230,36 @@ pub mod fmls_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn fmls_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -151,6 +289,36 @@ pub mod bfmls_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmls_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn bfmls_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -180,6 +348,30 @@ pub mod fmls_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn fmls_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -206,6 +398,30 @@ pub mod fmls_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmls_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn fmls_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fdot.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fdot.rs index e52ce163..f55b8c7a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fdot.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fdot.rs @@ -12,6 +12,24 @@ pub mod fdot_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fdot_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod bfdot_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfdot_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod fdot_z_zz8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_z_zz8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fdot_z_zz8z8_( Zm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod fdot_z32_zz8z8_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_z32_zz8z8_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fdot_z32_zz8z8_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fma_long.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fma_long.rs index fe62902e..a8791875 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fma_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w/sve_fp_fma_long.rs @@ -12,6 +12,24 @@ pub mod fmlalb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlalb_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod bfmlalb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlalb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmlalb_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod fmlslb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlslb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlslb_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod bfmlslb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlslb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmlslb_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod fmlalt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlalt_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod bfmlalt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlalt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmlalt_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -156,6 +264,24 @@ pub mod fmlslt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlslt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmlslt_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -180,6 +306,24 @@ pub mod bfmlslt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlslt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmlslt_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fdot_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fdot_by_indexed_elem.rs index 0edcb44c..69893645 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fdot_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fdot_by_indexed_elem.rs @@ -12,6 +12,30 @@ pub mod fdot_z_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_z_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn fdot_z_zzzi_( i2: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod bfdot_z_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfdot_z_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn bfdot_z_zzzi_( i2: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,36 @@ pub mod fdot_z_zz8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_z_zz8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn fdot_z_zz8z8i_( i3h: ::aarchmrs_types::BitValue<2>, @@ -93,6 +171,30 @@ pub mod fdot_z32_zz8z8i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdot_z32_zz8z8i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn fdot_z32_zz8z8i_( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fma_long_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fma_long_by_indexed_elem.rs index 90586ef7..1d59f32d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fma_long_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fma_w_by_indexed_elem/sve_fp_fma_long_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod fmlalb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlalb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod bfmlalb_z_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlalb_z_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn bfmlalb_z_zzzi_( i3h: ::aarchmrs_types::BitValue<2>, @@ -70,6 +130,36 @@ pub mod fmlslb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlslb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlslb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -99,6 +189,36 @@ pub mod bfmlslb_z_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlslb_z_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn bfmlslb_z_zzzi_( i3h: ::aarchmrs_types::BitValue<2>, @@ -128,6 +248,36 @@ pub mod fmlalt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlalt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlalt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -157,6 +307,36 @@ pub mod bfmlalt_z_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlalt_z_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn bfmlalt_z_zzzi_( i3h: ::aarchmrs_types::BitValue<2>, @@ -186,6 +366,36 @@ pub mod fmlslt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmlslt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn fmlslt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -215,6 +425,36 @@ pub mod bfmlslt_z_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmlslt_z_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn bfmlslt_z_zzzi_( i3h: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla/sve_fp_fmmla.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla/sve_fp_fmmla.rs index 11830d36..d0a08d35 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla/sve_fp_fmmla.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla/sve_fp_fmmla.rs @@ -12,6 +12,24 @@ pub mod fmmla_z32_zzz_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmmla_z32_zzz_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmmla_z32_zzz_h( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod bfmmla_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmmla_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmmla_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod fmmla_z_zzz_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmmla_z_zzz_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmmla_z_zzz_s( Zm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod fmmla_z_zzz_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmmla_z_zzz_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmmla_z_zzz_d( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla_nw/sve_fp_fmmla_nw.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla_nw/sve_fp_fmmla_nw.rs index a96535f8..aa5ea893 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla_nw/sve_fp_fmmla_nw.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fmmla_nw/sve_fp_fmmla_nw.rs @@ -12,6 +12,24 @@ pub mod fmmla_z_zzz_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmmla_z_zzz_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn fmmla_z_zzz_h( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod bfmmla_z_zzz_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmmla_z_zzz_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmmla_z_zzz_h( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_fmul_by_indexed_elem/sve_fp_fmul_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_fmul_by_indexed_elem/sve_fp_fmul_by_indexed_elem.rs index 4106e66e..ed370318 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_fmul_by_indexed_elem/sve_fp_fmul_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_fmul_by_indexed_elem/sve_fp_fmul_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod fmul_z_zzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_z_zzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn fmul_z_zzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod bfmul_z_zzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmul_z_zzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn bfmul_z_zzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,30 @@ pub mod fmul_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_z_zzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -96,6 +180,30 @@ pub mod fmul_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn fmul_z_zzi_d( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_pairwise/sve_fp_pairwise.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_pairwise/sve_fp_pairwise.rs index 8b63a159..a7387824 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_pairwise/sve_fp_pairwise.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_pairwise/sve_fp_pairwise.rs @@ -12,6 +12,30 @@ pub mod faddp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "faddp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn faddp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod fmaxnmp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnmp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnmp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod fminnmp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnmp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnmp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod fmaxp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod fminp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_i_p_zds.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_i_p_zds.rs index 5be1dbb7..c2dc9041 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_i_p_zds.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_i_p_zds.rs @@ -12,6 +12,30 @@ pub mod fadd_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadd_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fadd_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod fsub_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsub_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fsub_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod fmul_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod fsubr_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsubr_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fsubr_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod fmaxnm_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnm_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnm_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, @@ -147,6 +267,30 @@ pub mod fminnm_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnm_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnm_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, @@ -174,6 +318,30 @@ pub mod fmax_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmax_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmax_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, @@ -201,6 +369,30 @@ pub mod fmin_z_p_zs_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmin_z_p_zs_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmin_z_p_zs_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_p_zds.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_p_zds.rs index 3e8e86f2..06bf2823 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_p_zds.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_2op_p_zds.rs @@ -12,6 +12,30 @@ pub mod fadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,24 @@ pub mod bfadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfadd_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -61,6 +103,30 @@ pub mod fsub_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsub_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fsub_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -87,6 +153,24 @@ pub mod bfsub_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfsub_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfsub_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -110,6 +194,30 @@ pub mod fmul_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -136,6 +244,24 @@ pub mod bfmul_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmul_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfmul_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -159,6 +285,30 @@ pub mod fsubr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsubr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fsubr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -185,6 +335,30 @@ pub mod fmaxnm_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmaxnm_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmaxnm_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -211,6 +385,24 @@ pub mod bfmaxnm_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmaxnm_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfmaxnm_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -234,6 +426,30 @@ pub mod fminnm_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fminnm_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fminnm_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -260,6 +476,24 @@ pub mod bfminnm_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfminnm_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfminnm_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -283,6 +517,30 @@ pub mod fmax_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmax_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmax_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -309,6 +567,24 @@ pub mod bfmax_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmax_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfmax_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -332,6 +608,30 @@ pub mod fmin_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmin_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmin_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -358,6 +658,24 @@ pub mod bfmin_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmin_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfmin_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -381,6 +699,30 @@ pub mod fabd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fabd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fabd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -407,6 +749,30 @@ pub mod fscale_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fscale_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fscale_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -433,6 +799,24 @@ pub mod bfscale_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfscale_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfscale_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -456,6 +840,30 @@ pub mod fmulx_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmulx_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmulx_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -482,6 +890,30 @@ pub mod fdivr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdivr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fdivr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -508,6 +940,30 @@ pub mod fdiv_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdiv_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fdiv_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -534,6 +990,30 @@ pub mod famax_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "famax_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn famax_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -560,6 +1040,30 @@ pub mod famin_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "famin_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn famin_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_ftmad.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_ftmad.rs index 97e61faa..7f85ae80 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_ftmad.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_pred/sve_fp_ftmad.rs @@ -12,6 +12,30 @@ pub mod ftmad_z_zzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftmad_z_zzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ftmad_z_zzi_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_slowreduce/sve_fp_2op_p_vd.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_slowreduce/sve_fp_2op_p_vd.rs index 9fde7129..7fdfe022 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_slowreduce/sve_fp_2op_p_vd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_slowreduce/sve_fp_2op_p_vd.rs @@ -12,6 +12,30 @@ pub mod fadda_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadda_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fadda_v_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_a.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_a.rs index 88dd644e..a9d2832a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_a.rs @@ -12,6 +12,30 @@ pub mod frintn_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintn_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintn_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod frintp_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintp_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintp_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod frintm_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintm_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintm_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod frintz_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintz_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintz_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod frinta_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frinta_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frinta_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod frintx_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintx_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintx_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod frinti_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frinti_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frinti_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_0.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_0.rs index fc3a6efe..434fcb1e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_0.rs @@ -12,6 +12,24 @@ pub mod fcvtx_z_p_z_d2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtx_z_p_z_d2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtx_z_p_z_d2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod fcvt_z_p_z_s2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_s2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_s2h( Pg: ::aarchmrs_types::BitValue<3>, @@ -58,6 +94,24 @@ pub mod fcvt_z_p_z_h2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_h2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_h2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -81,6 +135,24 @@ pub mod bfcvt_z_p_z_s2bf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvt_z_p_z_s2bf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfcvt_z_p_z_s2bf( Pg: ::aarchmrs_types::BitValue<3>, @@ -104,6 +176,24 @@ pub mod fcvt_z_p_z_d2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_d2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_d2h( Pg: ::aarchmrs_types::BitValue<3>, @@ -127,6 +217,24 @@ pub mod fcvt_z_p_z_h2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_h2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_h2d( Pg: ::aarchmrs_types::BitValue<3>, @@ -150,6 +258,24 @@ pub mod fcvt_z_p_z_d2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_d2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_d2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -173,6 +299,24 @@ pub mod fcvt_z_p_z_s2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_s2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_s2d( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_1.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_1.rs index 705547b6..92ba6ff8 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_b_1.rs @@ -12,6 +12,30 @@ pub mod frecpx_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frecpx_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frecpx_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod fsqrt_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsqrt_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fsqrt_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_c.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_c.rs index 617c5a58..5e78eb81 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_c.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_c.rs @@ -12,6 +12,30 @@ pub mod frint32z_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint32z_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint32z_z_p_z_m( sz: ::aarchmrs_types::BitValue<1>, @@ -38,6 +62,30 @@ pub mod frint32x_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint32x_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint32x_z_p_z_m( sz: ::aarchmrs_types::BitValue<1>, @@ -64,6 +112,30 @@ pub mod frint64z_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint64z_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint64z_z_p_z_m( sz: ::aarchmrs_types::BitValue<1>, @@ -90,6 +162,30 @@ pub mod frint64x_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint64x_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint64x_z_p_z_m( sz: ::aarchmrs_types::BitValue<1>, @@ -116,6 +212,24 @@ pub mod scvtf_z_p_z_w2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_w2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_w2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -139,6 +253,24 @@ pub mod scvtf_z_p_z_w2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_w2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_w2d( Pg: ::aarchmrs_types::BitValue<3>, @@ -162,6 +294,24 @@ pub mod scvtf_z_p_z_x2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_x2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_x2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -185,6 +335,24 @@ pub mod scvtf_z_p_z_x2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_x2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_x2d( Pg: ::aarchmrs_types::BitValue<3>, @@ -208,6 +376,24 @@ pub mod scvtf_z_p_z_h2fp16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_h2fp16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_h2fp16( Pg: ::aarchmrs_types::BitValue<3>, @@ -231,6 +417,24 @@ pub mod scvtf_z_p_z_w2fp16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_w2fp16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_w2fp16( Pg: ::aarchmrs_types::BitValue<3>, @@ -254,6 +458,24 @@ pub mod scvtf_z_p_z_x2fp16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_x2fp16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_x2fp16( Pg: ::aarchmrs_types::BitValue<3>, @@ -277,6 +499,24 @@ pub mod ucvtf_z_p_z_w2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_w2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_w2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -300,6 +540,24 @@ pub mod ucvtf_z_p_z_w2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_w2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_w2d( Pg: ::aarchmrs_types::BitValue<3>, @@ -323,6 +581,24 @@ pub mod ucvtf_z_p_z_x2s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_x2s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_x2s( Pg: ::aarchmrs_types::BitValue<3>, @@ -346,6 +622,24 @@ pub mod ucvtf_z_p_z_x2d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_x2d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_x2d( Pg: ::aarchmrs_types::BitValue<3>, @@ -369,6 +663,24 @@ pub mod ucvtf_z_p_z_h2fp16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_h2fp16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_h2fp16( Pg: ::aarchmrs_types::BitValue<3>, @@ -392,6 +704,24 @@ pub mod ucvtf_z_p_z_w2fp16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_w2fp16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_w2fp16( Pg: ::aarchmrs_types::BitValue<3>, @@ -415,6 +745,24 @@ pub mod ucvtf_z_p_z_x2fp16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_x2fp16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_x2fp16( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_d.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_d.rs index bc6ecee5..d8c57a94 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_d.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary/sve_fp_2op_p_zd_d.rs @@ -12,6 +12,30 @@ pub mod flogb_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "flogb_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn flogb_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,24 @@ pub mod fcvtzs_z_p_z_s2w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_s2w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_s2w( Pg: ::aarchmrs_types::BitValue<3>, @@ -61,6 +103,24 @@ pub mod fcvtzs_z_p_z_d2w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_d2w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_d2w( Pg: ::aarchmrs_types::BitValue<3>, @@ -84,6 +144,24 @@ pub mod fcvtzs_z_p_z_s2x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_s2x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_s2x( Pg: ::aarchmrs_types::BitValue<3>, @@ -107,6 +185,24 @@ pub mod fcvtzs_z_p_z_d2x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_d2x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_d2x( Pg: ::aarchmrs_types::BitValue<3>, @@ -130,6 +226,24 @@ pub mod fcvtzs_z_p_z_fp162h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_fp162h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_fp162h( Pg: ::aarchmrs_types::BitValue<3>, @@ -153,6 +267,24 @@ pub mod fcvtzs_z_p_z_fp162w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_fp162w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_fp162w( Pg: ::aarchmrs_types::BitValue<3>, @@ -176,6 +308,24 @@ pub mod fcvtzs_z_p_z_fp162x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_fp162x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_fp162x( Pg: ::aarchmrs_types::BitValue<3>, @@ -199,6 +349,24 @@ pub mod fcvtzu_z_p_z_s2w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_s2w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_s2w( Pg: ::aarchmrs_types::BitValue<3>, @@ -222,6 +390,24 @@ pub mod fcvtzu_z_p_z_d2w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_d2w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_d2w( Pg: ::aarchmrs_types::BitValue<3>, @@ -245,6 +431,24 @@ pub mod fcvtzu_z_p_z_s2x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_s2x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_s2x( Pg: ::aarchmrs_types::BitValue<3>, @@ -268,6 +472,24 @@ pub mod fcvtzu_z_p_z_d2x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_d2x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_d2x( Pg: ::aarchmrs_types::BitValue<3>, @@ -291,6 +513,24 @@ pub mod fcvtzu_z_p_z_fp162h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_fp162h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_fp162h( Pg: ::aarchmrs_types::BitValue<3>, @@ -314,6 +554,24 @@ pub mod fcvtzu_z_p_z_fp162w { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_fp162w"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_fp162w( Pg: ::aarchmrs_types::BitValue<3>, @@ -337,6 +595,24 @@ pub mod fcvtzu_z_p_z_fp162x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_fp162x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_fp162x( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_narrow.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_narrow.rs index 4d49696f..59083801 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_narrow.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_narrow.rs @@ -12,6 +12,18 @@ pub mod fcvtn_z8_mz2_h2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtn_z8_mz2_h2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvtn_z8_mz2_h2b( Zn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod fcvtnb_z8_mz2_s2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtnb_z8_mz2_s2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvtnb_z8_mz2_s2b( Zn: ::aarchmrs_types::BitValue<4>, @@ -56,6 +80,18 @@ pub mod bfcvtn_z8_mz2_bf2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvtn_z8_mz2_bf2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn bfcvtn_z8_mz2_bf2b( Zn: ::aarchmrs_types::BitValue<4>, @@ -78,6 +114,18 @@ pub mod fcvtnt_z8_mz2_s2b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtnt_z8_mz2_s2b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn fcvtnt_z8_mz2_s2b( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_wide.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_wide.rs index c32cd2ab..c3fc458e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_wide.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp8_fcvt_wide.rs @@ -12,6 +12,18 @@ pub mod f1cvt_z_z8_b2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f1cvt_z_z8_b2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f1cvt_z_z8_b2h( Zn: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod f2cvt_z_z8_b2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f2cvt_z_z8_b2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f2cvt_z_z8_b2h( Zn: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod bf1cvt_z_z8_b2bf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf1cvt_z_z8_b2bf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf1cvt_z_z8_b2bf( Zn: ::aarchmrs_types::BitValue<5>, @@ -75,6 +111,18 @@ pub mod bf2cvt_z_z8_b2bf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf2cvt_z_z8_b2bf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf2cvt_z_z8_b2bf( Zn: ::aarchmrs_types::BitValue<5>, @@ -96,6 +144,18 @@ pub mod f1cvtlt_z_z8_b2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f1cvtlt_z_z8_b2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f1cvtlt_z_z8_b2h( Zn: ::aarchmrs_types::BitValue<5>, @@ -117,6 +177,18 @@ pub mod f2cvtlt_z_z8_b2h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "f2cvtlt_z_z8_b2h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn f2cvtlt_z_z8_b2h( Zn: ::aarchmrs_types::BitValue<5>, @@ -138,6 +210,18 @@ pub mod bf1cvtlt_z_z8_b2bf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf1cvtlt_z_z8_b2bf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf1cvtlt_z_z8_b2bf( Zn: ::aarchmrs_types::BitValue<5>, @@ -159,6 +243,18 @@ pub mod bf2cvtlt_z_z8_b2bf { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bf2cvtlt_z_z8_b2bf"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn bf2cvtlt_z_z8_b2bf( Zn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_2op_u_zd.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_2op_u_zd.rs index 86aca578..54ec200c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_2op_u_zd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_2op_u_zd.rs @@ -12,6 +12,24 @@ pub mod frecpe_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frecpe_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frecpe_z_z_( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod frsqrte_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frsqrte_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frsqrte_z_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_fcvtzu_narrow.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_fcvtzu_narrow.rs index 6b468f59..33d14d95 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_fcvtzu_narrow.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_fcvtzu_narrow.rs @@ -12,6 +12,24 @@ pub mod fcvtzsn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzsn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcvtzsn_z_mz2_( size: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod fcvtzun_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzun_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcvtzun_z_mz2_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_ucvtf_wide.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_ucvtf_wide.rs index fe1bf88e..77c706f7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_ucvtf_wide.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unary_unpred/sve_fp_ucvtf_wide.rs @@ -12,6 +12,24 @@ pub mod scvtf_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn scvtf_z_z_( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod scvtflt_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtflt_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn scvtflt_z_z_( size: ::aarchmrs_types::BitValue<2>, @@ -60,6 +96,24 @@ pub mod ucvtf_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ucvtf_z_z_( size: ::aarchmrs_types::BitValue<2>, @@ -84,6 +138,24 @@ pub mod ucvtflt_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtflt_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ucvtflt_z_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_unpred/sve_fp_3op_u_zd.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_unpred/sve_fp_3op_u_zd.rs index 786b6a1f..19fa04b9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_unpred/sve_fp_3op_u_zd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_unpred/sve_fp_3op_u_zd.rs @@ -12,6 +12,30 @@ pub mod fadd_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fadd_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fadd_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,24 @@ pub mod bfadd_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfadd_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfadd_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -63,6 +105,30 @@ pub mod fsub_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsub_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fsub_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +156,24 @@ pub mod bfsub_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfsub_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfsub_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -114,6 +198,30 @@ pub mod fmul_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fmul_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fmul_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -141,6 +249,24 @@ pub mod bfmul_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfmul_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bfmul_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -165,6 +291,30 @@ pub mod ftsmul_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftsmul_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ftsmul_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -192,6 +342,30 @@ pub mod frecps_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frecps_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frecps_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -219,6 +393,30 @@ pub mod frsqrts_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frsqrts_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frsqrts_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_a.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_a.rs index 381cf687..f0778ef3 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_a.rs @@ -12,6 +12,30 @@ pub mod frintn_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintn_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintn_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod frintp_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintp_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintp_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod frintm_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintm_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintm_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod frintz_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintz_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintz_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod frinta_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frinta_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frinta_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod frintx_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frintx_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frintx_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod frinti_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frinti_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frinti_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_0.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_0.rs index 1e05df52..59edb347 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_0.rs @@ -12,6 +12,24 @@ pub mod fcvtx_z_p_z_d2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtx_z_p_z_d2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtx_z_p_z_d2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod fcvt_z_p_z_s2hz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_s2hz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_s2hz( Pg: ::aarchmrs_types::BitValue<3>, @@ -58,6 +94,24 @@ pub mod fcvt_z_p_z_h2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_h2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_h2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -81,6 +135,24 @@ pub mod bfcvt_z_p_z_s2bfz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bfcvt_z_p_z_s2bfz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn bfcvt_z_p_z_s2bfz( Pg: ::aarchmrs_types::BitValue<3>, @@ -104,6 +176,24 @@ pub mod fcvt_z_p_z_d2hz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_d2hz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_d2hz( Pg: ::aarchmrs_types::BitValue<3>, @@ -127,6 +217,24 @@ pub mod fcvt_z_p_z_h2dz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_h2dz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_h2dz( Pg: ::aarchmrs_types::BitValue<3>, @@ -150,6 +258,24 @@ pub mod fcvt_z_p_z_d2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_d2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_d2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -173,6 +299,24 @@ pub mod fcvt_z_p_z_s2dz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvt_z_p_z_s2dz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvt_z_p_z_s2dz( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_1.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_1.rs index 7f10ecc9..9acde7ba 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_b_1.rs @@ -12,6 +12,30 @@ pub mod frecpx_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frecpx_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn frecpx_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod fsqrt_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fsqrt_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fsqrt_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_c.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_c.rs index 89a8b933..d34ba56c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_c.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_c.rs @@ -12,6 +12,30 @@ pub mod frint32z_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint32z_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint32z_z_p_z_z( sz: ::aarchmrs_types::BitValue<1>, @@ -38,6 +62,30 @@ pub mod frint32x_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint32x_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint32x_z_p_z_z( sz: ::aarchmrs_types::BitValue<1>, @@ -64,6 +112,30 @@ pub mod frint64z_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint64z_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint64z_z_p_z_z( sz: ::aarchmrs_types::BitValue<1>, @@ -90,6 +162,30 @@ pub mod frint64x_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "frint64x_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn frint64x_z_p_z_z( sz: ::aarchmrs_types::BitValue<1>, @@ -116,6 +212,24 @@ pub mod scvtf_z_p_z_w2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_w2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_w2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -139,6 +253,24 @@ pub mod scvtf_z_p_z_w2dz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_w2dz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_w2dz( Pg: ::aarchmrs_types::BitValue<3>, @@ -162,6 +294,24 @@ pub mod scvtf_z_p_z_x2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_x2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_x2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -185,6 +335,24 @@ pub mod scvtf_z_p_z_x2dz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_x2dz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_x2dz( Pg: ::aarchmrs_types::BitValue<3>, @@ -208,6 +376,24 @@ pub mod scvtf_z_p_z_h2fp16z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_h2fp16z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_h2fp16z( Pg: ::aarchmrs_types::BitValue<3>, @@ -231,6 +417,24 @@ pub mod scvtf_z_p_z_w2fp16z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_w2fp16z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_w2fp16z( Pg: ::aarchmrs_types::BitValue<3>, @@ -254,6 +458,24 @@ pub mod scvtf_z_p_z_x2fp16z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "scvtf_z_p_z_x2fp16z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn scvtf_z_p_z_x2fp16z( Pg: ::aarchmrs_types::BitValue<3>, @@ -277,6 +499,24 @@ pub mod ucvtf_z_p_z_w2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_w2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_w2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -300,6 +540,24 @@ pub mod ucvtf_z_p_z_w2dz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_w2dz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_w2dz( Pg: ::aarchmrs_types::BitValue<3>, @@ -323,6 +581,24 @@ pub mod ucvtf_z_p_z_x2sz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_x2sz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_x2sz( Pg: ::aarchmrs_types::BitValue<3>, @@ -346,6 +622,24 @@ pub mod ucvtf_z_p_z_x2dz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_x2dz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_x2dz( Pg: ::aarchmrs_types::BitValue<3>, @@ -369,6 +663,24 @@ pub mod ucvtf_z_p_z_h2fp16z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_h2fp16z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_h2fp16z( Pg: ::aarchmrs_types::BitValue<3>, @@ -392,6 +704,24 @@ pub mod ucvtf_z_p_z_w2fp16z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_w2fp16z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_w2fp16z( Pg: ::aarchmrs_types::BitValue<3>, @@ -415,6 +745,24 @@ pub mod ucvtf_z_p_z_x2fp16z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ucvtf_z_p_z_x2fp16z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn ucvtf_z_p_z_x2fp16z( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_d.rs b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_d.rs index 56e4f8aa..5542f059 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_d.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_fp_zeroing_unary/sve_fp_z2op_p_zd_d.rs @@ -12,6 +12,30 @@ pub mod flogb_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "flogb_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn flogb_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -37,6 +61,24 @@ pub mod fcvtzs_z_p_z_s2wz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_s2wz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_s2wz( Pg: ::aarchmrs_types::BitValue<3>, @@ -60,6 +102,24 @@ pub mod fcvtzs_z_p_z_d2wz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_d2wz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_d2wz( Pg: ::aarchmrs_types::BitValue<3>, @@ -83,6 +143,24 @@ pub mod fcvtzs_z_p_z_s2xz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_s2xz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_s2xz( Pg: ::aarchmrs_types::BitValue<3>, @@ -106,6 +184,24 @@ pub mod fcvtzs_z_p_z_d2xz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_d2xz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_d2xz( Pg: ::aarchmrs_types::BitValue<3>, @@ -129,6 +225,24 @@ pub mod fcvtzs_z_p_z_fp162hz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_fp162hz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_fp162hz( Pg: ::aarchmrs_types::BitValue<3>, @@ -152,6 +266,24 @@ pub mod fcvtzs_z_p_z_fp162wz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_fp162wz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_fp162wz( Pg: ::aarchmrs_types::BitValue<3>, @@ -175,6 +307,24 @@ pub mod fcvtzs_z_p_z_fp162xz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzs_z_p_z_fp162xz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzs_z_p_z_fp162xz( Pg: ::aarchmrs_types::BitValue<3>, @@ -198,6 +348,24 @@ pub mod fcvtzu_z_p_z_s2wz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_s2wz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_s2wz( Pg: ::aarchmrs_types::BitValue<3>, @@ -221,6 +389,24 @@ pub mod fcvtzu_z_p_z_d2wz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_d2wz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_d2wz( Pg: ::aarchmrs_types::BitValue<3>, @@ -244,6 +430,24 @@ pub mod fcvtzu_z_p_z_s2xz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_s2xz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_s2xz( Pg: ::aarchmrs_types::BitValue<3>, @@ -267,6 +471,24 @@ pub mod fcvtzu_z_p_z_d2xz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_d2xz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_d2xz( Pg: ::aarchmrs_types::BitValue<3>, @@ -290,6 +512,24 @@ pub mod fcvtzu_z_p_z_fp162hz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_fp162hz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_fp162hz( Pg: ::aarchmrs_types::BitValue<3>, @@ -313,6 +553,24 @@ pub mod fcvtzu_z_p_z_fp162wz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_fp162wz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_fp162wz( Pg: ::aarchmrs_types::BitValue<3>, @@ -336,6 +594,24 @@ pub mod fcvtzu_z_p_z_fp162xz { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcvtzu_z_p_z_fp162xz"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn fcvtzu_z_p_z_fp162xz( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ii.rs b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ii.rs index d39a74ae..4f5fbab1 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ii.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ii.rs @@ -12,6 +12,30 @@ pub mod index_z_ii_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "index_z_ii_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5b_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5b_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn index_z_ii_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ir.rs b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ir.rs index d703aaaa..374e5017 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ir.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ir.rs @@ -12,6 +12,30 @@ pub mod index_z_ir_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "index_z_ir_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn index_z_ir_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ri.rs b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ri.rs index ecabdc1d..04c745fd 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ri.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_ri.rs @@ -12,6 +12,30 @@ pub mod index_z_ri_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "index_z_ri_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn index_z_ri_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_rr.rs b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_rr.rs index 804f48f1..f8483c87 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_rr.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_index/sve_int_index_rr.rs @@ -12,6 +12,30 @@ pub mod index_z_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "index_z_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn index_z_rr_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_adr/sve_int_bin_cons_misc_0_a.rs b/aarchmrs-instructions/src/A64/sve/sve_int_adr/sve_int_bin_cons_misc_0_a.rs index b1a7f614..1cce5f48 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_adr/sve_int_bin_cons_misc_0_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_adr/sve_int_bin_cons_misc_0_a.rs @@ -12,6 +12,30 @@ pub mod adr_z_az_d_s32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "adr_z_az_d_s32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msz_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msz_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn adr_z_az_d_s32_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod adr_z_az_d_u32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "adr_z_az_d_u32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msz_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msz_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn adr_z_az_d_u32_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,36 @@ pub mod adr_z_az_sd_same_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "adr_z_az_sd_same_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msz_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msz_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn adr_z_az_sd_same_scaled( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mladdsub_vvv_pred.rs b/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mladdsub_vvv_pred.rs index 70e93197..7fcfd191 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mladdsub_vvv_pred.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mladdsub_vvv_pred.rs @@ -12,6 +12,36 @@ pub mod mad_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mad_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn mad_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod msb_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "msb_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn msb_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mlas_vvv_pred.rs b/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mlas_vvv_pred.rs index 09fd9daa..d4018926 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mlas_vvv_pred.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_muladd_pred/sve_int_mlas_vvv_pred.rs @@ -12,6 +12,36 @@ pub mod mla_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mla_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn mla_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod mls_z_p_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mls_z_p_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn mls_z_p_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_0.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_0.rs index 325503f3..d823b634 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_0.rs @@ -12,6 +12,30 @@ pub mod add_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn add_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sub_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sub_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod subr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "subr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn subr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,24 @@ pub mod addpt_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addpt_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn addpt_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, @@ -113,6 +203,24 @@ pub mod subpt_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "subpt_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn subpt_z_p_zz_( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_1.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_1.rs index 31148731..c3791e66 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_1.rs @@ -12,6 +12,30 @@ pub mod smax_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smax_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smax_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod smin_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smin_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smin_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod sabd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sabd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sabd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod umax_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umax_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umax_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod umin_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umin_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umin_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod uabd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uabd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uabd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_2.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_2.rs index 40908f6b..4779f6c2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_arit_2.rs @@ -12,6 +12,30 @@ pub mod mul_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mul_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn mul_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod smulh_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smulh_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smulh_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod umulh_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umulh_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umulh_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_div.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_div.rs index 72eb3de6..5d62e5da 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_div.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_div.rs @@ -12,6 +12,30 @@ pub mod sdiv_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdiv_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sdiv_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sdivr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdivr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sdivr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod udiv_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udiv_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn udiv_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod udivr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udivr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn udivr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_log.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_log.rs index 12653a86..52bc8183 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_log.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_bin/sve_int_bin_pred_log.rs @@ -12,6 +12,30 @@ pub mod orr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn orr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod eor_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eor_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn eor_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod and_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "and_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn and_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod bic_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bic_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn bic_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_movprfx_pred.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_movprfx_pred.rs index 11018068..1d659488 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_movprfx_pred.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_movprfx_pred.rs @@ -12,6 +12,36 @@ pub mod movprfx_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movprfx_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn movprfx_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0.rs index bbd52948..13f74873 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0.rs @@ -12,6 +12,30 @@ pub mod saddv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "saddv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn saddv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod uaddv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uaddv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uaddv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0q.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0q.rs index 2236d89d..2a81c2b5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0q.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_0q.rs @@ -12,6 +12,30 @@ pub mod addqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn addqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1.rs index ae0a6828..e5a299c5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1.rs @@ -12,6 +12,30 @@ pub mod smaxv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smaxv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smaxv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sminv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sminv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sminv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod umaxv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umaxv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umaxv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod uminv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uminv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uminv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1q.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1q.rs index 6f6867c5..f4df751a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1q.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_1q.rs @@ -12,6 +12,30 @@ pub mod smaxqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smaxqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smaxqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sminqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sminqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sminqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod umaxqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umaxqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umaxqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod uminqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uminqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uminqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2.rs index e8b88683..54907895 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2.rs @@ -12,6 +12,30 @@ pub mod orv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn orv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod eorv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eorv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn eorv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod andv_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "andv_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn andv_r_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2q.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2q.rs index c93c5c7d..8dc11291 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2q.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_red/sve_int_reduce_2q.rs @@ -12,6 +12,30 @@ pub mod orqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn orqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod eorqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eorqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn eorqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod andqv_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "andqv_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn andqv_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_0.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_0.rs index d82535a6..33767737 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_0.rs @@ -12,6 +12,36 @@ pub mod asr_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "asr_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn asr_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod lsl_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsl_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn lsl_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -68,6 +128,36 @@ pub mod asrd_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "asrd_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn asrd_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -96,6 +186,36 @@ pub mod sqshl_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshl_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn sqshl_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -124,6 +244,36 @@ pub mod srshr_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srshr_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn srshr_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -152,6 +302,36 @@ pub mod sqshlu_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshlu_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn sqshlu_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -180,6 +360,36 @@ pub mod lsr_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsr_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn lsr_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -208,6 +418,36 @@ pub mod uqshl_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqshl_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn uqshl_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -236,6 +476,36 @@ pub mod urshr_z_p_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urshr_z_p_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn urshr_z_p_zi_( tszh: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_1.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_1.rs index 4634d2fd..2206ab76 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_1.rs @@ -12,6 +12,30 @@ pub mod asr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "asr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn asr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod lsl_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsl_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lsl_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod asrr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "asrr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn asrr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod lslr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lslr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lslr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod lsr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lsr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod lsrr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsrr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lsrr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_2.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_2.rs index 6a92d002..e024e02d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_shift/sve_int_bin_pred_shift_2.rs @@ -12,6 +12,30 @@ pub mod asr_z_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "asr_z_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn asr_z_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod lsl_z_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsl_z_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lsl_z_p_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod lsr_z_p_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsr_z_p_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lsr_z_p_zw_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_0.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_0.rs index c4ede702..57544ac6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_0.rs @@ -12,6 +12,30 @@ pub mod abs_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "abs_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn abs_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod abs_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "abs_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn abs_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod neg_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "neg_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn neg_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod neg_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "neg_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn neg_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod sxtw_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sxtw_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sxtw_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod sxtw_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sxtw_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sxtw_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod sxth_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sxth_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sxth_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod sxth_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sxth_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sxth_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -220,6 +412,30 @@ pub mod sxtb_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sxtb_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sxtb_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -246,6 +462,30 @@ pub mod sxtb_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sxtb_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sxtb_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -272,6 +512,30 @@ pub mod uxtw_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uxtw_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uxtw_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -298,6 +562,30 @@ pub mod uxtw_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uxtw_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uxtw_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -324,6 +612,30 @@ pub mod uxth_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uxth_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uxth_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -350,6 +662,30 @@ pub mod uxth_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uxth_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uxth_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -376,6 +712,30 @@ pub mod uxtb_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uxtb_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uxtb_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -402,6 +762,30 @@ pub mod uxtb_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uxtb_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uxtb_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_1.rs b/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_1.rs index 5020ab38..0d8c71b9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_pred_un/sve_int_un_pred_arit_1.rs @@ -12,6 +12,30 @@ pub mod cls_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cls_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cls_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod cls_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cls_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cls_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod clz_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clz_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clz_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod clz_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clz_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clz_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod cnt_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cnt_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cnt_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod cnt_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cnt_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cnt_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod cnot_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cnot_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cnot_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod cnot_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cnot_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cnot_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -220,6 +412,30 @@ pub mod fabs_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fabs_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fabs_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -246,6 +462,30 @@ pub mod fabs_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fabs_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fabs_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -272,6 +512,30 @@ pub mod fneg_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fneg_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fneg_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -298,6 +562,30 @@ pub mod fneg_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fneg_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fneg_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -324,6 +612,30 @@ pub mod not_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "not_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn not_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -350,6 +662,30 @@ pub mod not_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "not_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn not_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_select/sve_int_sel_vvv.rs b/aarchmrs-instructions/src/A64/sve/sve_int_select/sve_int_sel_vvv.rs index d1fbde40..fec94720 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_select/sve_int_sel_vvv.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_select/sve_int_sel_vvv.rs @@ -12,6 +12,36 @@ pub mod sel_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sel_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sel_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit/sve_int_bin_cons_arit_0.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit/sve_int_bin_cons_arit_0.rs index 534610e2..b937f69e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit/sve_int_bin_cons_arit_0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit/sve_int_bin_cons_arit_0.rs @@ -12,6 +12,30 @@ pub mod add_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn add_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod sub_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sub_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,24 @@ pub mod addpt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addpt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn addpt_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +156,24 @@ pub mod subpt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "subpt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn subpt_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -114,6 +198,30 @@ pub mod sqadd_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqadd_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqadd_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -141,6 +249,30 @@ pub mod sqsub_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqsub_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqsub_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +300,30 @@ pub mod uqadd_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqadd_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqadd_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -195,6 +351,30 @@ pub mod uqsub_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqsub_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqsub_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addqp.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addqp.rs index c27f1ee6..d4252827 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addqp.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addqp.rs @@ -12,6 +12,30 @@ pub mod addqp_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addqp_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn addqp_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addsubp.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addsubp.rs index 7f562925..e9945879 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addsubp.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_addsubp.rs @@ -12,6 +12,30 @@ pub mod addsubp_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addsubp_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn addsubp_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_mul_b.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_mul_b.rs index f6f1891f..93cae67a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_mul_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_mul_b.rs @@ -12,6 +12,30 @@ pub mod mul_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mul_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn mul_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,24 @@ pub mod pmul_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmul_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn pmul_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -63,6 +105,30 @@ pub mod smulh_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smulh_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smulh_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +156,30 @@ pub mod umulh_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umulh_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umulh_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_sqdmulh.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_sqdmulh.rs index 32143590..bb48ff9e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_sqdmulh.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_arit_b/sve_int_sqdmulh.rs @@ -12,6 +12,30 @@ pub mod sqdmulh_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmulh_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod sqrdmulh_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmulh_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdmulh_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_bin_cons_log.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_bin_cons_log.rs index b97eacde..e0e026b6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_bin_cons_log.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_bin_cons_log.rs @@ -12,6 +12,24 @@ pub mod and_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "and_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn and_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod orr_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orr_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn orr_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod eor_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eor_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn eor_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod bic_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bic_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bic_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_rotate_imm.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_rotate_imm.rs index a1f27be5..1216c1f4 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_rotate_imm.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_rotate_imm.rs @@ -12,6 +12,36 @@ pub mod xar_z_zzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "xar_z_zzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn xar_z_zzi_( tszh: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_tern_log.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_tern_log.rs index fb1a7a21..ef7cd052 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_tern_log.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_logical/sve_int_tern_log.rs @@ -12,6 +12,24 @@ pub mod eor3_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eor3_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn eor3_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod bcax_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bcax_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bcax_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod bsl_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bsl_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bsl_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod bsl1n_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bsl1n_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bsl1n_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod bsl2n_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bsl2n_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn bsl2n_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod nbsl_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "nbsl_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zk_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn nbsl_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_b.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_b.rs index 5635498e..65826b0b 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_b.rs @@ -12,6 +12,30 @@ pub mod ftssel_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ftssel_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ftssel_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_c.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_c.rs index 3bcb1476..cec85807 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_c.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_c.rs @@ -12,6 +12,24 @@ pub mod fexpa_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fexpa_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fexpa_z_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_d.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_d.rs index 1889e353..ce70ff47 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_d.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_misc/sve_int_bin_cons_misc_0_d.rs @@ -12,6 +12,18 @@ pub mod movprfx_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "movprfx_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn movprfx_z_z_( Zn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_a.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_a.rs index 51ade1b5..db66fd3b 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_a.rs @@ -12,6 +12,30 @@ pub mod asr_z_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "asr_z_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn asr_z_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod lsl_z_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsl_z_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lsl_z_zw_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod lsr_z_zw_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsr_z_zw_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lsr_z_zw_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_b.rs b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_b.rs index 4bb76c42..f8dc184a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_int_unpred_shift/sve_int_bin_cons_shift_b.rs @@ -12,6 +12,36 @@ pub mod asr_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "asr_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn asr_z_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod lsl_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsl_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn lsl_z_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -70,6 +130,36 @@ pub mod lsr_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lsr_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn lsr_z_zi_( tszh: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba.rs index e40602fb..87609980 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba.rs @@ -12,6 +12,30 @@ pub mod saba_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "saba_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn saba_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod uaba_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uaba_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uaba_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba_long.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba_long.rs index b95ef8d0..47899eea 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_aba_long.rs @@ -12,6 +12,30 @@ pub mod sabalb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sabalb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sabalb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod sabalt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sabalt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sabalt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod uabalb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uabalb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uabalb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod uabalt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uabalt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uabalt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_adc_long.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_adc_long.rs index f0f1afd2..9682d15b 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_adc_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_adc_long.rs @@ -12,6 +12,30 @@ pub mod adclb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "adclb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn adclb_z_zzz_( sz: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod sbclb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sbclb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sbclb_z_zzz_( sz: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod adclt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "adclt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn adclt_z_zzz_( sz: ::aarchmrs_types::BitValue<1>, @@ -93,6 +165,30 @@ pub mod sbclt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sbclt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn sbclt_z_zzz_( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_cadd.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_cadd.rs index 5fe15f32..d099aae0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_cadd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_cadd.rs @@ -12,6 +12,30 @@ pub mod cadd_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cadd_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cadd_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sqcadd_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcadd_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqcadd_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_shift_insert.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_shift_insert.rs index e8c9d4ed..4cea60ba 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_shift_insert.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_shift_insert.rs @@ -12,6 +12,36 @@ pub mod sri_z_zzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sri_z_zzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn sri_z_zzi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod sli_z_zzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sli_z_zzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn sli_z_zzi_( tszh: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_sra.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_sra.rs index d5b13b4a..453b5ae7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_sra.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_acc/sve_intx_sra.rs @@ -12,6 +12,36 @@ pub mod ssra_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ssra_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn ssra_z_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod srsra_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srsra_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn srsra_z_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -70,6 +130,36 @@ pub mod usra_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usra_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn usra_z_zi_( tszh: ::aarchmrs_types::BitValue<2>, @@ -99,6 +189,36 @@ pub mod ursra_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ursra_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 2u32; #[inline] pub const fn ursra_z_zi_( tszh: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cdot_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cdot_by_indexed_elem.rs index 547cad8e..b4ec29f2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cdot_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cdot_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod cdot_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cdot_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn cdot_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod cdot_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cdot_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn cdot_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cmla_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cmla_by_indexed_elem.rs index cb86c0e1..dd6b87c5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cmla_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_cmla_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod cmla_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmla_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn cmla_z_zzzi_h( i2: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod cmla_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmla_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn cmla_z_zzzi_s( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_dot_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_dot_by_indexed_elem.rs index 08dcbeb1..b6e9fa45 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_dot_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_dot_by_indexed_elem.rs @@ -12,6 +12,30 @@ pub mod sdot_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sdot_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sdot_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn sdot_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, @@ -64,6 +112,36 @@ pub mod sdot_z16_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_z16_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn sdot_z16_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -93,6 +171,30 @@ pub mod udot_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn udot_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -119,6 +221,30 @@ pub mod udot_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn udot_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, @@ -145,6 +271,36 @@ pub mod udot_z16_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_z16_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn udot_z16_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mixed_dot_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mixed_dot_by_indexed_elem.rs index 56f9db9a..1d5c3a20 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mixed_dot_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mixed_dot_by_indexed_elem.rs @@ -12,6 +12,30 @@ pub mod usdot_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn usdot_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sudot_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sudot_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sudot_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_by_indexed_elem.rs index 4c054cca..44600bee 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod mla_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mla_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn mla_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,30 @@ pub mod mla_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mla_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn mla_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -67,6 +121,30 @@ pub mod mla_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mla_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn mla_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, @@ -93,6 +171,36 @@ pub mod mls_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mls_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn mls_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -122,6 +230,30 @@ pub mod mls_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mls_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn mls_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -148,6 +280,30 @@ pub mod mls_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mls_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn mls_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_long_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_long_by_indexed_elem.rs index 1c69af82..162b505d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_long_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mla_long_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod smlalb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlalb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn smlalb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod smlalb_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlalb_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn smlalb_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod smlslb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlslb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn smlslb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -99,6 +189,36 @@ pub mod smlslb_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlslb_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn smlslb_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod smlalt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlalt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn smlalt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -157,6 +307,36 @@ pub mod smlalt_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlalt_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn smlalt_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod smlslt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlslt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn smlslt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -215,6 +425,36 @@ pub mod smlslt_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlslt_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn smlslt_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -244,6 +484,36 @@ pub mod umlalb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlalb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn umlalb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -273,6 +543,36 @@ pub mod umlalb_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlalb_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn umlalb_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -302,6 +602,36 @@ pub mod umlslb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlslb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn umlslb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -331,6 +661,36 @@ pub mod umlslb_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlslb_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn umlslb_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -360,6 +720,36 @@ pub mod umlalt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlalt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn umlalt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -389,6 +779,36 @@ pub mod umlalt_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlalt_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn umlalt_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -418,6 +838,36 @@ pub mod umlslt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlslt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn umlslt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -447,6 +897,36 @@ pub mod umlslt_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlslt_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn umlslt_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_by_indexed_elem.rs index 3016d9b9..0a10abce 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod mul_z_zzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mul_z_zzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn mul_z_zzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,30 @@ pub mod mul_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mul_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn mul_z_zzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -67,6 +121,30 @@ pub mod mul_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mul_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn mul_z_zzi_d( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_long_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_long_by_indexed_elem.rs index 552e6d9d..e2c866f2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_long_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_mul_long_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod smullb_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smullb_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn smullb_z_zzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod smullb_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smullb_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn smullb_z_zzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod smullt_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smullt_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn smullt_z_zzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -99,6 +189,36 @@ pub mod smullt_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smullt_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn smullt_z_zzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod umullb_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umullb_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn umullb_z_zzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -157,6 +307,36 @@ pub mod umullb_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umullb_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn umullb_z_zzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod umullt_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umullt_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn umullt_z_zzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -215,6 +425,36 @@ pub mod umullt_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umullt_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn umullt_z_zzi_d( i2h: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmla_long_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmla_long_by_indexed_elem.rs index edffe3d9..786f34fd 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmla_long_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmla_long_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod sqdmlalb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlalb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlalb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod sqdmlalb_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlalb_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmlalb_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod sqdmlslb_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlslb_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlslb_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -99,6 +189,36 @@ pub mod sqdmlslb_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlslb_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmlslb_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod sqdmlalt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlalt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlalt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -157,6 +307,36 @@ pub mod sqdmlalt_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlalt_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmlalt_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod sqdmlslt_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlslt_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlslt_z_zzzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -215,6 +425,36 @@ pub mod sqdmlslt_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlslt_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmlslt_z_zzzi_d( i2h: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmul_long_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmul_long_by_indexed_elem.rs index 2631a74c..175d1a05 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmul_long_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmul_long_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod sqdmullb_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmullb_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmullb_z_zzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod sqdmullb_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmullb_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmullb_z_zzi_d( i2h: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod sqdmullt_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmullt_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmullt_z_zzi_s( i3h: ::aarchmrs_types::BitValue<2>, @@ -99,6 +189,36 @@ pub mod sqdmullt_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmullt_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2h_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmullt_z_zzi_d( i2h: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmulh_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmulh_by_indexed_elem.rs index dcba020a..6866b176 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmulh_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qdmulh_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod sqdmulh_z_zzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_z_zzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmulh_z_zzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,30 @@ pub mod sqdmulh_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmulh_z_zzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -67,6 +121,30 @@ pub mod sqdmulh_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmulh_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn sqdmulh_z_zzi_d( i1: ::aarchmrs_types::BitValue<1>, @@ -93,6 +171,36 @@ pub mod sqrdmulh_z_zzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmulh_z_zzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn sqrdmulh_z_zzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -122,6 +230,30 @@ pub mod sqrdmulh_z_zzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmulh_z_zzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdmulh_z_zzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -148,6 +280,30 @@ pub mod sqrdmulh_z_zzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmulh_z_zzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn sqrdmulh_z_zzi_d( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdcmla_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdcmla_by_indexed_elem.rs index d6e2cec2..b23109f8 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdcmla_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdcmla_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod sqrdcmlah_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdcmlah_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdcmlah_z_zzzi_h( i2: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod sqrdcmlah_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdcmlah_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn sqrdcmlah_z_zzzi_s( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdmlah_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdmlah_by_indexed_elem.rs index 245780d3..ee3458d7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdmlah_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_by_indexed_elem/sve_intx_qrdmlah_by_indexed_elem.rs @@ -12,6 +12,36 @@ pub mod sqrdmlah_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlah_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn sqrdmlah_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,30 @@ pub mod sqrdmlah_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlah_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdmlah_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -67,6 +121,30 @@ pub mod sqrdmlah_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlah_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn sqrdmlah_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, @@ -93,6 +171,36 @@ pub mod sqrdmlsh_z_zzzi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlsh_z_zzzi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn sqrdmlsh_z_zzzi_h( i3h: ::aarchmrs_types::BitValue<1>, @@ -122,6 +230,30 @@ pub mod sqrdmlsh_z_zzzi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlsh_z_zzzi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdmlsh_z_zzzi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -148,6 +280,30 @@ pub mod sqrdmlsh_z_zzzi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlsh_z_zzzi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn sqrdmlsh_z_zzzi_d( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_clamp/sve_intx_clamp.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_clamp/sve_intx_clamp.rs index 000e9cae..afa8131e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_clamp/sve_intx_clamp.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_clamp/sve_intx_clamp.rs @@ -12,6 +12,30 @@ pub mod sclamp_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sclamp_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sclamp_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod uclamp_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uclamp_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uclamp_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_long.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_long.rs index aef5ebfc..5c419ab6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_long.rs @@ -12,6 +12,30 @@ pub mod saddlb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "saddlb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn saddlb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod ssublb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ssublb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ssublb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod sabdlb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sabdlb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sabdlb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod saddlt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "saddlt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn saddlt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod ssublt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ssublt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ssublt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -147,6 +267,30 @@ pub mod sabdlt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sabdlt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sabdlt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -174,6 +318,30 @@ pub mod uaddlb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uaddlb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uaddlb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -201,6 +369,30 @@ pub mod usublb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usublb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn usublb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -228,6 +420,30 @@ pub mod uabdlb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uabdlb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uabdlb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -255,6 +471,30 @@ pub mod uaddlt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uaddlt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uaddlt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -282,6 +522,30 @@ pub mod usublt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usublt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn usublt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -309,6 +573,30 @@ pub mod uabdlt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uabdlt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uabdlt_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_wide.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_wide.rs index b1cf688f..8cf177b1 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_wide.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_arith_wide.rs @@ -12,6 +12,30 @@ pub mod saddwb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "saddwb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn saddwb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod ssubwb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ssubwb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ssubwb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod saddwt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "saddwt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn saddwt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod ssubwt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ssubwt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ssubwt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod uaddwb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uaddwb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uaddwb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -147,6 +267,30 @@ pub mod usubwb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usubwb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn usubwb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -174,6 +318,30 @@ pub mod uaddwt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uaddwt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uaddwt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -201,6 +369,30 @@ pub mod usubwt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usubwt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn usubwt_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_mul_long.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_mul_long.rs index e1138771..8cb4d7b7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_mul_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_cons_widening/sve_intx_cons_mul_long.rs @@ -12,6 +12,30 @@ pub mod sqdmullb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmullb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmullb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,24 @@ pub mod pmullb_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmullb_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn pmullb_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, @@ -63,6 +105,30 @@ pub mod pmullb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmullb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn pmullb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +156,30 @@ pub mod smullb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smullb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smullb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -117,6 +207,30 @@ pub mod sqdmullt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmullt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmullt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -144,6 +258,24 @@ pub mod pmullt_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmullt_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn pmullt_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +300,30 @@ pub mod pmullt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmullt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn pmullt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -195,6 +351,30 @@ pub mod smullt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smullt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smullt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -222,6 +402,30 @@ pub mod umullb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umullb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umullb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -249,6 +453,30 @@ pub mod umullt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umullt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umullt_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_clong.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_clong.rs index 51cef361..05368207 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_clong.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_clong.rs @@ -12,6 +12,30 @@ pub mod saddlbt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "saddlbt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn saddlbt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod ssublbt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ssublbt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ssublbt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod ssubltb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ssubltb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ssubltb_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_eorx.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_eorx.rs index 12211ee3..250637a6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_eorx.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_eorx.rs @@ -12,6 +12,30 @@ pub mod eorbt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eorbt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn eorbt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod eortb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eortb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn eortb_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_mmla.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_mmla.rs index bad1bdfe..836255d5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_mmla.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_mmla.rs @@ -12,6 +12,24 @@ pub mod smmla_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smmla_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn smmla_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod usmmla_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usmmla_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn usmmla_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod ummla_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ummla_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ummla_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_perm_bit.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_perm_bit.rs index 7887aa4c..c584fe1f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_perm_bit.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_perm_bit.rs @@ -12,6 +12,30 @@ pub mod bext_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bext_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn bext_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod bdep_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bdep_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn bdep_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod bgrp_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bgrp_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn bgrp_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_shift_long.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_shift_long.rs index ce14c3a8..77937332 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_shift_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_constructive/sve_intx_shift_long.rs @@ -12,6 +12,36 @@ pub mod sshllb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sshllb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sshllb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod sshllt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sshllt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sshllt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod ushllb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ushllb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn ushllb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod ushllt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ushllt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn ushllt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_const.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_const.rs index 882a652f..0ed0a695 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_const.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_const.rs @@ -12,6 +12,24 @@ pub mod sm4ekey_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sm4ekey_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sm4ekey_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod rax1_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rax1_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn rax1_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_dest.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_dest.rs index 987b02c5..550e7576 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_dest.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_dest.rs @@ -12,6 +12,18 @@ pub mod aese_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aese_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn aese_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -33,6 +45,18 @@ pub mod aesd_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesd_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn aesd_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -54,6 +78,18 @@ pub mod sm4e_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sm4e_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sm4e_z_zz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi2.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi2.rs index f411b8fc..31f464ea 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi2.rs @@ -12,6 +12,24 @@ pub mod aese_mz_zzi_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aese_mz_zzi_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aese_mz_zzi_2x1( i2: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod aesd_mz_zzi_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesd_mz_zzi_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aesd_mz_zzi_2x1( i2: ::aarchmrs_types::BitValue<2>, @@ -62,6 +98,24 @@ pub mod aesemc_mz_zzi_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesemc_mz_zzi_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aesemc_mz_zzi_2x1( i2: ::aarchmrs_types::BitValue<2>, @@ -87,6 +141,24 @@ pub mod aesdimc_mz_zzi_2x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesdimc_mz_zzi_2x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aesdimc_mz_zzi_2x1( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi4.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi4.rs index dab981cb..edb2aedb 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi4.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_binary_multi4.rs @@ -12,6 +12,24 @@ pub mod aese_mz_zzi_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aese_mz_zzi_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aese_mz_zzi_4x1( i2: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod aesd_mz_zzi_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesd_mz_zzi_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aesd_mz_zzi_4x1( i2: ::aarchmrs_types::BitValue<2>, @@ -62,6 +98,24 @@ pub mod aesemc_mz_zzi_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesemc_mz_zzi_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aesemc_mz_zzi_4x1( i2: ::aarchmrs_types::BitValue<2>, @@ -87,6 +141,24 @@ pub mod aesdimc_mz_zzi_4x1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesdimc_mz_zzi_4x1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn aesdimc_mz_zzi_4x1( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmlal_multi.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmlal_multi.rs index 3d62c98d..e70e9e23 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmlal_multi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmlal_multi.rs @@ -12,6 +12,24 @@ pub mod pmlal_mz_zzzw_1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmlal_mz_zzzw_1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn pmlal_mz_zzzw_1x2( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmull_multi.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmull_multi.rs index 649ba3c2..a9a0b9c9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmull_multi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_pmull_multi.rs @@ -12,6 +12,24 @@ pub mod pmull_mz_zzw_1x2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmull_mz_zzw_1x2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn pmull_mz_zzw_1x2( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_unary.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_unary.rs index e5de6624..3efc27b7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_unary.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_crypto/sve_crypto_unary.rs @@ -12,6 +12,12 @@ pub mod aesmc_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesmc_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; #[inline] pub const fn aesmc_z_z_( Zdn: ::aarchmrs_types::BitValue<5>, @@ -30,6 +36,12 @@ pub mod aesimc_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "aesimc_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; #[inline] pub const fn aesimc_z_z_( Zdn: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_dot2/sve_intx_dot2.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_dot2/sve_intx_dot2.rs index a0680379..e7019bff 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_dot2/sve_intx_dot2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_dot2/sve_intx_dot2.rs @@ -12,6 +12,24 @@ pub mod sdot_z32_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_z32_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sdot_z32_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod udot_z32_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_z32_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn udot_z32_zzz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_dot2_by_indexed_elem/sve_intx_dot2_by_indexed_elem.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_dot2_by_indexed_elem/sve_intx_dot2_by_indexed_elem.rs index c148f2ad..538e341e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_dot2_by_indexed_elem/sve_intx_dot2_by_indexed_elem.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_dot2_by_indexed_elem/sve_intx_dot2_by_indexed_elem.rs @@ -12,6 +12,30 @@ pub mod sdot_z32_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_z32_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn sdot_z32_zzzi_( i2: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod udot_z32_zzzi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_z32_zzzi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn udot_z32_zzzi_( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histcnt/sve_intx_histcnt.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histcnt/sve_intx_histcnt.rs index c4db78a5..1c00a82c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histcnt/sve_intx_histcnt.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histcnt/sve_intx_histcnt.rs @@ -12,6 +12,36 @@ pub mod histcnt_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "histcnt_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn histcnt_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_histseg.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_histseg.rs index fd217a8d..9e9981e8 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_histseg.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_histseg.rs @@ -12,6 +12,30 @@ pub mod histseg_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "histseg_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn histseg_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_16.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_16.rs index 119397ed..f692043e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_16.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_16.rs @@ -12,6 +12,36 @@ pub mod luti2_z_zz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti2_z_zz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 2u32; #[inline] pub const fn luti2_z_zz_16( i3h: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_8.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_8.rs index 4e00f4cb..fbd83846 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_8.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut2_8.rs @@ -12,6 +12,30 @@ pub mod luti2_z_zz_8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti2_z_zz_8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn luti2_z_zz_8( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_16.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_16.rs index a2c58abb..2e7bb1fe 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_16.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_16.rs @@ -12,6 +12,30 @@ pub mod luti4_z_zz_2x16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_z_zz_2x16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn luti4_z_zz_2x16( i2: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod luti4_z_zz_1x16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_z_zz_1x16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn luti4_z_zz_1x16( i2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_8.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_8.rs index 92027d09..08a2d7ed 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_8.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut4_8.rs @@ -12,6 +12,30 @@ pub mod luti4_z_zz_8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti4_z_zz_8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn luti4_z_zz_8( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_16.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_16.rs index 7b36c021..1f350a47 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_16.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_16.rs @@ -12,6 +12,30 @@ pub mod luti6_z_zzz_16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti6_z_zzz_16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn luti6_z_zzz_16( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_8.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_8.rs index 775bccf7..82c84069 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_8.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_histseg_lut/sve_intx_lut6_8.rs @@ -12,6 +12,24 @@ pub mod luti6_z_zzz_8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "luti6_z_zzz_8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn luti6_z_zzz_8( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cdot.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cdot.rs index 83d78cd1..623976ce 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cdot.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cdot.rs @@ -12,6 +12,36 @@ pub mod cdot_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cdot_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cdot_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cmla.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cmla.rs index b8fde330..b62ad745 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cmla.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_cmla.rs @@ -12,6 +12,36 @@ pub mod cmla_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cmla_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cmla_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod sqrdcmlah_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdcmlah_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdcmlah_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_dot.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_dot.rs index 0ab7e2b5..777f744d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_dot.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_dot.rs @@ -12,6 +12,30 @@ pub mod sdot_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; #[inline] pub const fn sdot_z_zzz_( size: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,24 @@ pub mod sdot_z16_zzz_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sdot_z16_zzz_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn sdot_z16_zzz_h( Zm: ::aarchmrs_types::BitValue<5>, @@ -63,6 +105,30 @@ pub mod udot_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 1u32; #[inline] pub const fn udot_z_zzz_( size: ::aarchmrs_types::BitValue<1>, @@ -90,6 +156,24 @@ pub mod udot_z16_zzz_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "udot_z16_zzz_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn udot_z16_zzz_h( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mixed_dot.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mixed_dot.rs index f5da74bf..c45de3e1 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mixed_dot.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mixed_dot.rs @@ -12,6 +12,24 @@ pub mod usdot_z_zzz_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usdot_z_zzz_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn usdot_z_zzz_s( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mlal_long.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mlal_long.rs index f6f5da51..603d2cbd 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mlal_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_mlal_long.rs @@ -12,6 +12,30 @@ pub mod smlalb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlalb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smlalb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod smlslb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlslb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smlslb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod smlalt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlalt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smlalt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod smlslt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smlslt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smlslt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod umlalb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlalb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umlalb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -147,6 +267,30 @@ pub mod umlslb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlslb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umlslb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -174,6 +318,30 @@ pub mod umlalt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlalt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umlalt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -201,6 +369,30 @@ pub mod umlslt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umlslt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umlslt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlal_long.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlal_long.rs index fe24ca9f..2dbfde79 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlal_long.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlal_long.rs @@ -12,6 +12,30 @@ pub mod sqdmlalb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlalb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlalb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod sqdmlslb_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlslb_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlslb_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod sqdmlalt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlalt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlalt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod sqdmlslt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlslt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlslt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlalbt.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlalbt.rs index 58d295b4..7b663bfb 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlalbt.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qdmlalbt.rs @@ -12,6 +12,30 @@ pub mod sqdmlalbt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlalbt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlalbt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod sqdmlslbt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdmlslbt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdmlslbt_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qrdmlah.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qrdmlah.rs index 55e000b6..2f9f7fc4 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qrdmlah.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_muladd_unpred/sve_intx_qrdmlah.rs @@ -12,6 +12,30 @@ pub mod sqrdmlah_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlah_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdmlah_z_zzz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod sqrdmlsh_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrdmlsh_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqrdmlsh_z_zzz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_arith_narrow.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_arith_narrow.rs index 8ade5ec3..343a885c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_arith_narrow.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_arith_narrow.rs @@ -12,6 +12,30 @@ pub mod addhnb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addhnb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn addhnb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod raddhnb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "raddhnb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn raddhnb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod subhnb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "subhnb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn subhnb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod rsubhnb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rsubhnb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn rsubhnb_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod addhnt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addhnt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn addhnt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -147,6 +267,30 @@ pub mod raddhnt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "raddhnt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn raddhnt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -174,6 +318,30 @@ pub mod subhnt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "subhnt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn subhnt_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -201,6 +369,30 @@ pub mod rsubhnt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rsubhnt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn rsubhnt_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_extract_narrow.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_extract_narrow.rs index 2b642228..acdafa6f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_extract_narrow.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_extract_narrow.rs @@ -12,6 +12,30 @@ pub mod sqxtnb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqxtnb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqxtnb_z_zz_( tszh: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod sqxtunb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqxtunb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqxtunb_z_zz_( tszh: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod sqxtnt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqxtnt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqxtnt_z_zz_( tszh: ::aarchmrs_types::BitValue<1>, @@ -93,6 +165,30 @@ pub mod sqxtunt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqxtunt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqxtunt_z_zz_( tszh: ::aarchmrs_types::BitValue<1>, @@ -120,6 +216,30 @@ pub mod uqxtnb_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqxtnb_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn uqxtnb_z_zz_( tszh: ::aarchmrs_types::BitValue<1>, @@ -147,6 +267,30 @@ pub mod uqxtnt_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqxtnt_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn uqxtnt_z_zz_( tszh: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_extract_narrow.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_extract_narrow.rs index 5a943609..73c2829c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_extract_narrow.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_extract_narrow.rs @@ -12,6 +12,18 @@ pub mod sqcvtn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvtn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn sqcvtn_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod sqcvtun_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqcvtun_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn sqcvtun_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, @@ -56,6 +80,18 @@ pub mod uqcvtn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqcvtn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; #[inline] pub const fn uqcvtn_z_mz2_( Zn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_shift_narrow.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_shift_narrow.rs index 84a823a7..b45fce02 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_shift_narrow.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_multi_shift_narrow.rs @@ -12,6 +12,24 @@ pub mod sqrshrn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqrshrn_z_mz2_( imm4: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,24 @@ pub mod sqrshrn_z_mz2_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrn_z_mz2_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn sqrshrn_z_mz2_b( imm3: ::aarchmrs_types::BitValue<3>, @@ -62,6 +98,24 @@ pub mod sqrshrun_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrun_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn sqrshrun_z_mz2_( imm4: ::aarchmrs_types::BitValue<4>, @@ -87,6 +141,24 @@ pub mod sqrshrun_z_mz2_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrun_z_mz2_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn sqrshrun_z_mz2_b( imm3: ::aarchmrs_types::BitValue<3>, @@ -112,6 +184,30 @@ pub mod sqshrn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshrn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn sqshrn_z_mz2_( tsize: ::aarchmrs_types::BitValue<2>, @@ -139,6 +235,30 @@ pub mod sqshrun_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshrun_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn sqshrun_z_mz2_( tsize: ::aarchmrs_types::BitValue<2>, @@ -166,6 +286,24 @@ pub mod uqrshrn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshrn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn uqrshrn_z_mz2_( imm4: ::aarchmrs_types::BitValue<4>, @@ -191,6 +329,24 @@ pub mod uqrshrn_z_mz2_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshrn_z_mz2_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn uqrshrn_z_mz2_b( imm3: ::aarchmrs_types::BitValue<3>, @@ -216,6 +372,30 @@ pub mod uqshrn_z_mz2_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqshrn_z_mz2_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsize_WIDTH: u32 = 2u32; #[inline] pub const fn uqshrn_z_mz2_( tsize: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_shift_narrow.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_shift_narrow.rs index d05aad79..30c33a4a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_shift_narrow.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_narrowing/sve_intx_shift_narrow.rs @@ -12,6 +12,36 @@ pub mod sqshrunb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshrunb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqshrunb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod sqrshrunb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrunb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqrshrunb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod shrnb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "shrnb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn shrnb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod rshrnb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rshrnb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn rshrnb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod sqshrnb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshrnb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqshrnb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -157,6 +307,36 @@ pub mod sqrshrnb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrnb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqrshrnb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod sqshrunt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshrunt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqshrunt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -215,6 +425,36 @@ pub mod sqrshrunt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrunt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqrshrunt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -244,6 +484,36 @@ pub mod shrnt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "shrnt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn shrnt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -273,6 +543,36 @@ pub mod rshrnt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rshrnt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn rshrnt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -302,6 +602,36 @@ pub mod sqshrnt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshrnt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqshrnt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -331,6 +661,36 @@ pub mod sqrshrnt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshrnt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn sqrshrnt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -360,6 +720,36 @@ pub mod uqshrnb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqshrnb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn uqshrnb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -389,6 +779,36 @@ pub mod uqrshrnb_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshrnb_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn uqrshrnb_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -418,6 +838,36 @@ pub mod uqshrnt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqshrnt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn uqshrnt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, @@ -447,6 +897,36 @@ pub mod uqrshrnt_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshrnt_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; #[inline] pub const fn uqrshrnt_z_zi_( tszh: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_accumulate_long_pairs.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_accumulate_long_pairs.rs index 9f5d57ff..5bafef2b 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_accumulate_long_pairs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_accumulate_long_pairs.rs @@ -12,6 +12,30 @@ pub mod sadalp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sadalp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sadalp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod uadalp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uadalp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uadalp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_arith_binary_pairs.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_arith_binary_pairs.rs index 77bc73e6..5cbc033c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_arith_binary_pairs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_arith_binary_pairs.rs @@ -12,6 +12,30 @@ pub mod subp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "subp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn subp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod addp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "addp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn addp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod smaxp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smaxp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smaxp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod sminp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sminp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sminp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod umaxp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umaxp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umaxp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod uminp_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uminp_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uminp_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_bin_pred_shift_sat_round.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_bin_pred_shift_sat_round.rs index a74bb459..9fc9e0ee 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_bin_pred_shift_sat_round.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_bin_pred_shift_sat_round.rs @@ -12,6 +12,30 @@ pub mod srshl_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srshl_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn srshl_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod srshlr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srshlr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn srshlr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod sqshl_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshl_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqshl_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod sqrshl_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshl_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqrshl_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod sqshlr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqshlr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqshlr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod sqrshlr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqrshlr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqrshlr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod urshl_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urshl_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urshl_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod urshlr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urshlr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urshlr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -220,6 +412,30 @@ pub mod uqshl_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqshl_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqshl_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -246,6 +462,30 @@ pub mod uqrshl_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshl_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqrshl_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -272,6 +512,30 @@ pub mod uqshlr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqshlr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqshlr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -298,6 +562,30 @@ pub mod uqrshlr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqrshlr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqrshlr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary.rs index 8df88f5c..358c3529 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary.rs @@ -12,6 +12,30 @@ pub mod shadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "shadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn shadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod shsub_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "shsub_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn shsub_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod srhadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "srhadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn srhadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod shsubr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "shsubr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn shsubr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod uhadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uhadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uhadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod uhsub_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uhsub_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uhsub_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod urhadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urhadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urhadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod uhsubr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uhsubr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uhsubr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary_sat.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary_sat.rs index b591f940..a3e8f40f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary_sat.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_binary_sat.rs @@ -12,6 +12,30 @@ pub mod sqadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sqsub_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqsub_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqsub_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod suqadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "suqadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn suqadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod usqadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "usqadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn usqadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod sqsubr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqsubr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqsubr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod uqadd_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqadd_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqadd_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod uqsub_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqsub_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqsub_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod uqsubr_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqsubr_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqsubr_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_unary.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_unary.rs index 41d6473c..082672c1 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_unary.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_predicated/sve_intx_pred_arith_unary.rs @@ -12,6 +12,30 @@ pub mod urecpe_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urecpe_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urecpe_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod urecpe_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "urecpe_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn urecpe_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod ursqrte_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ursqrte_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ursqrte_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod ursqrte_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ursqrte_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ursqrte_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod sqabs_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqabs_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqabs_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod sqabs_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqabs_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqabs_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod sqneg_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqneg_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqneg_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod sqneg_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqneg_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqneg_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_intx_string/sve_intx_match.rs b/aarchmrs-instructions/src/A64/sve/sve_intx_string/sve_intx_match.rs index 5bb8970c..28378a4e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_intx_string/sve_intx_match.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_intx_string/sve_intx_match.rs @@ -12,6 +12,36 @@ pub mod match_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "match_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn match_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,36 @@ pub mod nmatch_p_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "nmatch_p_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn nmatch_p_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_dup_mask_imm.rs b/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_dup_mask_imm.rs index 25094859..9e71e4fe 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_dup_mask_imm.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_dup_mask_imm.rs @@ -12,6 +12,18 @@ pub mod dupm_z_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "dupm_z_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_WIDTH: u32 = 13u32; #[inline] pub const fn dupm_z_i_( imm13: ::aarchmrs_types::BitValue<13>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_log_imm.rs b/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_log_imm.rs index 07ebe758..4d3de83c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_log_imm.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_maskimm/sve_int_log_imm.rs @@ -12,6 +12,18 @@ pub mod orr_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orr_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_WIDTH: u32 = 13u32; #[inline] pub const fn orr_z_zi_( imm13: ::aarchmrs_types::BitValue<13>, @@ -31,6 +43,18 @@ pub mod eor_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eor_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_WIDTH: u32 = 13u32; #[inline] pub const fn eor_z_zi_( imm13: ::aarchmrs_types::BitValue<13>, @@ -50,6 +74,18 @@ pub mod and_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "and_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm13_WIDTH: u32 = 13u32; #[inline] pub const fn and_z_zi_( imm13: ::aarchmrs_types::BitValue<13>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_fill.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_fill.rs index 44098f2d..f654493f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_fill.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_fill.rs @@ -12,6 +12,30 @@ pub mod ldr_z_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldr_z_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_WIDTH: u32 = 6u32; #[inline] pub const fn ldr_z_bi_( imm9h: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_a.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_a.rs index eaba0b58..3dc4ae2e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_a.rs @@ -12,6 +12,36 @@ pub mod ld1sh_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sh_z_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod ld1h_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1h_z_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod ldff1sh_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sh_z_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod ldff1h_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1h_z_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_b.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_b.rs index 8ef15f4f..f79e81f1 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_sv_b.rs @@ -12,6 +12,36 @@ pub mod ld1w_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1w_z_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod ldff1w_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1w_z_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vi.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vi.rs index 8896ddab..c7243ded 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vi.rs @@ -12,6 +12,30 @@ pub mod ld1sb_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sb_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld1sh_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sh_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld1w_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ld1b_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ld1h_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ldff1sb_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sb_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ldff1sh_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sh_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ldff1w_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1w_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod ldff1b_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1b_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod ldff1h_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1h_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vs.rs index 6b4fc8cb..2668e6fe 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gld_vs.rs @@ -12,6 +12,36 @@ pub mod ld1sb_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sb_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod ld1sh_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sh_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod ld1w_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1w_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod ld1b_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1b_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod ld1h_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1h_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -157,6 +307,36 @@ pub mod ldff1sb_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sb_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod ldff1sh_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sh_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -215,6 +425,36 @@ pub mod ldff1w_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1w_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -244,6 +484,36 @@ pub mod ldff1b_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1b_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -273,6 +543,36 @@ pub mod ldff1h_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1h_z_p_bz_s_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gldnt_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gldnt_vs.rs index 59205777..c38e6344 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gldnt_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_gldnt_vs.rs @@ -12,6 +12,30 @@ pub mod ldnt1sb_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1sb_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1sb_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ldnt1sh_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1sh_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1sh_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ldnt1w_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1w_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ldnt1b_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1b_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ldnt1h_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1h_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_pfill.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_pfill.rs index b78e314a..ed713ac3 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_pfill.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_pfill.rs @@ -12,6 +12,30 @@ pub mod ldr_p_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldr_p_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_WIDTH: u32 = 6u32; #[inline] pub const fn ldr_p_bi_( imm9h: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_sv.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_sv.rs index 695b763c..099edc04 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_sv.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_sv.rs @@ -12,6 +12,36 @@ pub mod prfb_i_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfb_i_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfb_i_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,36 @@ pub mod prfh_i_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfh_i_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfh_i_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -72,6 +132,36 @@ pub mod prfw_i_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfw_i_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfw_i_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -102,6 +192,36 @@ pub mod prfd_i_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfd_i_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfd_i_p_bz_s_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_vi.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_vi.rs index 5c36fff2..13a8240c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_vi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_32b_prfm_vi.rs @@ -12,6 +12,30 @@ pub mod prfb_i_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfb_i_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfb_i_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod prfh_i_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfh_i_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfh_i_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod prfw_i_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfw_i_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfw_i_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod prfd_i_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfd_i_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfd_i_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_ld_dup.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_ld_dup.rs index 5c0ce5f3..24f15d94 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_ld_dup.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_ld_dup.rs @@ -12,6 +12,30 @@ pub mod ld1rb_z_p_bi_u8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rb_z_p_bi_u8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rb_z_p_bi_u8( imm6: ::aarchmrs_types::BitValue<6>, @@ -38,6 +62,30 @@ pub mod ld1rb_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rb_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rb_z_p_bi_u16( imm6: ::aarchmrs_types::BitValue<6>, @@ -64,6 +112,30 @@ pub mod ld1rb_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rb_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rb_z_p_bi_u32( imm6: ::aarchmrs_types::BitValue<6>, @@ -90,6 +162,30 @@ pub mod ld1rb_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rb_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rb_z_p_bi_u64( imm6: ::aarchmrs_types::BitValue<6>, @@ -116,6 +212,30 @@ pub mod ld1rsw_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rsw_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rsw_z_p_bi_s64( imm6: ::aarchmrs_types::BitValue<6>, @@ -142,6 +262,30 @@ pub mod ld1rh_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rh_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rh_z_p_bi_u16( imm6: ::aarchmrs_types::BitValue<6>, @@ -168,6 +312,30 @@ pub mod ld1rh_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rh_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rh_z_p_bi_u32( imm6: ::aarchmrs_types::BitValue<6>, @@ -194,6 +362,30 @@ pub mod ld1rh_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rh_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rh_z_p_bi_u64( imm6: ::aarchmrs_types::BitValue<6>, @@ -220,6 +412,30 @@ pub mod ld1rsh_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rsh_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rsh_z_p_bi_s64( imm6: ::aarchmrs_types::BitValue<6>, @@ -246,6 +462,30 @@ pub mod ld1rsh_z_p_bi_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rsh_z_p_bi_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rsh_z_p_bi_s32( imm6: ::aarchmrs_types::BitValue<6>, @@ -272,6 +512,30 @@ pub mod ld1rw_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rw_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rw_z_p_bi_u32( imm6: ::aarchmrs_types::BitValue<6>, @@ -298,6 +562,30 @@ pub mod ld1rw_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rw_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rw_z_p_bi_u64( imm6: ::aarchmrs_types::BitValue<6>, @@ -324,6 +612,30 @@ pub mod ld1rsb_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rsb_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rsb_z_p_bi_s64( imm6: ::aarchmrs_types::BitValue<6>, @@ -350,6 +662,30 @@ pub mod ld1rsb_z_p_bi_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rsb_z_p_bi_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rsb_z_p_bi_s32( imm6: ::aarchmrs_types::BitValue<6>, @@ -376,6 +712,30 @@ pub mod ld1rsb_z_p_bi_s16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rsb_z_p_bi_s16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rsb_z_p_bi_s16( imm6: ::aarchmrs_types::BitValue<6>, @@ -402,6 +762,30 @@ pub mod ld1rd_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rd_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn ld1rd_z_p_bi_u64( imm6: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_si.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_si.rs index 9e00def2..3be2d36f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_si.rs @@ -12,6 +12,30 @@ pub mod prfb_i_p_bi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfb_i_p_bi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn prfb_i_p_bi_s( imm6: ::aarchmrs_types::BitValue<6>, @@ -39,6 +63,30 @@ pub mod prfh_i_p_bi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfh_i_p_bi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn prfh_i_p_bi_s( imm6: ::aarchmrs_types::BitValue<6>, @@ -66,6 +114,30 @@ pub mod prfw_i_p_bi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfw_i_p_bi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn prfw_i_p_bi_s( imm6: ::aarchmrs_types::BitValue<6>, @@ -93,6 +165,30 @@ pub mod prfd_i_p_bi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfd_i_p_bi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn prfd_i_p_bi_s( imm6: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_ss.rs index 76dd3c06..21d86ba8 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem32/sve_mem_prfm_ss.rs @@ -12,6 +12,30 @@ pub mod prfb_i_p_br_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfb_i_p_br_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn prfb_i_p_br_s( Rm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod prfh_i_p_br_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfh_i_p_br_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn prfh_i_p_br_s( Rm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod prfw_i_p_br_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfw_i_p_br_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn prfw_i_p_br_s( Rm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod prfd_i_p_br_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfd_i_p_br_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn prfd_i_p_br_s( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv.rs index 0e62d2f0..f7ab6861 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv.rs @@ -12,6 +12,36 @@ pub mod ld1sh_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sh_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod ld1sw_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sw_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sw_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod ld1d_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1d_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod ld1h_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1h_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod ld1w_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1w_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -157,6 +307,36 @@ pub mod ldff1sh_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sh_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod ldff1sw_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sw_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sw_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -215,6 +425,36 @@ pub mod ldff1d_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1d_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1d_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -244,6 +484,36 @@ pub mod ldff1h_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1h_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -273,6 +543,36 @@ pub mod ldff1w_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1w_z_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv2.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv2.rs index 4a03ed9d..d6fff5b9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_sv2.rs @@ -12,6 +12,30 @@ pub mod ld1sh_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sh_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld1sw_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sw_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sw_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld1d_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ld1h_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ld1w_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ldff1sh_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sh_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ldff1sw_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sw_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sw_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ldff1d_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1d_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1d_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod ldff1h_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1h_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod ldff1w_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1w_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vi.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vi.rs index 031e936a..1905a496 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vi.rs @@ -12,6 +12,30 @@ pub mod ld1sb_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sb_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld1sh_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sh_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld1sw_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sw_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sw_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ld1d_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ld1b_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ld1h_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ld1w_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ldff1sb_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sb_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod ldff1sh_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sh_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod ldff1sw_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sw_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sw_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -272,6 +512,30 @@ pub mod ldff1d_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1d_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1d_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -298,6 +562,30 @@ pub mod ldff1b_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1b_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -324,6 +612,30 @@ pub mod ldff1h_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1h_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -350,6 +662,30 @@ pub mod ldff1w_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1w_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs.rs index c425aae9..6a847ee0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs.rs @@ -12,6 +12,36 @@ pub mod ld1sb_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sb_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod ld1sh_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sh_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,36 @@ pub mod ld1sw_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sw_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1sw_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -99,6 +189,36 @@ pub mod ld1d_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1d_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -128,6 +248,36 @@ pub mod ld1b_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1b_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -157,6 +307,36 @@ pub mod ld1h_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1h_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -186,6 +366,36 @@ pub mod ld1w_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ld1w_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -215,6 +425,36 @@ pub mod ldff1sb_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sb_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -244,6 +484,36 @@ pub mod ldff1sh_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sh_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -273,6 +543,36 @@ pub mod ldff1sw_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sw_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1sw_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -302,6 +602,36 @@ pub mod ldff1d_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1d_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1d_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -331,6 +661,36 @@ pub mod ldff1b_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1b_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -360,6 +720,36 @@ pub mod ldff1h_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1h_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, @@ -389,6 +779,36 @@ pub mod ldff1w_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn ldff1w_z_p_bz_d_x32_unscaled( xs: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs2.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs2.rs index 855e3600..c1ca123f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gld_vs2.rs @@ -12,6 +12,30 @@ pub mod ld1sb_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sb_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld1sh_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sh_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld1sw_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sw_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sw_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ld1d_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ld1b_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ld1h_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ld1w_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ldff1sb_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sb_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod ldff1sh_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sh_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod ldff1sw_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sw_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sw_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -272,6 +512,30 @@ pub mod ldff1d_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1d_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1d_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -298,6 +562,30 @@ pub mod ldff1b_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1b_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -324,6 +612,30 @@ pub mod ldff1h_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1h_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -350,6 +662,30 @@ pub mod ldff1w_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1w_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldnt_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldnt_vs.rs index 83ea2852..09c1e904 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldnt_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldnt_vs.rs @@ -12,6 +12,30 @@ pub mod ldnt1sb_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1sb_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1sb_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ldnt1sh_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1sh_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1sh_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ldnt1sw_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1sw_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1sw_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ldnt1d_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1d_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ldnt1b_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1b_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ldnt1h_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1h_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ldnt1w_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1w_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldq_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldq_vs.rs index bd813a65..057eabbf 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldq_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_gldq_vs.rs @@ -12,6 +12,30 @@ pub mod ld1q_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1q_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1q_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv.rs index 41e7ae7e..a4638552 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv.rs @@ -12,6 +12,36 @@ pub mod prfb_i_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfb_i_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfb_i_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,36 @@ pub mod prfh_i_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfh_i_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfh_i_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -72,6 +132,36 @@ pub mod prfw_i_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfw_i_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfw_i_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, @@ -102,6 +192,36 @@ pub mod prfd_i_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfd_i_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; #[inline] pub const fn prfd_i_p_bz_d_x32_scaled( xs: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv2.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv2.rs index 9554a133..3ed4528f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_sv2.rs @@ -12,6 +12,30 @@ pub mod prfb_i_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfb_i_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn prfb_i_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod prfh_i_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfh_i_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn prfh_i_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod prfw_i_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfw_i_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn prfw_i_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod prfd_i_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfd_i_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn prfd_i_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_vi.rs b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_vi.rs index 2d89ce55..762e2daa 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_vi.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_mem64/sve_mem_64b_prfm_vi.rs @@ -12,6 +12,30 @@ pub mod prfb_i_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfb_i_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfb_i_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -39,6 +63,30 @@ pub mod prfh_i_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfh_i_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfh_i_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -66,6 +114,30 @@ pub mod prfw_i_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfw_i_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfw_i_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -93,6 +165,30 @@ pub mod prfd_i_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "prfd_i_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_prfop_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn prfd_i_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si.rs index 818d6fd2..38a62b59 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si.rs @@ -12,6 +12,30 @@ pub mod ld1b_z_p_bi_u8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_bi_u8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_z_p_bi_u8( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod ld1b_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_z_p_bi_u16( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod ld1b_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod ld1b_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1b_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod ld1sw_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sw_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1sw_z_p_bi_s64( imm4: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod ld1h_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1h_z_p_bi_u16( imm4: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod ld1h_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1h_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod ld1h_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1h_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, @@ -220,6 +412,30 @@ pub mod ld1sh_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1sh_z_p_bi_s64( imm4: ::aarchmrs_types::BitValue<4>, @@ -246,6 +462,30 @@ pub mod ld1sh_z_p_bi_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_bi_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1sh_z_p_bi_s32( imm4: ::aarchmrs_types::BitValue<4>, @@ -272,6 +512,30 @@ pub mod ld1w_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1w_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -298,6 +562,30 @@ pub mod ld1w_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1w_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, @@ -324,6 +612,30 @@ pub mod ld1sb_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1sb_z_p_bi_s64( imm4: ::aarchmrs_types::BitValue<4>, @@ -350,6 +662,30 @@ pub mod ld1sb_z_p_bi_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_bi_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1sb_z_p_bi_s32( imm4: ::aarchmrs_types::BitValue<4>, @@ -376,6 +712,30 @@ pub mod ld1sb_z_p_bi_s16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_bi_s16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1sb_z_p_bi_s16( imm4: ::aarchmrs_types::BitValue<4>, @@ -402,6 +762,30 @@ pub mod ld1d_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1d_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si_q.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si_q.rs index 8cede19d..67c1e659 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si_q.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_si_q.rs @@ -12,6 +12,30 @@ pub mod ld1w_z_p_bi_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_bi_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1w_z_p_bi_u128( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod ld1d_z_p_bi_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_bi_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1d_z_p_bi_u128( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss.rs index aac830da..5bc3d495 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss.rs @@ -12,6 +12,30 @@ pub mod ld1b_z_p_br_u8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_br_u8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_z_p_br_u8( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld1b_z_p_br_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_br_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_z_p_br_u16( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld1b_z_p_br_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_br_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_z_p_br_u32( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ld1b_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1b_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1b_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ld1sw_z_p_br_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sw_z_p_br_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sw_z_p_br_s64( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ld1h_z_p_br_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_br_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_z_p_br_u16( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ld1h_z_p_br_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_br_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_z_p_br_u32( Rm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ld1h_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1h_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1h_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod ld1sh_z_p_br_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_br_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sh_z_p_br_s64( Rm: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod ld1sh_z_p_br_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sh_z_p_br_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sh_z_p_br_s32( Rm: ::aarchmrs_types::BitValue<5>, @@ -272,6 +512,30 @@ pub mod ld1w_z_p_br_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_br_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_z_p_br_u32( Rm: ::aarchmrs_types::BitValue<5>, @@ -298,6 +562,30 @@ pub mod ld1w_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, @@ -324,6 +612,30 @@ pub mod ld1sb_z_p_br_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_br_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sb_z_p_br_s64( Rm: ::aarchmrs_types::BitValue<5>, @@ -350,6 +662,30 @@ pub mod ld1sb_z_p_br_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_br_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sb_z_p_br_s32( Rm: ::aarchmrs_types::BitValue<5>, @@ -376,6 +712,30 @@ pub mod ld1sb_z_p_br_s16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1sb_z_p_br_s16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1sb_z_p_br_s16( Rm: ::aarchmrs_types::BitValue<5>, @@ -402,6 +762,30 @@ pub mod ld1d_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss_q.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss_q.rs index fa8521dd..583765ee 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss_q.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cld_ss_q.rs @@ -12,6 +12,30 @@ pub mod ld1w_z_p_br_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1w_z_p_br_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1w_z_p_br_u128( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld1d_z_p_br_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1d_z_p_br_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1d_z_p_br_u128( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldff_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldff_ss.rs index df441c9d..8ca0dff7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldff_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldff_ss.rs @@ -12,6 +12,30 @@ pub mod ldff1b_z_p_br_u8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_br_u8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1b_z_p_br_u8( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ldff1b_z_p_br_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_br_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1b_z_p_br_u16( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ldff1b_z_p_br_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_br_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1b_z_p_br_u32( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ldff1b_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1b_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1b_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ldff1sw_z_p_br_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sw_z_p_br_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sw_z_p_br_s64( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ldff1h_z_p_br_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_br_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1h_z_p_br_u16( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ldff1h_z_p_br_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_br_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1h_z_p_br_u32( Rm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ldff1h_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1h_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1h_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod ldff1sh_z_p_br_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_br_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sh_z_p_br_s64( Rm: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod ldff1sh_z_p_br_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sh_z_p_br_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sh_z_p_br_s32( Rm: ::aarchmrs_types::BitValue<5>, @@ -272,6 +512,30 @@ pub mod ldff1w_z_p_br_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_br_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1w_z_p_br_u32( Rm: ::aarchmrs_types::BitValue<5>, @@ -298,6 +562,30 @@ pub mod ldff1w_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1w_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1w_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, @@ -324,6 +612,30 @@ pub mod ldff1sb_z_p_br_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_br_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sb_z_p_br_s64( Rm: ::aarchmrs_types::BitValue<5>, @@ -350,6 +662,30 @@ pub mod ldff1sb_z_p_br_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_br_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sb_z_p_br_s32( Rm: ::aarchmrs_types::BitValue<5>, @@ -376,6 +712,30 @@ pub mod ldff1sb_z_p_br_s16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1sb_z_p_br_s16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1sb_z_p_br_s16( Rm: ::aarchmrs_types::BitValue<5>, @@ -402,6 +762,30 @@ pub mod ldff1d_z_p_br_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldff1d_z_p_br_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldff1d_z_p_br_u64( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnf_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnf_si.rs index 1f7f3dba..6f9ebf5f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnf_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnf_si.rs @@ -12,6 +12,30 @@ pub mod ldnf1b_z_p_bi_u8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1b_z_p_bi_u8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1b_z_p_bi_u8( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod ldnf1b_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1b_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1b_z_p_bi_u16( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod ldnf1b_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1b_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1b_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod ldnf1b_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1b_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1b_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod ldnf1sw_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1sw_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1sw_z_p_bi_s64( imm4: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod ldnf1h_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1h_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1h_z_p_bi_u16( imm4: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod ldnf1h_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1h_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1h_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod ldnf1h_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1h_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1h_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, @@ -220,6 +412,30 @@ pub mod ldnf1sh_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1sh_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1sh_z_p_bi_s64( imm4: ::aarchmrs_types::BitValue<4>, @@ -246,6 +462,30 @@ pub mod ldnf1sh_z_p_bi_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1sh_z_p_bi_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1sh_z_p_bi_s32( imm4: ::aarchmrs_types::BitValue<4>, @@ -272,6 +512,30 @@ pub mod ldnf1w_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1w_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1w_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -298,6 +562,30 @@ pub mod ldnf1w_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1w_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1w_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, @@ -324,6 +612,30 @@ pub mod ldnf1sb_z_p_bi_s64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1sb_z_p_bi_s64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1sb_z_p_bi_s64( imm4: ::aarchmrs_types::BitValue<4>, @@ -350,6 +662,30 @@ pub mod ldnf1sb_z_p_bi_s32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1sb_z_p_bi_s32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1sb_z_p_bi_s32( imm4: ::aarchmrs_types::BitValue<4>, @@ -376,6 +712,30 @@ pub mod ldnf1sb_z_p_bi_s16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1sb_z_p_bi_s16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1sb_z_p_bi_s16( imm4: ::aarchmrs_types::BitValue<4>, @@ -402,6 +762,30 @@ pub mod ldnf1d_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnf1d_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnf1d_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_si.rs index ffcd1f3e..2d63d1f0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_si.rs @@ -12,6 +12,30 @@ pub mod ldnt1b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod ldnt1h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod ldnt1w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod ldnt1d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ldnt1d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_ss.rs index fc371999..1f111fef 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_cldnt_ss.rs @@ -12,6 +12,30 @@ pub mod ldnt1b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ldnt1h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ldnt1w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ldnt1d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ldnt1d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ldnt1d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_si.rs index 64b40f57..78eb1cd3 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_si.rs @@ -12,6 +12,30 @@ pub mod ld2b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld2b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod ld3b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld3b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod ld4b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld4b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod ld2h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld2h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod ld3h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld3h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod ld4h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld4h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod ld2w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld2w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod ld3w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld3w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -220,6 +412,30 @@ pub mod ld4w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld4w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -246,6 +462,30 @@ pub mod ld2d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld2d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -272,6 +512,30 @@ pub mod ld3d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld3d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -298,6 +562,30 @@ pub mod ld4d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld4d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_ss.rs index d288b50d..9fded660 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eld_ss.rs @@ -12,6 +12,30 @@ pub mod ld2b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld2b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld3b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld3b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld4b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld4b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ld2h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld2h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ld3h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld3h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ld4h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld4h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ld2w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld2w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ld3w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld3w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod ld4w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld4w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod ld2d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld2d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -272,6 +512,30 @@ pub mod ld3d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld3d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -298,6 +562,30 @@ pub mod ld4d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld4d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_si.rs index a84b2e98..0e9163ab 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_si.rs @@ -12,6 +12,30 @@ pub mod ld2q_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2q_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld2q_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod ld3q_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3q_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld3q_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod ld4q_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4q_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld4q_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_ss.rs index 07b151be..4824830e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_eldq_ss.rs @@ -12,6 +12,30 @@ pub mod ld2q_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld2q_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld2q_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld3q_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld3q_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld3q_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld4q_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld4q_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld4q_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_si.rs index 5e18ea63..8a98d321 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_si.rs @@ -12,6 +12,30 @@ pub mod ld1rqb_z_p_bi_u8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqb_z_p_bi_u8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1rqb_z_p_bi_u8( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod ld1rob_z_p_bi_u8 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rob_z_p_bi_u8"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1rob_z_p_bi_u8( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod ld1rqh_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqh_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1rqh_z_p_bi_u16( imm4: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod ld1roh_z_p_bi_u16 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1roh_z_p_bi_u16"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1roh_z_p_bi_u16( imm4: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod ld1rqw_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqw_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1rqw_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod ld1row_z_p_bi_u32 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1row_z_p_bi_u32"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1row_z_p_bi_u32( imm4: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod ld1rqd_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqd_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1rqd_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod ld1rod_z_p_bi_u64 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rod_z_p_bi_u64"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn ld1rod_z_p_bi_u64( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_ss.rs index b6d3eec0..91dcb5dc 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcld/sve_mem_ldqr_ss.rs @@ -12,6 +12,30 @@ pub mod ld1rqb_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqb_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1rqb_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod ld1rob_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rob_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1rob_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod ld1rqh_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqh_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1rqh_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod ld1roh_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1roh_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1roh_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod ld1rqw_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqw_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1rqw_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod ld1row_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1row_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1row_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod ld1rqd_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rqd_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1rqd_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod ld1rod_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ld1rod_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn ld1rod_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_cstnt_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_cstnt_ss.rs index 45a19387..89163058 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_cstnt_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_cstnt_ss.rs @@ -12,6 +12,30 @@ pub mod stnt1b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod stnt1h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod stnt1w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod stnt1d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_est_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_est_ss.rs index 576ac1b3..f231b23b 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_est_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memcst_nt/sve_mem_est_ss.rs @@ -12,6 +12,30 @@ pub mod st2b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st2b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod st3b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st3b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod st4b_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4b_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st4b_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod st2h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st2h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -116,6 +212,30 @@ pub mod st3h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st3h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -142,6 +262,30 @@ pub mod st4h_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4h_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st4h_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -168,6 +312,30 @@ pub mod st2w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st2w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -194,6 +362,30 @@ pub mod st3w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st3w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -220,6 +412,30 @@ pub mod st4w_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4w_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st4w_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -246,6 +462,30 @@ pub mod st2d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st2d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -272,6 +512,30 @@ pub mod st3d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st3d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -298,6 +562,30 @@ pub mod st4d_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4d_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st4d_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_32b_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_32b_vs.rs index a671a04b..78906bcc 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_32b_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_32b_vs.rs @@ -12,6 +12,30 @@ pub mod stnt1b_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1b_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod stnt1h_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1h_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod stnt1w_z_p_ar_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_z_p_ar_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1w_z_p_ar_s_x32_unscaled( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_64b_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_64b_vs.rs index aad7c20e..e7f985aa 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_64b_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstnt_64b_vs.rs @@ -12,6 +12,30 @@ pub mod stnt1b_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1b_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod stnt1h_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1h_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod stnt1w_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1w_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod stnt1d_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn stnt1d_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstq_64b_vs.rs b/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstq_64b_vs.rs index aed45863..d44aee10 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstq_64b_vs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memsst_nt/sve_mem_sstq_64b_vs.rs @@ -12,6 +12,30 @@ pub mod st1q_z_p_ar_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1q_z_p_ar_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1q_z_p_ar_d_64_unscaled( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_cst_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_cst_ss.rs index b26a92ea..58f0ed9e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_cst_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_cst_ss.rs @@ -12,6 +12,36 @@ pub mod st1b_z_p_br_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_z_p_br_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn st1b_z_p_br_( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +70,36 @@ pub mod st1h_z_p_br_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_br_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn st1h_z_p_br_( size: ::aarchmrs_types::BitValue<2>, @@ -68,6 +128,30 @@ pub mod st1w_z_p_br_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_br_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_br_u128( Rm: ::aarchmrs_types::BitValue<5>, @@ -94,6 +178,36 @@ pub mod st1w_z_p_br_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_br_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn st1w_z_p_br_( sz: ::aarchmrs_types::BitValue<1>, @@ -122,6 +236,30 @@ pub mod st1d_z_p_br_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_br_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_z_p_br_u128( Rm: ::aarchmrs_types::BitValue<5>, @@ -148,6 +286,30 @@ pub mod st1d_z_p_br_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_br_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_z_p_br_( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_si.rs index 6cf1ba1f..ce229ce5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_si.rs @@ -12,6 +12,30 @@ pub mod st2q_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2q_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st2q_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod st3q_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3q_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st3q_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod st4q_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4q_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st4q_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_ss.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_ss.rs index 052dff46..ee943be0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_ss.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_estq_ss.rs @@ -12,6 +12,30 @@ pub mod st2q_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2q_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st2q_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod st3q_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3q_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st3q_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod st4q_z_p_br_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4q_z_p_br_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; #[inline] pub const fn st4q_z_p_br_contiguous( Rm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_pspill.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_pspill.rs index a85cb9f1..b8be9f68 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_pspill.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_pspill.rs @@ -12,6 +12,30 @@ pub mod str_p_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "str_p_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_WIDTH: u32 = 6u32; #[inline] pub const fn str_p_bi_( imm9h: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_spill.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_spill.rs index 7af357f4..35e3aac5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_spill.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_cs/sve_mem_spill.rs @@ -12,6 +12,30 @@ pub mod str_z_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "str_z_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm9h_WIDTH: u32 = 6u32; #[inline] pub const fn str_z_bi_( imm9h: ::aarchmrs_types::BitValue<6>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cst_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cst_si.rs index fe12a99e..df85af60 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cst_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cst_si.rs @@ -12,6 +12,36 @@ pub mod st1b_z_p_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_z_p_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn st1b_z_p_bi_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod st1h_z_p_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn st1h_z_p_bi_( size: ::aarchmrs_types::BitValue<2>, @@ -70,6 +130,30 @@ pub mod st1w_z_p_bi_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bi_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1w_z_p_bi_u128( imm4: ::aarchmrs_types::BitValue<4>, @@ -96,6 +180,36 @@ pub mod st1w_z_p_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn st1w_z_p_bi_( sz: ::aarchmrs_types::BitValue<1>, @@ -125,6 +239,30 @@ pub mod st1d_z_p_bi_u128 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_bi_u128"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1d_z_p_bi_u128( imm4: ::aarchmrs_types::BitValue<4>, @@ -151,6 +289,30 @@ pub mod st1d_z_p_bi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_bi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st1d_z_p_bi_( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cstnt_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cstnt_si.rs index 27142006..311d97d0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cstnt_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_cstnt_si.rs @@ -12,6 +12,30 @@ pub mod stnt1b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod stnt1h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod stnt1w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod stnt1d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "stnt1d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn stnt1d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_est_si.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_est_si.rs index 74690c71..cd33d136 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_est_si.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_si/sve_mem_est_si.rs @@ -12,6 +12,30 @@ pub mod st2b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st2b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod st3b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st3b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod st4b_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4b_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st4b_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod st2h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st2h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod st3h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st3h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod st4h_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4h_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st4h_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod st2w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st2w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod st3w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st3w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -220,6 +412,30 @@ pub mod st4w_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4w_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st4w_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -246,6 +462,30 @@ pub mod st2d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st2d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st2d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -272,6 +512,30 @@ pub mod st3d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st3d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st3d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, @@ -298,6 +562,30 @@ pub mod st4d_z_p_bi_contiguous { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st4d_z_p_bi_contiguous"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn st4d_z_p_bi_contiguous( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_a.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_a.rs index 01523d7b..9ab0981e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_a.rs @@ -12,6 +12,36 @@ pub mod st1h_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_bz_d_x32_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod st1w_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_bz_d_x32_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -70,6 +130,36 @@ pub mod st1d_z_p_bz_d_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_bz_d_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_z_p_bz_d_x32_scaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_b.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_b.rs index 0403995f..3fbcf97e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_sv_b.rs @@ -12,6 +12,36 @@ pub mod st1h_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_bz_s_x32_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod st1w_z_p_bz_s_x32_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bz_s_x32_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_bz_s_x32_scaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_a.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_a.rs index 8afc403b..3b7f50c5 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_a.rs @@ -12,6 +12,36 @@ pub mod st1b_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_z_p_bz_d_x32_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod st1h_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_bz_d_x32_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -70,6 +130,36 @@ pub mod st1w_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_bz_d_x32_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -99,6 +189,36 @@ pub mod st1d_z_p_bz_d_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_bz_d_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_z_p_bz_d_x32_unscaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_b.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_b.rs index 3e30c974..91f65a40 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss/sve_mem_sst_vs_b.rs @@ -12,6 +12,36 @@ pub mod st1b_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_z_p_bz_s_x32_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -41,6 +71,36 @@ pub mod st1h_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_bz_s_x32_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -70,6 +130,36 @@ pub mod st1w_z_p_bz_s_x32_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bz_s_x32_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_xs_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_bz_s_x32_unscaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_sv2.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_sv2.rs index 431f5b63..879b098f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_sv2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_sv2.rs @@ -12,6 +12,30 @@ pub mod st1h_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod st1w_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod st1d_z_p_bz_d_64_scaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_bz_d_64_scaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_z_p_bz_d_64_scaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_a.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_a.rs index 65454331..427cccc9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_a.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_a.rs @@ -12,6 +12,30 @@ pub mod st1b_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod st1h_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod st1w_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod st1d_z_p_ai_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_ai_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_z_p_ai_d( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_b.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_b.rs index d760f4f0..f45d4987 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_b.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vi_b.rs @@ -12,6 +12,30 @@ pub mod st1b_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod st1h_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod st1w_z_p_ai_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_ai_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_ai_s( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vs2.rs b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vs2.rs index 751e9e28..0ec8d0f6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vs2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_memst_ss2/sve_mem_sst_vs2.rs @@ -12,6 +12,30 @@ pub mod st1b_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1b_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1b_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -38,6 +62,30 @@ pub mod st1h_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1h_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1h_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -64,6 +112,30 @@ pub mod st1w_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1w_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1w_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, @@ -90,6 +162,30 @@ pub mod st1d_z_p_bz_d_64_unscaled { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "st1d_z_p_bz_d_64_unscaled"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zt_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn st1d_z_p_bz_d_64_unscaled( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_int_perm_extract_i.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_int_perm_extract_i.rs index 15a2c56d..e7ac179b 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_int_perm_extract_i.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_int_perm_extract_i.rs @@ -12,6 +12,30 @@ pub mod ext_z_zi_des { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ext_z_zi_des"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8h_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8h_WIDTH: u32 = 5u32; #[inline] pub const fn ext_z_zi_des( imm8h: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_intx_perm_extract_i.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_intx_perm_extract_i.rs index 90665e49..f3c30dee 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_intx_perm_extract_i.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_extract/sve_intx_perm_extract_i.rs @@ -12,6 +12,30 @@ pub mod ext_z_zi_con { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ext_z_zi_con"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8l_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8l_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8h_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8h_WIDTH: u32 = 5u32; #[inline] pub const fn ext_z_zi_con( imm8h: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_inter/sve_int_perm_bin_perm_zz.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_inter/sve_int_perm_bin_perm_zz.rs index 0799e387..a4332ff0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_inter/sve_int_perm_bin_perm_zz.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_inter/sve_int_perm_bin_perm_zz.rs @@ -12,6 +12,30 @@ pub mod zip1_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip1_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zip1_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod uzp1_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp1_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzp1_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod trn1_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "trn1_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn trn1_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod zip2_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip2_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zip2_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod uzp2_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp2_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzp2_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -147,6 +267,30 @@ pub mod trn2_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "trn2_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn trn2_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_inter_long/sve_int_perm_bin_long_perm_zz.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_inter_long/sve_int_perm_bin_long_perm_zz.rs index db1a5a2c..8a151812 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_inter_long/sve_int_perm_bin_long_perm_zz.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_inter_long/sve_int_perm_bin_long_perm_zz.rs @@ -12,6 +12,24 @@ pub mod zip1_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip1_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn zip1_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod uzp1_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp1_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn uzp1_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, @@ -60,6 +96,24 @@ pub mod trn1_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "trn1_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn trn1_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, @@ -84,6 +138,24 @@ pub mod zip2_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip2_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn zip2_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, @@ -108,6 +180,24 @@ pub mod uzp2_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp2_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn uzp2_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, @@ -132,6 +222,24 @@ pub mod trn2_z_zz_q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "trn2_z_zz_q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn trn2_z_zz_q( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_rz.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_rz.rs index 72a8b273..6325b713 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_rz.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_rz.rs @@ -12,6 +12,30 @@ pub mod clasta_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clasta_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clasta_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod clastb_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clastb_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clastb_r_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_vz.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_vz.rs index c6dafbfc..6750303e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_vz.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_vz.rs @@ -12,6 +12,30 @@ pub mod clasta_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clasta_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clasta_v_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod clastb_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clastb_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clastb_v_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_zz.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_zz.rs index b11c737d..f2b8f0f9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_zz.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_clast_zz.rs @@ -12,6 +12,30 @@ pub mod clasta_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clasta_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clasta_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod clastb_z_p_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "clastb_z_p_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn clastb_z_p_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_compact.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_compact.rs index 0408bd9e..e9f05dbd 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_compact.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_compact.rs @@ -12,6 +12,30 @@ pub mod compact_z_p_z_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "compact_z_p_z_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn compact_z_p_z_s( sz: ::aarchmrs_types::BitValue<1>, @@ -38,6 +62,30 @@ pub mod compact_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "compact_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; #[inline] pub const fn compact_z_p_z_( sz: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_r.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_r.rs index 2cc40b62..d9a63563 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_r.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_r.rs @@ -12,6 +12,30 @@ pub mod cpy_z_p_r_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cpy_z_p_r_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cpy_z_p_r_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_v.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_v.rs index 5384e3be..1cae0c88 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_v.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_cpy_v.rs @@ -12,6 +12,30 @@ pub mod cpy_z_p_v_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cpy_z_p_v_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cpy_z_p_v_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_expand.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_expand.rs index 8b145233..199ef59d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_expand.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_expand.rs @@ -12,6 +12,30 @@ pub mod expand_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "expand_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn expand_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_r.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_r.rs index 13b123ff..7ba15d6a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_r.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_r.rs @@ -12,6 +12,30 @@ pub mod lasta_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lasta_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lasta_r_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod lastb_r_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lastb_r_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lastb_r_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_v.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_v.rs index ef8545d7..589f6cae 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_v.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_last_v.rs @@ -12,6 +12,30 @@ pub mod lasta_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lasta_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lasta_v_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod lastb_v_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lastb_v_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lastb_v_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_rev.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_rev.rs index 6830e113..2b0c67c1 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_rev.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_rev.rs @@ -12,6 +12,30 @@ pub mod revb_z_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revb_z_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn revb_z_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod revb_z_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revb_z_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn revb_z_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod revh_z_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revh_z_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn revh_z_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod revh_z_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revh_z_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn revh_z_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod revw_z_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revw_z_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn revw_z_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod revw_z_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revw_z_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn revw_z_z_z( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod rbit_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rbit_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn rbit_z_p_z_m( size: ::aarchmrs_types::BitValue<2>, @@ -194,6 +362,30 @@ pub mod rbit_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rbit_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn rbit_z_p_z_z( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_revd.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_revd.rs index 3baf200a..c12344f9 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_revd.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_revd.rs @@ -12,6 +12,24 @@ pub mod revd_z_p_z_m { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revd_z_p_z_m"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn revd_z_p_z_m( Pg: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod revd_z_p_z_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "revd_z_p_z_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 3u32; #[inline] pub const fn revd_z_p_z_z( Pg: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_splice.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_splice.rs index 36ba70b2..e9dc2497 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_splice.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_int_perm_splice.rs @@ -12,6 +12,30 @@ pub mod splice_z_p_zz_des { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "splice_z_p_zz_des"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn splice_z_p_zz_des( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_intx_perm_splice.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_intx_perm_splice.rs index ce6f37c2..6a0f5100 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_intx_perm_splice.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_pred/sve_intx_perm_splice.rs @@ -12,6 +12,30 @@ pub mod splice_z_p_zz_con { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "splice_z_p_zz_con"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn splice_z_p_zz_con( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_bin_perm_pp.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_bin_perm_pp.rs index 4255b325..acb4a11f 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_bin_perm_pp.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_bin_perm_pp.rs @@ -12,6 +12,30 @@ pub mod zip1_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip1_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zip1_p_pp_( size: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod uzp1_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp1_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzp1_p_pp_( size: ::aarchmrs_types::BitValue<2>, @@ -68,6 +116,30 @@ pub mod trn1_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "trn1_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn trn1_p_pp_( size: ::aarchmrs_types::BitValue<2>, @@ -96,6 +168,30 @@ pub mod zip2_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zip2_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zip2_p_pp_( size: ::aarchmrs_types::BitValue<2>, @@ -124,6 +220,30 @@ pub mod uzp2_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzp2_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzp2_p_pp_( size: ::aarchmrs_types::BitValue<2>, @@ -152,6 +272,30 @@ pub mod trn2_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "trn2_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn trn2_p_pp_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_punpk.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_punpk.rs index d2bef30a..8c27a795 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_punpk.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_punpk.rs @@ -12,6 +12,18 @@ pub mod punpklo_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "punpklo_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; #[inline] pub const fn punpklo_p_p_( Pn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod punpkhi_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "punpkhi_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; #[inline] pub const fn punpkhi_p_p_( Pn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_reverse_p.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_reverse_p.rs index b630985f..2b64d244 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_reverse_p.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_predicates/sve_int_perm_reverse_p.rs @@ -12,6 +12,24 @@ pub mod rev_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rev_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn rev_p_p_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_dupq_i.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_dupq_i.rs index 3c31edd9..b3adcb8c 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_dupq_i.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_dupq_i.rs @@ -12,6 +12,30 @@ pub mod dupq_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "dupq_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsz_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsz_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn dupq_z_zi_( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_extq.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_extq.rs index 8b54a953..93c3f4a7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_extq.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_a/sve_int_perm_extq.rs @@ -12,6 +12,24 @@ pub mod extq_z_zi_des { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "extq_z_zi_des"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn extq_z_zi_des( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_b/sve_int_perm_binquads.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_b/sve_int_perm_binquads.rs index aee8cd61..d8233821 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_b/sve_int_perm_binquads.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_b/sve_int_perm_binquads.rs @@ -12,6 +12,30 @@ pub mod zipq1_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zipq1_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zipq1_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod uzpq1_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzpq1_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzpq1_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod tblq_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "tblq_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn tblq_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -93,6 +165,30 @@ pub mod zipq2_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "zipq2_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn zipq2_z_zz_( size: ::aarchmrs_types::BitValue<2>, @@ -120,6 +216,30 @@ pub mod uzpq2_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uzpq2_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uzpq2_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_c/sve_int_perm_tbxquads.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_c/sve_int_perm_tbxquads.rs index 10db1393..cffbeaa3 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_quads_c/sve_int_perm_tbxquads.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_quads_c/sve_int_perm_tbxquads.rs @@ -12,6 +12,30 @@ pub mod tbxq_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "tbxq_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn tbxq_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_a/sve_int_perm_dup_i.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_a/sve_int_perm_dup_i.rs index 993d967f..404348d8 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_a/sve_int_perm_dup_i.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_a/sve_int_perm_dup_i.rs @@ -12,6 +12,30 @@ pub mod dup_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "dup_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsz_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tsz_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; #[inline] pub const fn dup_z_zi_( imm2: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_b/sve_int_perm_tbl_3src.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_b/sve_int_perm_tbl_3src.rs index 97a66307..57bb5ca8 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_b/sve_int_perm_tbl_3src.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_b/sve_int_perm_tbl_3src.rs @@ -12,6 +12,30 @@ pub mod tbl_z_zz_2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "tbl_z_zz_2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn tbl_z_zz_2( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod tbx_z_zz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "tbx_z_zz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn tbx_z_zz_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_c/sve_int_perm_tbl.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_c/sve_int_perm_tbl.rs index ac0158dc..b431dc18 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_c/sve_int_perm_tbl.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_c/sve_int_perm_tbl.rs @@ -12,6 +12,30 @@ pub mod tbl_z_zz_1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "tbl_z_zz_1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn tbl_z_zz_1( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_p2v.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_p2v.rs index 64c42841..f8425ddc 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_p2v.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_p2v.rs @@ -12,6 +12,18 @@ pub mod pmov_z_pi_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_z_pi_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; #[inline] pub const fn pmov_z_pi_b( Pn: ::aarchmrs_types::BitValue<4>, @@ -33,6 +45,24 @@ pub mod pmov_z_pi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_z_pi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn pmov_z_pi_h( i1: ::aarchmrs_types::BitValue<1>, @@ -57,6 +87,24 @@ pub mod pmov_z_pi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_z_pi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn pmov_z_pi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -81,6 +129,30 @@ pub mod pmov_z_pi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_z_pi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn pmov_z_pi_d( i3h: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_v2p.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_v2p.rs index 59dc14eb..b415b3ef 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_v2p.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_mov_v2p.rs @@ -12,6 +12,18 @@ pub mod pmov_p_zi_b { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_p_zi_b"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; #[inline] pub const fn pmov_p_zi_b( Zn: ::aarchmrs_types::BitValue<5>, @@ -34,6 +46,24 @@ pub mod pmov_p_zi_h { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_p_zi_h"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn pmov_p_zi_h( i1: ::aarchmrs_types::BitValue<1>, @@ -59,6 +89,24 @@ pub mod pmov_p_zi_s { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_p_zi_s"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i2_WIDTH: u32 = 2u32; #[inline] pub const fn pmov_p_zi_s( i2: ::aarchmrs_types::BitValue<2>, @@ -84,6 +132,30 @@ pub mod pmov_p_zi_d { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pmov_p_zi_d"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_OFFSET: u32 = 17u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3l_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i3h_WIDTH: u32 = 1u32; #[inline] pub const fn pmov_p_zi_d( i3h: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_dup_r.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_dup_r.rs index 5decd701..365556e7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_dup_r.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_dup_r.rs @@ -12,6 +12,24 @@ pub mod dup_z_r_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "dup_z_r_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn dup_z_r_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrs.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrs.rs index 93bab28b..7d563597 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrs.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrs.rs @@ -12,6 +12,24 @@ pub mod insr_z_r_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "insr_z_r_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn insr_z_r_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrv.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrv.rs index afcbd7c6..b85bf9b0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrv.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_insrv.rs @@ -12,6 +12,24 @@ pub mod insr_z_v_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "insr_z_v_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn insr_z_v_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_reverse_z.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_reverse_z.rs index 2c802d29..8de341a2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_reverse_z.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_reverse_z.rs @@ -12,6 +12,24 @@ pub mod rev_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rev_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn rev_z_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_unpk.rs b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_unpk.rs index 397d84a2..a1df52d2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_unpk.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_perm_unpred_d/sve_int_perm_unpk.rs @@ -12,6 +12,24 @@ pub mod sunpklo_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sunpklo_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sunpklo_z_z_( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod sunpkhi_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sunpkhi_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sunpkhi_z_z_( size: ::aarchmrs_types::BitValue<2>, @@ -60,6 +96,24 @@ pub mod uunpklo_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uunpklo_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uunpklo_z_z_( size: ::aarchmrs_types::BitValue<2>, @@ -84,6 +138,24 @@ pub mod uunpkhi_z_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uunpkhi_z_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uunpkhi_z_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pn.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pn.rs index 73050da1..3bcb32a7 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pn.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pn.rs @@ -12,6 +12,30 @@ pub mod cntp_r_pn_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cntp_r_pn_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cntp_r_pn_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pred.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pred.rs index 3dbd3291..ec79eee0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pred.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_count_a/sve_int_pcount_pred.rs @@ -12,6 +12,30 @@ pub mod cntp_r_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cntp_r_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cntp_r_p_p_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod firstp_r_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "firstp_r_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn firstp_r_p_p_( size: ::aarchmrs_types::BitValue<2>, @@ -66,6 +114,30 @@ pub mod lastp_r_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "lastp_r_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn lastp_r_p_p_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r.rs index a7f0a211..e7204aa2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r.rs @@ -12,6 +12,24 @@ pub mod incp_r_p_r_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "incp_r_p_r_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn incp_r_p_r_( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod decp_r_p_r_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "decp_r_p_r_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn decp_r_p_r_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r_sat.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r_sat.rs index b6e4af77..74e8ce07 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r_sat.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_r_sat.rs @@ -12,6 +12,24 @@ pub mod sqincp_r_p_r_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincp_r_p_r_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqincp_r_p_r_sx( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod uqincp_r_p_r_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincp_r_p_r_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqincp_r_p_r_uw( size: ::aarchmrs_types::BitValue<2>, @@ -60,6 +96,24 @@ pub mod sqdecp_r_p_r_sx { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecp_r_p_r_sx"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdecp_r_p_r_sx( size: ::aarchmrs_types::BitValue<2>, @@ -84,6 +138,24 @@ pub mod uqdecp_r_p_r_uw { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecp_r_p_r_uw"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqdecp_r_p_r_uw( size: ::aarchmrs_types::BitValue<2>, @@ -108,6 +180,24 @@ pub mod sqincp_r_p_r_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincp_r_p_r_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqincp_r_p_r_x( size: ::aarchmrs_types::BitValue<2>, @@ -132,6 +222,24 @@ pub mod sqdecp_r_p_r_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecp_r_p_r_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdecp_r_p_r_x( size: ::aarchmrs_types::BitValue<2>, @@ -156,6 +264,24 @@ pub mod uqincp_r_p_r_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincp_r_p_r_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqincp_r_p_r_x( size: ::aarchmrs_types::BitValue<2>, @@ -180,6 +306,24 @@ pub mod uqdecp_r_p_r_x { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecp_r_p_r_x"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqdecp_r_p_r_x( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v.rs index 4ef8f6fa..b9cc871d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v.rs @@ -12,6 +12,24 @@ pub mod incp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "incp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn incp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod decp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "decp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn decp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v_sat.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v_sat.rs index 56df3f05..b1ed9c5a 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v_sat.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_count_b/sve_int_count_v_sat.rs @@ -12,6 +12,24 @@ pub mod sqincp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqincp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqincp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod sqdecp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqdecp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqdecp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -60,6 +96,24 @@ pub mod uqincp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqincp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqincp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, @@ -84,6 +138,24 @@ pub mod uqdecp_z_p_z_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqdecp_z_p_z_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqdecp_z_p_z_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_dup/sve_int_pred_dup.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_dup/sve_int_pred_dup.rs index cf6647c0..3fc80db6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_dup/sve_int_pred_dup.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_dup/sve_int_pred_dup.rs @@ -12,6 +12,48 @@ pub mod psel_p_ppi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "psel_p_ppi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rv_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszl_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_tszh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; #[inline] pub const fn psel_p_ppi_( i1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_a/sve_int_pred_log.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_a/sve_int_pred_log.rs index e7db0eab..e2e3b0f6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_a/sve_int_pred_log.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_a/sve_int_pred_log.rs @@ -12,6 +12,30 @@ pub mod and_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "and_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn and_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod bic_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bic_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn bic_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod orr_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orr_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn orr_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod orn_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orn_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn orn_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -124,6 +220,30 @@ pub mod eor_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eor_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn eor_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -152,6 +272,30 @@ pub mod sel_p_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sel_p_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn sel_p_p_pp_( Pm: ::aarchmrs_types::BitValue<4>, @@ -180,6 +324,30 @@ pub mod nor_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "nor_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn nor_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -208,6 +376,30 @@ pub mod nand_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "nand_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn nand_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -236,6 +428,30 @@ pub mod ands_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ands_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn ands_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -264,6 +480,30 @@ pub mod bics_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "bics_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn bics_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -292,6 +532,30 @@ pub mod orrs_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orrs_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn orrs_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -320,6 +584,30 @@ pub mod orns_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "orns_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn orns_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -348,6 +636,30 @@ pub mod eors_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "eors_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn eors_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -376,6 +688,30 @@ pub mod nors_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "nors_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn nors_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, @@ -404,6 +740,30 @@ pub mod nands_p_p_pp_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "nands_p_p_pp_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn nands_p_p_pp_z( Pm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_b/sve_int_brkp.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_b/sve_int_brkp.rs index 0be53bfc..5e78b28e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_b/sve_int_brkp.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_b/sve_int_brkp.rs @@ -12,6 +12,30 @@ pub mod brkpa_p_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkpa_p_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn brkpa_p_p_pp_( Pm: ::aarchmrs_types::BitValue<4>, @@ -40,6 +64,30 @@ pub mod brkpas_p_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkpas_p_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn brkpas_p_p_pp_( Pm: ::aarchmrs_types::BitValue<4>, @@ -68,6 +116,30 @@ pub mod brkpb_p_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkpb_p_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn brkpb_p_p_pp_( Pm: ::aarchmrs_types::BitValue<4>, @@ -96,6 +168,30 @@ pub mod brkpbs_p_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkpbs_p_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pm_WIDTH: u32 = 4u32; #[inline] pub const fn brkpbs_p_p_pp_( Pm: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_break.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_break.rs index 89bc3c55..8bedafe6 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_break.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_break.rs @@ -12,6 +12,30 @@ pub mod brka_p_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brka_p_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn brka_p_p_p_( Pg: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,24 @@ pub mod brkas_p_p_p_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkas_p_p_p_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn brkas_p_p_p_z( Pg: ::aarchmrs_types::BitValue<4>, @@ -63,6 +105,30 @@ pub mod brkb_p_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkb_p_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn brkb_p_p_p_( Pg: ::aarchmrs_types::BitValue<4>, @@ -89,6 +155,24 @@ pub mod brkbs_p_p_p_z { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkbs_p_p_p_z"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn brkbs_p_p_p_z( Pg: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_brkn.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_brkn.rs index 8921318b..d2fe52ac 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_brkn.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_c/sve_int_brkn.rs @@ -12,6 +12,24 @@ pub mod brkn_p_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkn_p_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn brkn_p_p_pp_( Pg: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,24 @@ pub mod brkns_p_p_pp_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "brkns_p_p_pp_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn brkns_p_p_pp_( Pg: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfalse.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfalse.rs index f917cb88..5383ed6e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfalse.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfalse.rs @@ -12,6 +12,12 @@ pub mod pfalse_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pfalse_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; #[inline] pub const fn pfalse_p_(Pd: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfirst.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfirst.rs index b7284960..ca2a13a4 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfirst.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pfirst.rs @@ -12,6 +12,18 @@ pub mod pfirst_p_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pfirst_p_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn pfirst_p_p_p_( Pg: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pnext.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pnext.rs index 99d2c01c..eeb83a71 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pnext.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_pnext.rs @@ -12,6 +12,24 @@ pub mod pnext_p_p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pnext_p_p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pdn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pv_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn pnext_p_p_p_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptest.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptest.rs index 06e2fd56..5f292fd4 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptest.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptest.rs @@ -12,6 +12,18 @@ pub mod ptest__p_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ptest__p_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn ptest__p_p_( Pg: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptrue.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptrue.rs index fe6c8a33..a92a9ab4 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptrue.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_ptrue.rs @@ -12,6 +12,24 @@ pub mod ptrue_p_s_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ptrue_p_s_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ptrue_p_s_( size: ::aarchmrs_types::BitValue<2>, @@ -37,6 +55,24 @@ pub mod ptrues_p_s_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ptrues_p_s_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_pattern_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ptrues_p_s_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr.rs index 4b48076f..fbcac76e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr.rs @@ -12,6 +12,18 @@ pub mod rdffr_p_p_f_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rdffr_p_p_f_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn rdffr_p_p_f_( Pg: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod rdffrs_p_p_f_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rdffrs_p_p_f_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; #[inline] pub const fn rdffrs_p_p_f_( Pg: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr_2.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr_2.rs index b279ec0b..9672b704 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr_2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_gen_d/sve_int_rdffr_2.rs @@ -12,6 +12,12 @@ pub mod rdffr_p_f_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "rdffr_p_f_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; #[inline] pub const fn rdffr_p_f_( Pd: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_pred_wrffr/sve_int_wrffr.rs b/aarchmrs-instructions/src/A64/sve/sve_pred_wrffr/sve_int_wrffr.rs index 1b0eefc8..ab3b4fdb 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_pred_wrffr/sve_int_wrffr.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_pred_wrffr/sve_int_wrffr.rs @@ -12,6 +12,12 @@ pub mod wrffr_f_p_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "wrffr_f_p_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pn_WIDTH: u32 = 4u32; #[inline] pub const fn wrffr_f_p_( Pn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_ptr_muladd_unpred/sve_ptr_muladd_unpred.rs b/aarchmrs-instructions/src/A64/sve/sve_ptr_muladd_unpred/sve_ptr_muladd_unpred.rs index 5d42a353..26e0366e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_ptr_muladd_unpred/sve_ptr_muladd_unpred.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_ptr_muladd_unpred/sve_ptr_muladd_unpred.rs @@ -12,6 +12,24 @@ pub mod mlapt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mlapt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zda_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn mlapt_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, @@ -36,6 +54,24 @@ pub mod madpt_z_zzz_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "madpt_z_zzz_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Za_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zm_WIDTH: u32 = 5u32; #[inline] pub const fn madpt_z_zzz_( Zm: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_ctr_to_mask.rs b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_ctr_to_mask.rs index 4732a30e..13f06dc2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_ctr_to_mask.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_ctr_to_mask.rs @@ -12,6 +12,30 @@ pub mod pext_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pext_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn pext_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -39,6 +63,30 @@ pub mod pext_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "pext_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn pext_pp_rr_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_pn_ptrue.rs b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_pn_ptrue.rs index a86b6f30..77428750 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_pn_ptrue.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_pn_ptrue.rs @@ -12,6 +12,18 @@ pub mod ptrue_pn_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ptrue_pn_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn ptrue_pn_i_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pair.rs b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pair.rs index 16f6c07a..ffc26a5d 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pair.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pair.rs @@ -12,6 +12,30 @@ pub mod whilege_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilege_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilege_pp_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +65,30 @@ pub mod whilehs_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilehs_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilehs_pp_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -70,6 +118,30 @@ pub mod whilegt_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilegt_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilegt_pp_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -99,6 +171,30 @@ pub mod whilehi_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilehi_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilehi_pp_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -128,6 +224,30 @@ pub mod whilelt_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilelt_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilelt_pp_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -157,6 +277,30 @@ pub mod whilelo_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilelo_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilelo_pp_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -186,6 +330,30 @@ pub mod whilele_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilele_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilele_pp_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -215,6 +383,30 @@ pub mod whilels_pp_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilels_pp_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilels_pp_rr_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pn.rs b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pn.rs index 76fa9a2f..9e570145 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pn.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_while_pn/sve_int_while_rr_pn.rs @@ -12,6 +12,36 @@ pub mod whilege_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilege_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilege_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -43,6 +73,36 @@ pub mod whilehs_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilehs_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilehs_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -74,6 +134,36 @@ pub mod whilegt_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilegt_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilegt_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -105,6 +195,36 @@ pub mod whilehi_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilehi_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilehi_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -136,6 +256,36 @@ pub mod whilelt_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilelt_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilelt_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -167,6 +317,36 @@ pub mod whilelo_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilelo_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilelo_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -198,6 +378,36 @@ pub mod whilele_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilele_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilele_pn_rr_( size: ::aarchmrs_types::BitValue<2>, @@ -229,6 +439,36 @@ pub mod whilels_pn_rr_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "whilels_pn_rr_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_PNd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_vl_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn whilels_pn_rr_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_fpimm_pred.rs b/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_fpimm_pred.rs index bd3f5168..42ecdff8 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_fpimm_pred.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_fpimm_pred.rs @@ -12,6 +12,30 @@ pub mod fcpy_z_p_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fcpy_z_p_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fcpy_z_p_i_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_imm_pred.rs b/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_imm_pred.rs index ae2f2441..5e1424b0 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_imm_pred.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_wideimm_pred/sve_int_dup_imm_pred.rs @@ -12,6 +12,36 @@ pub mod cpy_z_o_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cpy_z_o_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cpy_z_o_i_( size: ::aarchmrs_types::BitValue<2>, @@ -41,6 +71,36 @@ pub mod cpy_z_p_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "cpy_z_p_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Pg_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn cpy_z_p_i_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm0.rs b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm0.rs index aeff718b..9e630163 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm0.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm0.rs @@ -12,6 +12,30 @@ pub mod add_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "add_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn add_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -38,6 +62,30 @@ pub mod sub_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sub_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sub_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -64,6 +112,30 @@ pub mod subr_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "subr_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn subr_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -90,6 +162,30 @@ pub mod sqadd_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqadd_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqadd_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -116,6 +212,30 @@ pub mod sqsub_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "sqsub_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn sqsub_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -142,6 +262,30 @@ pub mod uqadd_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqadd_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqadd_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -168,6 +312,30 @@ pub mod uqsub_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "uqsub_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn uqsub_z_zi_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm1.rs b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm1.rs index 98becb92..72385337 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm1.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm1.rs @@ -12,6 +12,24 @@ pub mod smax_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smax_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smax_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -36,6 +54,24 @@ pub mod smin_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "smin_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn smin_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -60,6 +96,24 @@ pub mod umax_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umax_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umax_z_zi_( size: ::aarchmrs_types::BitValue<2>, @@ -84,6 +138,24 @@ pub mod umin_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "umin_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn umin_z_zi_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm2.rs b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm2.rs index bc38b0c5..d0bac8c2 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm2.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_arith_imm2.rs @@ -12,6 +12,24 @@ pub mod mul_z_zi_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "mul_z_zi_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zdn_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn mul_z_zi_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_fpimm.rs b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_fpimm.rs index 02d2c498..850ee95e 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_fpimm.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_fpimm.rs @@ -12,6 +12,24 @@ pub mod fdup_z_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "fdup_z_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn fdup_z_i_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_imm.rs b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_imm.rs index dc6f09cc..616160ae 100644 --- a/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_imm.rs +++ b/aarchmrs-instructions/src/A64/sve/sve_wideimm_unpred/sve_int_dup_imm.rs @@ -12,6 +12,30 @@ pub mod dup_z_i_ { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "dup_z_i_"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Zd_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sh_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; #[inline] pub const fn dup_z_i_( size: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/T32/b16.rs b/aarchmrs-instructions/src/T32/b16.rs index 24d734e3..9151cf1a 100644 --- a/aarchmrs-instructions/src/T32/b16.rs +++ b/aarchmrs-instructions/src/T32/b16.rs @@ -12,6 +12,12 @@ pub mod B_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "B_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_WIDTH: u32 = 11u32; #[inline] pub const fn B_T2(imm11: ::aarchmrs_types::BitValue<11>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/T32/n/addpcsp16.rs b/aarchmrs-instructions/src/T32/n/addpcsp16.rs index 378bd90c..eaa79487 100644 --- a/aarchmrs-instructions/src/T32/n/addpcsp16.rs +++ b/aarchmrs-instructions/src/T32/n/addpcsp16.rs @@ -12,6 +12,18 @@ pub mod ADR_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADR_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; #[inline] pub const fn ADR_T1( Rd: ::aarchmrs_types::BitValue<3>, @@ -31,6 +43,18 @@ pub mod ADD_SP_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; #[inline] pub const fn ADD_SP_i_T1( Rd: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/brc/bcond16.rs b/aarchmrs-instructions/src/T32/n/brc/bcond16.rs index b14f42c2..19147eeb 100644 --- a/aarchmrs-instructions/src/T32/n/brc/bcond16.rs +++ b/aarchmrs-instructions/src/T32/n/brc/bcond16.rs @@ -12,6 +12,18 @@ pub mod B_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "B_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; #[inline] pub const fn B_T1( cond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/n/brc/except16.rs b/aarchmrs-instructions/src/T32/n/brc/except16.rs index b4d398dc..4a7170b9 100644 --- a/aarchmrs-instructions/src/T32/n/brc/except16.rs +++ b/aarchmrs-instructions/src/T32/n/brc/except16.rs @@ -12,6 +12,12 @@ pub mod UDF_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDF_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn UDF_T1(imm8: ::aarchmrs_types::BitValue<8>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -28,6 +34,12 @@ pub mod SVC_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SVC_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn SVC_T1(imm8: ::aarchmrs_types::BitValue<8>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/T32/n/dpint16_2l.rs b/aarchmrs-instructions/src/T32/n/dpint16_2l.rs index 212f8563..7b56ea8b 100644 --- a/aarchmrs-instructions/src/T32/n/dpint16_2l.rs +++ b/aarchmrs-instructions/src/T32/n/dpint16_2l.rs @@ -12,6 +12,18 @@ pub mod AND_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn AND_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -31,6 +43,18 @@ pub mod EOR_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn EOR_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -50,6 +74,18 @@ pub mod MOV_rr_T1_ASR { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_rr_T1_ASR"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 3u32; #[inline] pub const fn MOV_rr_T1_ASR( Rs: ::aarchmrs_types::BitValue<3>, @@ -69,6 +105,18 @@ pub mod MOV_rr_T1_LSL { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_rr_T1_LSL"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 3u32; #[inline] pub const fn MOV_rr_T1_LSL( Rs: ::aarchmrs_types::BitValue<3>, @@ -88,6 +136,18 @@ pub mod MOV_rr_T1_LSR { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_rr_T1_LSR"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 3u32; #[inline] pub const fn MOV_rr_T1_LSR( Rs: ::aarchmrs_types::BitValue<3>, @@ -107,6 +167,18 @@ pub mod MOV_rr_T1_ROR { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_rr_T1_ROR"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 3u32; #[inline] pub const fn MOV_rr_T1_ROR( Rs: ::aarchmrs_types::BitValue<3>, @@ -126,6 +198,18 @@ pub mod ADC_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn ADC_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -145,6 +229,18 @@ pub mod SBC_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn SBC_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -164,6 +260,18 @@ pub mod TST_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn TST_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -183,6 +291,18 @@ pub mod RSB_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; #[inline] pub const fn RSB_i_T1( Rn: ::aarchmrs_types::BitValue<3>, @@ -202,6 +322,18 @@ pub mod CMP_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn CMP_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -221,6 +353,18 @@ pub mod CMN_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn CMN_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -240,6 +384,18 @@ pub mod ORR_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn ORR_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -259,6 +415,18 @@ pub mod MUL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MUL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; #[inline] pub const fn MUL_T1( Rn: ::aarchmrs_types::BitValue<3>, @@ -278,6 +446,18 @@ pub mod BIC_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn BIC_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -297,6 +477,18 @@ pub mod MVN_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn MVN_r_T1( Rm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/ldlit16.rs b/aarchmrs-instructions/src/T32/n/ldlit16.rs index 3149decc..56d7b02f 100644 --- a/aarchmrs-instructions/src/T32/n/ldlit16.rs +++ b/aarchmrs-instructions/src/T32/n/ldlit16.rs @@ -12,6 +12,18 @@ pub mod LDR_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; #[inline] pub const fn LDR_l_T1( Rt: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/ldst16_imm.rs b/aarchmrs-instructions/src/T32/n/ldst16_imm.rs index 7c59e833..0298b4d6 100644 --- a/aarchmrs-instructions/src/T32/n/ldst16_imm.rs +++ b/aarchmrs-instructions/src/T32/n/ldst16_imm.rs @@ -12,6 +12,24 @@ pub mod STR_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn STR_i_T1( imm5: ::aarchmrs_types::BitValue<5>, @@ -35,6 +53,24 @@ pub mod LDR_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn LDR_i_T1( imm5: ::aarchmrs_types::BitValue<5>, @@ -58,6 +94,24 @@ pub mod STRB_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn STRB_i_T1( imm5: ::aarchmrs_types::BitValue<5>, @@ -81,6 +135,24 @@ pub mod LDRB_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn LDRB_i_T1( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/T32/n/ldst16_reg.rs b/aarchmrs-instructions/src/T32/n/ldst16_reg.rs index a0c47347..05f43ceb 100644 --- a/aarchmrs-instructions/src/T32/n/ldst16_reg.rs +++ b/aarchmrs-instructions/src/T32/n/ldst16_reg.rs @@ -12,6 +12,24 @@ pub mod STR_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn STR_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod STRH_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn STRH_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -58,6 +94,24 @@ pub mod STRB_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn STRB_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -81,6 +135,24 @@ pub mod LDRSB_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn LDRSB_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -104,6 +176,24 @@ pub mod LDR_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn LDR_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -127,6 +217,24 @@ pub mod LDRH_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn LDRH_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -150,6 +258,24 @@ pub mod LDRB_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn LDRB_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -173,6 +299,24 @@ pub mod LDRSH_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn LDRSH_r_T1( Rm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/ldst16_sp.rs b/aarchmrs-instructions/src/T32/n/ldst16_sp.rs index 01a6cf49..83feb918 100644 --- a/aarchmrs-instructions/src/T32/n/ldst16_sp.rs +++ b/aarchmrs-instructions/src/T32/n/ldst16_sp.rs @@ -12,6 +12,18 @@ pub mod STR_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; #[inline] pub const fn STR_i_T2( Rt: ::aarchmrs_types::BitValue<3>, @@ -31,6 +43,18 @@ pub mod LDR_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; #[inline] pub const fn LDR_i_T2( Rt: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/ldsth16_imm.rs b/aarchmrs-instructions/src/T32/n/ldsth16_imm.rs index e715684c..befc688e 100644 --- a/aarchmrs-instructions/src/T32/n/ldsth16_imm.rs +++ b/aarchmrs-instructions/src/T32/n/ldsth16_imm.rs @@ -12,6 +12,24 @@ pub mod STRH_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn STRH_i_T1( imm5: ::aarchmrs_types::BitValue<5>, @@ -35,6 +53,24 @@ pub mod LDRH_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; #[inline] pub const fn LDRH_i_T1( imm5: ::aarchmrs_types::BitValue<5>, diff --git a/aarchmrs-instructions/src/T32/n/ldstm16.rs b/aarchmrs-instructions/src/T32/n/ldstm16.rs index 052cd355..2f88c8cf 100644 --- a/aarchmrs-instructions/src/T32/n/ldstm16.rs +++ b/aarchmrs-instructions/src/T32/n/ldstm16.rs @@ -12,6 +12,18 @@ pub mod STM_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STM_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; #[inline] pub const fn STM_T1( Rn: ::aarchmrs_types::BitValue<3>, @@ -31,6 +43,18 @@ pub mod LDM_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDM_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; #[inline] pub const fn LDM_T1( Rn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/adjsp16.rs b/aarchmrs-instructions/src/T32/n/misc16/adjsp16.rs index c380ea0f..9fa629a3 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/adjsp16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/adjsp16.rs @@ -12,6 +12,12 @@ pub mod ADD_SP_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn ADD_SP_i_T2( imm7: ::aarchmrs_types::BitValue<7>, @@ -30,6 +36,12 @@ pub mod SUB_SP_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm7_WIDTH: u32 = 7u32; #[inline] pub const fn SUB_SP_i_T1( imm7: ::aarchmrs_types::BitValue<7>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/bkpt16.rs b/aarchmrs-instructions/src/T32/n/misc16/bkpt16.rs index 333029e5..7ae18a4b 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/bkpt16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/bkpt16.rs @@ -12,6 +12,12 @@ pub mod BKPT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BKPT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; #[inline] pub const fn BKPT_T1(imm8: ::aarchmrs_types::BitValue<8>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/T32/n/misc16/cbznz16.rs b/aarchmrs-instructions/src/T32/n/misc16/cbznz16.rs index d194cc5f..298dc6d5 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/cbznz16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/cbznz16.rs @@ -12,6 +12,24 @@ pub mod CBNZ_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBNZ_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn CBNZ_T1( i: ::aarchmrs_types::BitValue<1>, @@ -36,6 +54,24 @@ pub mod CBZ_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CBZ_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn CBZ_T1( i: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/cps16.rs b/aarchmrs-instructions/src/T32/n/misc16/cps16.rs index 254b4077..21d5a6a4 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/cps16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/cps16.rs @@ -12,6 +12,12 @@ pub mod SETEND_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000010111u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETEND_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_WIDTH: u32 = 1u32; #[inline] pub const fn SETEND_T1(E: ::aarchmrs_types::BitValue<1>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -28,6 +34,24 @@ pub mod CPSID_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSID_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSID_T1_AS( A: ::aarchmrs_types::BitValue<1>, @@ -51,6 +75,24 @@ pub mod CPSIE_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSIE_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSIE_T1_AS( A: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/ext16.rs b/aarchmrs-instructions/src/T32/n/misc16/ext16.rs index cf864e7f..da6a934c 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/ext16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/ext16.rs @@ -12,6 +12,18 @@ pub mod SXTH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn SXTH_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -31,6 +43,18 @@ pub mod SXTB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn SXTB_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -50,6 +74,18 @@ pub mod UXTH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn UXTH_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -69,6 +105,18 @@ pub mod UXTB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn UXTB_T1( Rm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/hlt16.rs b/aarchmrs-instructions/src/T32/n/misc16/hlt16.rs index 544e97fc..45ebcd9d 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/hlt16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/hlt16.rs @@ -12,6 +12,12 @@ pub mod HLT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "HLT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; #[inline] pub const fn HLT_T1(imm6: ::aarchmrs_types::BitValue<6>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/T32/n/misc16/it16.rs b/aarchmrs-instructions/src/T32/n/misc16/it16.rs index 62f06ce1..c22b10a9 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/it16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/it16.rs @@ -12,6 +12,18 @@ pub mod IT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "IT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_firstcond_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_firstcond_WIDTH: u32 = 4u32; #[inline] pub const fn IT_T1( firstcond: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/pushpop16.rs b/aarchmrs-instructions/src/T32/n/misc16/pushpop16.rs index 52078005..24ba85b7 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/pushpop16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/pushpop16.rs @@ -12,6 +12,18 @@ pub mod PUSH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PUSH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; #[inline] pub const fn PUSH_T1( M: ::aarchmrs_types::BitValue<1>, @@ -31,6 +43,18 @@ pub mod POP_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "POP_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; #[inline] pub const fn POP_T1( P: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/rev16.rs b/aarchmrs-instructions/src/T32/n/misc16/rev16.rs index cd0bd652..f70f50f2 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/rev16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/rev16.rs @@ -12,6 +12,18 @@ pub mod REV_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn REV_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -31,6 +43,18 @@ pub mod REV16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn REV16_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -50,6 +74,18 @@ pub mod REVSH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REVSH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn REVSH_T1( Rm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/misc16/setpan16.rs b/aarchmrs-instructions/src/T32/n/misc16/setpan16.rs index ee801f4a..2a13634d 100644 --- a/aarchmrs-instructions/src/T32/n/misc16/setpan16.rs +++ b/aarchmrs-instructions/src/T32/n/misc16/setpan16.rs @@ -12,6 +12,12 @@ pub mod SETPAN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000010111u32; #[cfg(feature = "meta")] pub const NAME: &str = "SETPAN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm1_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm1_WIDTH: u32 = 1u32; #[inline] pub const fn SETPAN_T1( imm1: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_1l_imm.rs b/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_1l_imm.rs index 46f867cc..9eb88bb7 100644 --- a/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_1l_imm.rs +++ b/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_1l_imm.rs @@ -12,6 +12,18 @@ pub mod MOV_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; #[inline] pub const fn MOV_i_T1( Rd: ::aarchmrs_types::BitValue<3>, @@ -31,6 +43,18 @@ pub mod CMP_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; #[inline] pub const fn CMP_i_T1( Rn: ::aarchmrs_types::BitValue<3>, @@ -50,6 +74,18 @@ pub mod ADD_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; #[inline] pub const fn ADD_i_T2( Rdn: ::aarchmrs_types::BitValue<3>, @@ -69,6 +105,18 @@ pub mod SUB_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; #[inline] pub const fn SUB_i_T2( Rdn: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_2l_imm.rs b/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_2l_imm.rs index c3307f35..0c83cf1c 100644 --- a/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_2l_imm.rs +++ b/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_2l_imm.rs @@ -12,6 +12,24 @@ pub mod ADD_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn ADD_i_T1( imm3: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod SUB_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn SUB_i_T1( imm3: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_3l.rs b/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_3l.rs index c40807d3..3c63c22e 100644 --- a/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_3l.rs +++ b/aarchmrs-instructions/src/T32/n/sftdpi/addsub16_3l.rs @@ -12,6 +12,24 @@ pub mod ADD_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn ADD_r_T1( Rm: ::aarchmrs_types::BitValue<3>, @@ -35,6 +53,24 @@ pub mod SUB_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; #[inline] pub const fn SUB_r_T1( Rm: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/n/sftdpi/shift16_imm.rs b/aarchmrs-instructions/src/T32/n/sftdpi/shift16_imm.rs index 6c9a012b..97604f92 100644 --- a/aarchmrs-instructions/src/T32/n/sftdpi/shift16_imm.rs +++ b/aarchmrs-instructions/src/T32/n/sftdpi/shift16_imm.rs @@ -12,6 +12,30 @@ pub mod MOV_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm5_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; #[inline] pub const fn MOV_r_T2( op: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/T32/n/spcd/addsub16_2h.rs b/aarchmrs-instructions/src/T32/n/spcd/addsub16_2h.rs index d06e00e7..e2768f01 100644 --- a/aarchmrs-instructions/src/T32/n/spcd/addsub16_2h.rs +++ b/aarchmrs-instructions/src/T32/n/spcd/addsub16_2h.rs @@ -12,6 +12,24 @@ pub mod ADD_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_DN_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_DN_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_r_T2( DN: ::aarchmrs_types::BitValue<1>, @@ -35,6 +53,18 @@ pub mod ADD_SP_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rdm_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_DM_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_DM_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_SP_r_T1( DM: ::aarchmrs_types::BitValue<1>, @@ -57,6 +87,12 @@ pub mod ADD_SP_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_SP_r_T2( Rm: ::aarchmrs_types::BitValue<4>, @@ -75,6 +111,24 @@ pub mod CMP_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; #[inline] pub const fn CMP_r_T2( N: ::aarchmrs_types::BitValue<1>, @@ -98,6 +152,24 @@ pub mod MOV_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn MOV_r_T1( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/n/spcd/bx16.rs b/aarchmrs-instructions/src/T32/n/spcd/bx16.rs index f00ee307..66998228 100644 --- a/aarchmrs-instructions/src/T32/n/spcd/bx16.rs +++ b/aarchmrs-instructions/src/T32/n/spcd/bx16.rs @@ -12,6 +12,12 @@ pub mod BX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000111u32; #[cfg(feature = "meta")] pub const NAME: &str = "BX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; #[inline] pub const fn BX_T1(Rm: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( @@ -28,6 +34,12 @@ pub mod BLX_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000111u32; #[cfg(feature = "meta")] pub const NAME: &str = "BLX_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; #[inline] pub const fn BLX_r_T1(Rm: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/b.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/b.rs index 0e9cc669..8fb03fb3 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/b.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/b.rs @@ -12,6 +12,36 @@ pub mod B_T4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "B_T4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_WIDTH: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10_WIDTH: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn B_T4( S: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/bcond.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/bcond.rs index 8d7a8625..319c9efc 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/bcond.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/bcond.rs @@ -12,6 +12,42 @@ pub mod B_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "B_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_WIDTH: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cond_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn B_T3( S: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/bl.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/bl.rs index 7e9acc53..97613dc7 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/bl.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/bl.rs @@ -12,6 +12,36 @@ pub mod BL_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BL_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm11_WIDTH: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10_WIDTH: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn BL_i_T1( S: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/blx.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/blx.rs index 93392ca3..6153842b 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/blx.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/blx.rs @@ -12,6 +12,42 @@ pub mod BL_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BL_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_H_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10L_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10L_WIDTH: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_OFFSET: u32 = 11u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J2_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_OFFSET: u32 = 13u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_J1_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10H_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm10H_WIDTH: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; #[inline] pub const fn BL_i_T2( S: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/bx_jaz.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/bx_jaz.rs index e005e222..e914a018 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/bx_jaz.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/bx_jaz.rs @@ -12,6 +12,12 @@ pub mod BXJ_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000010111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "BXJ_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; #[inline] pub const fn BXJ_T1(Rm: ::aarchmrs_types::BitValue<4>) -> ::aarchmrs_types::InstructionCode { ::aarchmrs_types::InstructionCode::from_u32( diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/cps.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/cps.rs index fa4911d4..79ad1bdd 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/cps.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/cps.rs @@ -12,6 +12,30 @@ pub mod CPS_T2_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010100000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPS_T2_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPS_T2_AS( A: ::aarchmrs_types::BitValue<1>, @@ -37,6 +61,30 @@ pub mod CPSID_T2_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010100000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSID_T2_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSID_T2_AS( A: ::aarchmrs_types::BitValue<1>, @@ -62,6 +110,30 @@ pub mod CPSID_T2_ASM { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010100000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSID_T2_ASM"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSID_T2_ASM( A: ::aarchmrs_types::BitValue<1>, @@ -87,6 +159,30 @@ pub mod CPSIE_T2_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010100000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSIE_T2_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSIE_T2_AS( A: ::aarchmrs_types::BitValue<1>, @@ -112,6 +208,30 @@ pub mod CPSIE_T2_ASM { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010100000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CPSIE_T2_ASM"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_I_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_A_WIDTH: u32 = 1u32; #[inline] pub const fn CPSIE_T2_ASM( A: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/eret.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/eret.rs index 9ec01519..deacdb27 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/eret.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/eret.rs @@ -12,6 +12,18 @@ pub mod SUBS_PC_T5_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000010111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_PC_T5_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_PC_T5_AS( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/except.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/except.rs index 08106a1d..41506eb2 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/except.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/except.rs @@ -12,6 +12,18 @@ pub mod HVC_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "HVC_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn HVC_T1( imm4: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,12 @@ pub mod SMC_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMC_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn SMC_T1_AS( imm4: ::aarchmrs_types::BitValue<4>, @@ -52,6 +70,18 @@ pub mod UDF_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDF_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; #[inline] pub const fn UDF_T2( imm4: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/hints.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/hints.rs index b9e58bab..f67de5d7 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/hints.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/hints.rs @@ -152,6 +152,12 @@ pub mod DBG_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010100000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DBG_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; #[inline] pub const fn DBG_T1( option: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_bank.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_bank.rs index efd31d7f..96fa0b28 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_bank.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_bank.rs @@ -12,6 +12,30 @@ pub mod MRS_br_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000010000011001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRS_br_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; #[inline] pub const fn MRS_br_T1_AS( R: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_spec.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_spec.rs index 736b2301..dc142f00 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_spec.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/mrs_spec.rs @@ -12,6 +12,18 @@ pub mod MRS_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010000011011111u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRS_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; #[inline] pub const fn MRS_T1_AS( R: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/msr_bank.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/msr_bank.rs index 94170d1b..53d2bbc8 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/msr_bank.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/msr_bank.rs @@ -12,6 +12,30 @@ pub mod MSR_br_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000010000011001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSR_br_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; #[inline] pub const fn MSR_br_T1_AS( R: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/msr_spec.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/msr_spec.rs index e634c20e..83392aca 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/msr_spec.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/msr_spec.rs @@ -12,6 +12,24 @@ pub mod MSR_r_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000010000011011111u32; #[cfg(feature = "meta")] pub const NAME: &str = "MSR_r_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mask_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_R_WIDTH: u32 = 1u32; #[inline] pub const fn MSR_r_T1_AS( R: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/bcrtrl/system.rs b/aarchmrs-instructions/src/T32/w/bcrtrl/system.rs index 9c6aba66..2063eba5 100644 --- a/aarchmrs-instructions/src/T32/w/bcrtrl/system.rs +++ b/aarchmrs-instructions/src/T32/w/bcrtrl/system.rs @@ -26,6 +26,12 @@ pub mod DSB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DSB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; #[inline] pub const fn DSB_T1( option: ::aarchmrs_types::BitValue<4>, @@ -72,6 +78,12 @@ pub mod DMB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "DMB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; #[inline] pub const fn DMB_T1( option: ::aarchmrs_types::BitValue<4>, @@ -90,6 +102,12 @@ pub mod ISB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000011110010111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ISB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_option_WIDTH: u32 = 4u32; #[inline] pub const fn ISB_T1( option: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_csel.rs b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_csel.rs index 3660c560..a6eaaa19 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_csel.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_csel.rs @@ -12,6 +12,42 @@ pub mod VSELEQ_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELEQ_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELEQ_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VSELEQ_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELEQ_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELEQ_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VSELEQ_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELEQ_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELEQ_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VSELGE_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGE_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGE_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VSELGE_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGE_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGE_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VSELGE_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGE_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGE_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -210,6 +426,42 @@ pub mod VSELGT_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGT_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGT_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -243,6 +495,42 @@ pub mod VSELGT_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGT_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGT_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -276,6 +564,42 @@ pub mod VSELGT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELGT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELGT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -309,6 +633,42 @@ pub mod VSELVS_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELVS_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELVS_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -342,6 +702,42 @@ pub mod VSELVS_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELVS_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELVS_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -375,6 +771,42 @@ pub mod VSELVS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSELVS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSELVS_T1_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_extins.rs b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_extins.rs index 0b9f1410..b231eab5 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_extins.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_extins.rs @@ -12,6 +12,30 @@ pub mod VMOVX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOVX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOVX_T1( D: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod VINS_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VINS_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VINS_T1( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_minmax.rs b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_minmax.rs index fdb245a7..24f4e1e1 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_minmax.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_minmax.rs @@ -12,6 +12,42 @@ pub mod VMAXNM_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VMAXNM_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VMAXNM_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VMINNM_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VMINNM_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VMINNM_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_T2_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_toint.rs b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_toint.rs index 8ba5754b..6e6d3736 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_toint.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/fp_toint.rs @@ -12,6 +12,30 @@ pub mod VRINTA_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod VRINTA_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -68,6 +116,30 @@ pub mod VRINTA_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -96,6 +168,30 @@ pub mod VRINTN_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -124,6 +220,30 @@ pub mod VRINTN_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -152,6 +272,30 @@ pub mod VRINTN_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -180,6 +324,30 @@ pub mod VRINTP_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -208,6 +376,30 @@ pub mod VRINTP_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -236,6 +428,30 @@ pub mod VRINTP_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -264,6 +480,30 @@ pub mod VRINTM_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -292,6 +532,30 @@ pub mod VRINTM_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -320,6 +584,30 @@ pub mod VRINTM_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -348,6 +636,36 @@ pub mod VCVTA_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -379,6 +697,36 @@ pub mod VCVTA_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -410,6 +758,36 @@ pub mod VCVTA_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -441,6 +819,36 @@ pub mod VCVTN_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -472,6 +880,36 @@ pub mod VCVTN_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -503,6 +941,36 @@ pub mod VCVTN_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -534,6 +1002,36 @@ pub mod VCVTP_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -565,6 +1063,36 @@ pub mod VCVTP_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -596,6 +1124,36 @@ pub mod VCVTP_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -627,6 +1185,36 @@ pub mod VCVTM_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -658,6 +1246,36 @@ pub mod VCVTM_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -689,6 +1307,36 @@ pub mod VCVTM_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/simd_3sameext.rs b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/simd_3sameext.rs index b5279682..9645195c 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/simd_3sameext.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/simd_3sameext.rs @@ -12,6 +12,54 @@ pub mod VCADD_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCADD_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; #[inline] pub const fn VCADD_T1_D( rot: ::aarchmrs_types::BitValue<1>, @@ -50,6 +98,54 @@ pub mod VCADD_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCADD_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 1u32; #[inline] pub const fn VCADD_T1_Q( rot: ::aarchmrs_types::BitValue<1>, @@ -88,6 +184,42 @@ pub mod VMMLA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMMLA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMMLA_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -121,6 +253,42 @@ pub mod VDOT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -154,6 +322,42 @@ pub mod VDOT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -187,6 +391,42 @@ pub mod VFMAL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -220,6 +460,42 @@ pub mod VFMAL_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -253,6 +529,42 @@ pub mod VSMMLA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSMMLA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSMMLA_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -286,6 +598,42 @@ pub mod VUMMLA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUMMLA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUMMLA_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -319,6 +667,42 @@ pub mod VSDOT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -352,6 +736,42 @@ pub mod VSDOT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -385,6 +805,42 @@ pub mod VUDOT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -418,6 +874,42 @@ pub mod VUDOT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -451,6 +943,48 @@ pub mod VFMA_bf_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_bf_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_bf_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -485,6 +1019,42 @@ pub mod VFMSL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -518,6 +1088,42 @@ pub mod VFMSL_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -551,6 +1157,42 @@ pub mod VUSMMLA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSMMLA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSMMLA_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -584,6 +1226,42 @@ pub mod VUSDOT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -617,6 +1295,42 @@ pub mod VUSDOT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -650,6 +1364,54 @@ pub mod VCMLA_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; #[inline] pub const fn VCMLA_T1_D( rot: ::aarchmrs_types::BitValue<2>, @@ -687,6 +1449,54 @@ pub mod VCMLA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_S_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; #[inline] pub const fn VCMLA_T1_Q( rot: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tfloatdpmac.rs b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tfloatdpmac.rs index a18728b6..f8f8b7ef 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tfloatdpmac.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tfloatdpmac.rs @@ -12,6 +12,48 @@ pub mod VCMLA_s_T1_DH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_T1_DH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_T1_DH( D: ::aarchmrs_types::BitValue<1>, @@ -46,6 +88,48 @@ pub mod VCMLA_s_T1_DS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_T1_DS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_T1_DS( D: ::aarchmrs_types::BitValue<1>, @@ -80,6 +164,48 @@ pub mod VCMLA_s_T1_QH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_T1_QH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_T1_QH( D: ::aarchmrs_types::BitValue<1>, @@ -114,6 +240,48 @@ pub mod VCMLA_s_T1_QS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMLA_s_T1_QS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rot_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMLA_s_T1_QS( D: ::aarchmrs_types::BitValue<1>, @@ -148,6 +316,42 @@ pub mod VFMAL_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -181,6 +385,42 @@ pub mod VFMAL_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMAL_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMAL_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -214,6 +454,42 @@ pub mod VFMSL_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -247,6 +523,42 @@ pub mod VFMSL_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMSL_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMSL_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -280,6 +592,48 @@ pub mod VFMA_bfs_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_bfs_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_bfs_T1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tsimd_dotprod.rs b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tsimd_dotprod.rs index 5a8fa838..7c8b5760 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tsimd_dotprod.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/advsimdext/tsimd_dotprod.rs @@ -12,6 +12,42 @@ pub mod VDOT_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VDOT_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDOT_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDOT_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VSDOT_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VSDOT_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSDOT_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSDOT_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VUDOT_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VUDOT_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUDOT_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUDOT_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -210,6 +426,42 @@ pub mod VUSDOT_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -243,6 +495,42 @@ pub mod VUSDOT_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUSDOT_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUSDOT_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -276,6 +564,42 @@ pub mod VSUDOT_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUDOT_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUDOT_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -309,6 +633,42 @@ pub mod VSUDOT_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUDOT_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUDOT_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_2r.rs b/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_2r.rs index 7234226a..0ec761ef 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_2r.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_2r.rs @@ -12,6 +12,30 @@ pub mod VABS_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABS_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod VABS_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABS_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -68,6 +116,30 @@ pub mod VABS_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABS_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -96,6 +168,30 @@ pub mod VMOV_r_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_r_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_r_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -124,6 +220,30 @@ pub mod VMOV_r_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_r_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_r_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -152,6 +272,30 @@ pub mod VNEG_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNEG_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -180,6 +324,30 @@ pub mod VNEG_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNEG_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -208,6 +376,30 @@ pub mod VNEG_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNEG_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -236,6 +428,30 @@ pub mod VSQRT_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSQRT_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSQRT_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -264,6 +480,30 @@ pub mod VSQRT_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSQRT_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSQRT_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -292,6 +532,30 @@ pub mod VSQRT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSQRT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSQRT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -320,6 +584,30 @@ pub mod VCVTB_T1_SH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_T1_SH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTB_T1_SH( D: ::aarchmrs_types::BitValue<1>, @@ -348,6 +636,30 @@ pub mod VCVTB_T1_DH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_T1_DH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTB_T1_DH( D: ::aarchmrs_types::BitValue<1>, @@ -376,6 +688,30 @@ pub mod VCVTB_T1_HS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_T1_HS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTB_T1_HS( D: ::aarchmrs_types::BitValue<1>, @@ -404,6 +740,30 @@ pub mod VCVTB_T1_HD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_T1_HD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTB_T1_HD( D: ::aarchmrs_types::BitValue<1>, @@ -432,6 +792,30 @@ pub mod VCVTT_T1_SH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_T1_SH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTT_T1_SH( D: ::aarchmrs_types::BitValue<1>, @@ -460,6 +844,30 @@ pub mod VCVTT_T1_DH { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_T1_DH"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTT_T1_DH( D: ::aarchmrs_types::BitValue<1>, @@ -488,6 +896,30 @@ pub mod VCVTT_T1_HS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_T1_HS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTT_T1_HS( D: ::aarchmrs_types::BitValue<1>, @@ -516,6 +948,30 @@ pub mod VCVTT_T1_HD { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_T1_HD"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTT_T1_HD( D: ::aarchmrs_types::BitValue<1>, @@ -544,6 +1000,30 @@ pub mod VCVTB_T1_bfs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTB_T1_bfs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTB_T1_bfs( D: ::aarchmrs_types::BitValue<1>, @@ -572,6 +1052,30 @@ pub mod VCVTT_T1_bfs { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTT_T1_bfs"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTT_T1_bfs( D: ::aarchmrs_types::BitValue<1>, @@ -600,6 +1104,30 @@ pub mod VCMP_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMP_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -628,6 +1156,30 @@ pub mod VCMP_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMP_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -656,6 +1208,30 @@ pub mod VCMP_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMP_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -684,6 +1260,30 @@ pub mod VCMPE_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMPE_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -712,6 +1312,30 @@ pub mod VCMPE_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMPE_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -740,6 +1364,30 @@ pub mod VCMPE_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMPE_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -768,6 +1416,18 @@ pub mod VCMP_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMP_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -791,6 +1451,18 @@ pub mod VCMP_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMP_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -814,6 +1486,18 @@ pub mod VCMP_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMP_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMP_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -837,6 +1521,18 @@ pub mod VCMPE_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMPE_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -860,6 +1556,18 @@ pub mod VCMPE_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMPE_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -883,6 +1591,18 @@ pub mod VCMPE_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCMPE_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCMPE_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -906,6 +1626,30 @@ pub mod VRINTR_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTR_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTR_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -934,6 +1678,30 @@ pub mod VRINTR_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTR_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTR_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -962,6 +1730,30 @@ pub mod VRINTR_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTR_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTR_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -990,6 +1782,30 @@ pub mod VRINTZ_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTZ_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1018,6 +1834,30 @@ pub mod VRINTZ_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTZ_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1046,6 +1886,30 @@ pub mod VRINTZ_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTZ_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1074,6 +1938,30 @@ pub mod VRINTX_vfp_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_vfp_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTX_vfp_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1102,6 +1990,30 @@ pub mod VRINTX_vfp_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_vfp_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTX_vfp_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1130,6 +2042,30 @@ pub mod VRINTX_vfp_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_vfp_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTX_vfp_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1158,6 +2094,30 @@ pub mod VCVT_ds_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_ds_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_ds_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1186,6 +2146,30 @@ pub mod VCVT_sd_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_sd_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_sd_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1214,6 +2198,36 @@ pub mod VCVT_vi_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_vi_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_vi_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1245,6 +2259,36 @@ pub mod VCVT_vi_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_vi_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_vi_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1276,6 +2320,36 @@ pub mod VCVT_vi_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_vi_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_vi_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1307,6 +2381,30 @@ pub mod VJCVT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VJCVT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VJCVT_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1335,6 +2433,42 @@ pub mod VCVT_toxv_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_toxv_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_toxv_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1368,6 +2502,42 @@ pub mod VCVT_xv_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xv_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_xv_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1401,6 +2571,42 @@ pub mod VCVT_toxv_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_toxv_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_toxv_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1434,6 +2640,42 @@ pub mod VCVT_xv_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xv_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_xv_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1467,6 +2709,42 @@ pub mod VCVT_toxv_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_toxv_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_toxv_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1500,6 +2778,42 @@ pub mod VCVT_xv_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xv_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sx_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_xv_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1533,6 +2847,30 @@ pub mod VCVTR_uiv_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_uiv_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTR_uiv_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1561,6 +2899,30 @@ pub mod VCVTR_siv_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_siv_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTR_siv_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1589,6 +2951,30 @@ pub mod VCVTR_uiv_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_uiv_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTR_uiv_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1617,6 +3003,30 @@ pub mod VCVTR_siv_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_siv_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTR_siv_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1645,6 +3055,30 @@ pub mod VCVTR_uiv_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_uiv_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTR_uiv_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1673,6 +3107,30 @@ pub mod VCVTR_siv_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTR_siv_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTR_siv_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1701,6 +3159,30 @@ pub mod VCVT_uiv_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_uiv_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_uiv_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1729,6 +3211,30 @@ pub mod VCVT_siv_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_siv_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_siv_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1757,6 +3263,30 @@ pub mod VCVT_uiv_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_uiv_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_uiv_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1785,6 +3315,30 @@ pub mod VCVT_siv_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_siv_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_siv_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1813,6 +3367,30 @@ pub mod VCVT_uiv_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_uiv_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_uiv_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1841,6 +3419,30 @@ pub mod VCVT_siv_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_siv_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_siv_T1_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_3r.rs b/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_3r.rs index 47507122..4f9557ff 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_3r.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_3r.rs @@ -12,6 +12,42 @@ pub mod VMLA_f_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_f_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VMLA_f_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_f_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VMLA_f_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_f_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VMLS_f_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_f_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VMLS_f_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_f_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VMLS_f_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_f_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -210,6 +426,42 @@ pub mod VNMLS_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLS_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMLS_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -243,6 +495,42 @@ pub mod VNMLS_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLS_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMLS_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -276,6 +564,42 @@ pub mod VNMLS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMLS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -309,6 +633,42 @@ pub mod VNMLA_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLA_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMLA_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -342,6 +702,42 @@ pub mod VNMLA_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLA_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMLA_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -375,6 +771,42 @@ pub mod VNMLA_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMLA_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMLA_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -408,6 +840,42 @@ pub mod VMUL_f_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_f_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -441,6 +909,42 @@ pub mod VMUL_f_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_f_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -474,6 +978,42 @@ pub mod VMUL_f_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_f_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -507,6 +1047,42 @@ pub mod VNMUL_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMUL_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMUL_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -540,6 +1116,42 @@ pub mod VNMUL_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMUL_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMUL_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -573,6 +1185,42 @@ pub mod VNMUL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNMUL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNMUL_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -606,6 +1254,42 @@ pub mod VADD_f_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_f_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -639,6 +1323,42 @@ pub mod VADD_f_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_f_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -672,6 +1392,42 @@ pub mod VADD_f_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_f_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -705,6 +1461,42 @@ pub mod VSUB_f_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_f_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -738,6 +1530,42 @@ pub mod VSUB_f_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_f_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -771,6 +1599,42 @@ pub mod VSUB_f_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_f_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -804,6 +1668,42 @@ pub mod VDIV_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDIV_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDIV_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -837,6 +1737,42 @@ pub mod VDIV_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDIV_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDIV_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -870,6 +1806,42 @@ pub mod VDIV_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDIV_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDIV_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -903,6 +1875,42 @@ pub mod VFNMS_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMS_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFNMS_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -936,6 +1944,42 @@ pub mod VFNMS_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMS_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFNMS_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -969,6 +2013,42 @@ pub mod VFNMS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFNMS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1002,6 +2082,42 @@ pub mod VFNMA_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMA_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFNMA_T1_H( D: ::aarchmrs_types::BitValue<1>, @@ -1035,6 +2151,42 @@ pub mod VFNMA_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMA_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFNMA_T1_S( D: ::aarchmrs_types::BitValue<1>, @@ -1068,6 +2220,42 @@ pub mod VFNMA_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFNMA_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFNMA_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1101,6 +2289,42 @@ pub mod VFMA_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -1134,6 +2358,42 @@ pub mod VFMA_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -1167,6 +2427,42 @@ pub mod VFMA_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -1200,6 +2496,42 @@ pub mod VFMS_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMS_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -1233,6 +2565,42 @@ pub mod VFMS_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMS_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -1266,6 +2634,42 @@ pub mod VFMS_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMS_T2_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_movi.rs b/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_movi.rs index 9d515a4f..26ff5d64 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_movi.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/fpdp/fp_movi.rs @@ -12,6 +12,30 @@ pub mod VMOV_i_T2_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000010100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T2_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T2_H( D: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,30 @@ pub mod VMOV_i_T2_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000010100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T2_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T2_S( D: ::aarchmrs_types::BitValue<1>, @@ -66,6 +114,30 @@ pub mod VMOV_i_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000010100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4L_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4H_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T2_D( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/simd_3same.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/simd_3same.rs index fe5c7bda..130a06a1 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/simd_3same.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/simd_3same.rs @@ -12,6 +12,48 @@ pub mod VFMA_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -47,6 +89,48 @@ pub mod VFMA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMA_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -82,6 +166,48 @@ pub mod VADD_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -117,6 +243,48 @@ pub mod VADD_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -152,6 +320,48 @@ pub mod VMLA_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -187,6 +397,48 @@ pub mod VMLA_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -222,6 +474,48 @@ pub mod VCEQ_r_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -257,6 +551,48 @@ pub mod VCEQ_r_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_T2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -292,6 +628,48 @@ pub mod VMAX_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -327,6 +705,48 @@ pub mod VMAX_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -362,6 +782,48 @@ pub mod VRECPS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -397,6 +859,48 @@ pub mod VRECPS_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPS_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPS_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -432,6 +936,54 @@ pub mod VHADD_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHADD_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHADD_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -469,6 +1021,54 @@ pub mod VHADD_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHADD_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHADD_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -506,6 +1106,42 @@ pub mod VAND_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VAND_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VAND_r_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -539,6 +1175,42 @@ pub mod VAND_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VAND_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VAND_r_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -572,6 +1244,54 @@ pub mod VQADD_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQADD_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQADD_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -609,6 +1329,54 @@ pub mod VQADD_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQADD_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQADD_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -646,6 +1414,54 @@ pub mod VRHADD_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRHADD_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRHADD_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -683,6 +1499,54 @@ pub mod VRHADD_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRHADD_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRHADD_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -720,6 +1584,48 @@ pub mod SHA1C_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1C_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1C_T1( D: ::aarchmrs_types::BitValue<1>, @@ -754,6 +1660,54 @@ pub mod VHSUB_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHSUB_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHSUB_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -791,6 +1745,54 @@ pub mod VHSUB_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VHSUB_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VHSUB_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -828,6 +1830,42 @@ pub mod VBIC_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_r_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -861,6 +1899,42 @@ pub mod VBIC_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_r_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -894,6 +1968,54 @@ pub mod VQSUB_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSUB_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSUB_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -931,6 +2053,54 @@ pub mod VQSUB_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSUB_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSUB_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -968,6 +2138,54 @@ pub mod VCGT_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1005,6 +2223,54 @@ pub mod VCGT_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1042,6 +2308,54 @@ pub mod VCGE_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1079,6 +2393,54 @@ pub mod VCGE_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1116,6 +2478,48 @@ pub mod SHA1P_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1P_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1P_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1150,6 +2554,48 @@ pub mod VFMS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1185,6 +2631,48 @@ pub mod VFMS_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VFMS_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VFMS_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1220,6 +2708,48 @@ pub mod VSUB_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1255,6 +2785,48 @@ pub mod VSUB_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1290,6 +2862,48 @@ pub mod VMLS_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1325,6 +2939,48 @@ pub mod VMLS_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1360,6 +3016,48 @@ pub mod VMIN_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1395,6 +3093,48 @@ pub mod VMIN_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1430,6 +3170,48 @@ pub mod VRSQRTS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1465,6 +3247,48 @@ pub mod VRSQRTS_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTS_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTS_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1500,6 +3324,54 @@ pub mod VSHL_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_r_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1537,6 +3409,54 @@ pub mod VSHL_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_r_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1574,6 +3494,48 @@ pub mod VADD_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1608,6 +3570,48 @@ pub mod VADD_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADD_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADD_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1642,6 +3646,42 @@ pub mod VORR_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_r_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1675,6 +3715,42 @@ pub mod VORR_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_r_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1708,6 +3784,48 @@ pub mod VTST_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTST_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTST_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1742,6 +3860,48 @@ pub mod VTST_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTST_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTST_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1776,6 +3936,54 @@ pub mod VQSHL_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_r_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1813,6 +4021,54 @@ pub mod VQSHL_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_r_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1850,6 +4106,48 @@ pub mod VMLA_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1884,6 +4182,48 @@ pub mod VMLA_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1918,6 +4258,54 @@ pub mod VRSHL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHL_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -1955,6 +4343,54 @@ pub mod VRSHL_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHL_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHL_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -1992,6 +4428,54 @@ pub mod VQRSHL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHL_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2029,6 +4513,54 @@ pub mod VQRSHL_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHL_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHL_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2066,6 +4598,48 @@ pub mod VQDMULH_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2100,6 +4674,48 @@ pub mod VQDMULH_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2134,6 +4750,48 @@ pub mod SHA1M_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1M_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1M_T1( D: ::aarchmrs_types::BitValue<1>, @@ -2168,6 +4826,54 @@ pub mod VPADD_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADD_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADD_i_T1( D: ::aarchmrs_types::BitValue<1>, @@ -2203,6 +4909,54 @@ pub mod VMAX_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_i_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2240,6 +4994,54 @@ pub mod VMAX_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAX_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMAX_i_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2277,6 +5079,42 @@ pub mod VORN_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORN_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORN_r_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2310,6 +5148,42 @@ pub mod VORN_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORN_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VORN_r_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2343,6 +5217,54 @@ pub mod VMIN_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_i_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2380,6 +5302,54 @@ pub mod VMIN_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMIN_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMIN_i_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2417,6 +5387,54 @@ pub mod VABD_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_i_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2454,6 +5472,54 @@ pub mod VABD_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_i_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2491,6 +5557,54 @@ pub mod VABA_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABA_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABA_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -2528,6 +5642,54 @@ pub mod VABA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABA_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -2565,6 +5727,48 @@ pub mod SHA1SU0_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1SU0_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1SU0_T1( D: ::aarchmrs_types::BitValue<1>, @@ -2599,6 +5803,54 @@ pub mod VPADD_f_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADD_f_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADD_f_T1( D: ::aarchmrs_types::BitValue<1>, @@ -2635,6 +5887,48 @@ pub mod VMUL_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2670,6 +5964,48 @@ pub mod VMUL_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2705,6 +6041,48 @@ pub mod VCGE_r_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -2740,6 +6118,48 @@ pub mod VCGE_r_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_r_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_r_T2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2775,6 +6195,48 @@ pub mod VACGE_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGE_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGE_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2810,6 +6272,48 @@ pub mod VACGE_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGE_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGE_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2845,6 +6349,48 @@ pub mod VPMAX_f_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMAX_f_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPMAX_f_T1( D: ::aarchmrs_types::BitValue<1>, @@ -2880,6 +6426,48 @@ pub mod VMAXNM_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2915,6 +6503,48 @@ pub mod VMAXNM_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMAXNM_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMAXNM_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2950,6 +6580,42 @@ pub mod VEOR_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEOR_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEOR_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2983,6 +6649,42 @@ pub mod VEOR_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEOR_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEOR_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3016,6 +6718,54 @@ pub mod VMUL_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_i_T1_D( op: ::aarchmrs_types::BitValue<1>, @@ -3053,6 +6803,54 @@ pub mod VMUL_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_i_T1_Q( op: ::aarchmrs_types::BitValue<1>, @@ -3090,6 +6888,48 @@ pub mod SHA256H_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256H_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256H_T1( D: ::aarchmrs_types::BitValue<1>, @@ -3124,6 +6964,54 @@ pub mod VPMAX_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMAX_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VPMAX_i_T1( U: ::aarchmrs_types::BitValue<1>, @@ -3161,6 +7049,42 @@ pub mod VBSL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBSL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBSL_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3194,6 +7118,42 @@ pub mod VBSL_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBSL_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBSL_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3227,6 +7187,54 @@ pub mod VPMIN_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMIN_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VPMIN_i_T1( U: ::aarchmrs_types::BitValue<1>, @@ -3264,6 +7272,48 @@ pub mod SHA256H2_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256H2_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256H2_T1( D: ::aarchmrs_types::BitValue<1>, @@ -3298,6 +7348,48 @@ pub mod VABD_f_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_f_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_f_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3333,6 +7425,48 @@ pub mod VABD_f_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABD_f_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABD_f_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3368,6 +7502,48 @@ pub mod VCGT_r_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -3403,6 +7579,48 @@ pub mod VCGT_r_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_r_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_r_T2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3438,6 +7656,48 @@ pub mod VACGT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3473,6 +7733,48 @@ pub mod VACGT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VACGT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VACGT_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3508,6 +7810,48 @@ pub mod VPMIN_f_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPMIN_f_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPMIN_f_T1( D: ::aarchmrs_types::BitValue<1>, @@ -3543,6 +7887,48 @@ pub mod VMINNM_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3578,6 +7964,48 @@ pub mod VMINNM_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMINNM_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sz_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMINNM_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3613,6 +8041,48 @@ pub mod VSUB_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3647,6 +8117,48 @@ pub mod VSUB_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUB_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUB_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3681,6 +8193,42 @@ pub mod VBIT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3714,6 +8262,42 @@ pub mod VBIT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIT_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3747,6 +8331,48 @@ pub mod VCEQ_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3781,6 +8407,48 @@ pub mod VCEQ_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_r_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3815,6 +8483,48 @@ pub mod VMLS_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3849,6 +8559,48 @@ pub mod VMLS_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3883,6 +8635,48 @@ pub mod VQRDMULH_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -3917,6 +8711,48 @@ pub mod VQRDMULH_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -3951,6 +8787,48 @@ pub mod SHA256SU1_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256SU1_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Q_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256SU1_T1( D: ::aarchmrs_types::BitValue<1>, @@ -3985,6 +8863,48 @@ pub mod VQRDMLAH_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -4019,6 +8939,48 @@ pub mod VQRDMLAH_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -4053,6 +9015,42 @@ pub mod VBIF_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIF_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIF_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -4086,6 +9084,42 @@ pub mod VBIF_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIF_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VBIF_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -4119,6 +9153,48 @@ pub mod VQRDMLSH_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -4153,6 +9229,48 @@ pub mod VQRDMLSH_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_T1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_1r_imm.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_1r_imm.rs index bff91c91..7ed3c44f 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_1r_imm.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_1r_imm.rs @@ -12,6 +12,42 @@ pub mod VMOV_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T1_D( i: ::aarchmrs_types::BitValue<1>, @@ -45,6 +81,42 @@ pub mod VMOV_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -78,6 +150,42 @@ pub mod VMVN_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_T1_D( i: ::aarchmrs_types::BitValue<1>, @@ -111,6 +219,42 @@ pub mod VMVN_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_T1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -144,6 +288,42 @@ pub mod VORR_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_T1_D( i: ::aarchmrs_types::BitValue<1>, @@ -177,6 +357,42 @@ pub mod VORR_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_T1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -210,6 +426,42 @@ pub mod VBIC_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_T1_D( i: ::aarchmrs_types::BitValue<1>, @@ -243,6 +495,42 @@ pub mod VBIC_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_T1_Q( i: ::aarchmrs_types::BitValue<1>, @@ -276,6 +564,42 @@ pub mod VMOV_i_T3_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T3_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T3_D( i: ::aarchmrs_types::BitValue<1>, @@ -309,6 +633,42 @@ pub mod VMOV_i_T3_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T3_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T3_Q( i: ::aarchmrs_types::BitValue<1>, @@ -342,6 +702,42 @@ pub mod VMVN_i_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_T2_D( i: ::aarchmrs_types::BitValue<1>, @@ -375,6 +771,42 @@ pub mod VMVN_i_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_T2_Q( i: ::aarchmrs_types::BitValue<1>, @@ -408,6 +840,42 @@ pub mod VORR_i_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_T2_D( i: ::aarchmrs_types::BitValue<1>, @@ -441,6 +909,42 @@ pub mod VORR_i_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VORR_i_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VORR_i_T2_Q( i: ::aarchmrs_types::BitValue<1>, @@ -474,6 +978,42 @@ pub mod VBIC_i_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_T2_D( i: ::aarchmrs_types::BitValue<1>, @@ -507,6 +1047,42 @@ pub mod VBIC_i_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VBIC_i_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VBIC_i_T2_Q( i: ::aarchmrs_types::BitValue<1>, @@ -540,6 +1116,42 @@ pub mod VMOV_i_T4_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T4_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T4_D( i: ::aarchmrs_types::BitValue<1>, @@ -573,6 +1185,42 @@ pub mod VMOV_i_T4_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T4_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T4_Q( i: ::aarchmrs_types::BitValue<1>, @@ -606,6 +1254,42 @@ pub mod VMVN_i_T3_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_T3_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_T3_D( i: ::aarchmrs_types::BitValue<1>, @@ -639,6 +1323,42 @@ pub mod VMVN_i_T3_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_i_T3_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cmode_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_i_T3_Q( i: ::aarchmrs_types::BitValue<1>, @@ -672,6 +1392,36 @@ pub mod VMOV_i_T5_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T5_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T5_D( i: ::aarchmrs_types::BitValue<1>, @@ -702,6 +1452,36 @@ pub mod VMOV_i_T5_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_i_T5_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_i_T5_Q( i: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_2r_shift.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_2r_shift.rs index 7a52141d..4e3dd17d 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_2r_shift.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_12reg/simd_2r_shift.rs @@ -12,6 +12,48 @@ pub mod VSHR_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHR_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHR_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -47,6 +89,48 @@ pub mod VSHR_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHR_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHR_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -82,6 +166,48 @@ pub mod VSRA_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRA_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSRA_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -117,6 +243,48 @@ pub mod VSRA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSRA_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -152,6 +320,42 @@ pub mod VMOVL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOVL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3H_OFFSET: u32 = 19u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3H_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMOVL_T1( U: ::aarchmrs_types::BitValue<1>, @@ -185,6 +389,48 @@ pub mod VRSHR_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHR_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHR_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -220,6 +466,48 @@ pub mod VRSHR_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHR_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHR_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -255,6 +543,48 @@ pub mod VRSRA_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSRA_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSRA_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -290,6 +620,48 @@ pub mod VRSRA_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSRA_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VRSRA_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -325,6 +697,48 @@ pub mod VQSHL_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_i_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -360,6 +774,42 @@ pub mod VQSHLU_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHLU_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHLU_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -392,6 +842,48 @@ pub mod VQSHL_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHL_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHL_i_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -427,6 +919,42 @@ pub mod VQSHLU_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHLU_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHLU_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -459,6 +987,42 @@ pub mod VQSHRN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHRN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHRN_T1( U: ::aarchmrs_types::BitValue<1>, @@ -491,6 +1055,36 @@ pub mod VQSHRUN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQSHRUN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQSHRUN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -520,6 +1114,42 @@ pub mod VQRSHRN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHRN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHRN_T1( U: ::aarchmrs_types::BitValue<1>, @@ -552,6 +1182,36 @@ pub mod VQRSHRUN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRSHRUN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRSHRUN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -581,6 +1241,42 @@ pub mod VSHLL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHLL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSHLL_T1( U: ::aarchmrs_types::BitValue<1>, @@ -613,6 +1309,48 @@ pub mod VCVT_xs_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xs_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_xs_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -648,6 +1386,48 @@ pub mod VCVT_xs_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_xs_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_xs_T1_Q( U: ::aarchmrs_types::BitValue<1>, @@ -683,6 +1463,42 @@ pub mod VSHL_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -715,6 +1531,42 @@ pub mod VSHL_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHL_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHL_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -747,6 +1599,36 @@ pub mod VSHRN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHRN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHRN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -776,6 +1658,36 @@ pub mod VRSHRN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSHRN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSHRN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -805,6 +1717,42 @@ pub mod VSRI_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRI_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSRI_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -837,6 +1785,42 @@ pub mod VSRI_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSRI_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSRI_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -869,6 +1853,42 @@ pub mod VSLI_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSLI_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSLI_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -901,6 +1921,42 @@ pub mod VSLI_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSLI_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_L_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm6_WIDTH: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSLI_T1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_misc.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_misc.rs index 4f32ef7f..6c9da53b 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_misc.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_misc.rs @@ -12,6 +12,36 @@ pub mod VREV64_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV64_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV64_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -43,6 +73,36 @@ pub mod VREV64_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV64_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV64_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -74,6 +134,36 @@ pub mod VREV32_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV32_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV32_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -105,6 +195,36 @@ pub mod VREV32_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV32_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV32_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -136,6 +256,36 @@ pub mod VREV16_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV16_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV16_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -167,6 +317,36 @@ pub mod VREV16_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VREV16_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VREV16_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -198,6 +378,42 @@ pub mod VPADDL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADDL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADDL_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -232,6 +448,42 @@ pub mod VPADDL_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADDL_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADDL_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -266,6 +518,36 @@ pub mod AESE_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESE_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESE_T1( D: ::aarchmrs_types::BitValue<1>, @@ -297,6 +579,36 @@ pub mod AESD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESD_T1( D: ::aarchmrs_types::BitValue<1>, @@ -328,6 +640,36 @@ pub mod AESMC_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESMC_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESMC_T1( D: ::aarchmrs_types::BitValue<1>, @@ -359,6 +701,36 @@ pub mod AESIMC_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AESIMC_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn AESIMC_T1( D: ::aarchmrs_types::BitValue<1>, @@ -390,6 +762,36 @@ pub mod VCLS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -421,6 +823,36 @@ pub mod VCLS_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLS_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLS_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -452,6 +884,30 @@ pub mod VSWP_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSWP_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSWP_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -480,6 +936,30 @@ pub mod VSWP_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSWP_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSWP_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -508,6 +988,36 @@ pub mod VCLZ_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLZ_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLZ_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -539,6 +1049,36 @@ pub mod VCLZ_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLZ_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLZ_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -570,6 +1110,36 @@ pub mod VCNT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCNT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCNT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -601,6 +1171,36 @@ pub mod VCNT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCNT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCNT_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -632,6 +1232,36 @@ pub mod VMVN_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_r_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -663,6 +1293,36 @@ pub mod VMVN_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMVN_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMVN_r_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -694,6 +1354,42 @@ pub mod VPADAL_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADAL_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADAL_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -728,6 +1424,42 @@ pub mod VPADAL_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VPADAL_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VPADAL_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -762,6 +1494,36 @@ pub mod VQABS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQABS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQABS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -793,6 +1555,36 @@ pub mod VQABS_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQABS_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQABS_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -824,6 +1616,36 @@ pub mod VQNEG_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQNEG_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQNEG_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -855,6 +1677,36 @@ pub mod VQNEG_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQNEG_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQNEG_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -886,6 +1738,42 @@ pub mod VCGT_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -920,6 +1808,42 @@ pub mod VCGT_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGT_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGT_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -954,6 +1878,42 @@ pub mod VCGE_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -988,6 +1948,42 @@ pub mod VCGE_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCGE_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCGE_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1022,6 +2018,42 @@ pub mod VCEQ_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1056,6 +2088,42 @@ pub mod VCEQ_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCEQ_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCEQ_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1090,6 +2158,42 @@ pub mod VCLE_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLE_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLE_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1124,6 +2228,42 @@ pub mod VCLE_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLE_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLE_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1158,6 +2298,42 @@ pub mod VCLT_i_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLT_i_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLT_i_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1192,6 +2368,42 @@ pub mod VCLT_i_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCLT_i_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCLT_i_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1226,6 +2438,42 @@ pub mod VABS_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABS_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1260,6 +2508,42 @@ pub mod VABS_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABS_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VABS_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1294,6 +2578,42 @@ pub mod VNEG_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNEG_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1328,6 +2648,42 @@ pub mod VNEG_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VNEG_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 10u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VNEG_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1362,6 +2718,36 @@ pub mod SHA1H_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1H_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1H_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1393,6 +2779,30 @@ pub mod VCVT_bfs_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_bfs_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_bfs_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1421,6 +2831,36 @@ pub mod VTRN_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTRN_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTRN_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1452,6 +2892,36 @@ pub mod VTRN_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTRN_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTRN_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1483,6 +2953,36 @@ pub mod VUZP_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUZP_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUZP_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1514,6 +3014,36 @@ pub mod VUZP_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VUZP_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VUZP_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1545,6 +3075,36 @@ pub mod VZIP_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VZIP_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VZIP_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1576,6 +3136,36 @@ pub mod VZIP_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VZIP_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VZIP_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1607,6 +3197,36 @@ pub mod VMOVN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOVN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMOVN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1638,6 +3258,42 @@ pub mod VQMOVN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQMOVN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQMOVN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1671,6 +3327,36 @@ pub mod VQMOVUN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQMOVUN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQMOVUN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1702,6 +3388,36 @@ pub mod VSHLL_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSHLL_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSHLL_T2( D: ::aarchmrs_types::BitValue<1>, @@ -1733,6 +3449,36 @@ pub mod SHA1SU1_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA1SU1_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA1SU1_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1764,6 +3510,36 @@ pub mod SHA256SU0_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHA256SU0_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn SHA256SU0_T1( D: ::aarchmrs_types::BitValue<1>, @@ -1795,6 +3571,36 @@ pub mod VRINTN_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1826,6 +3632,36 @@ pub mod VRINTN_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTN_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTN_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1857,6 +3693,36 @@ pub mod VRINTX_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTX_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1888,6 +3754,36 @@ pub mod VRINTX_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTX_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTX_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1919,6 +3815,36 @@ pub mod VRINTA_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -1950,6 +3876,36 @@ pub mod VRINTA_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTA_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTA_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -1981,6 +3937,36 @@ pub mod VRINTZ_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTZ_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2012,6 +3998,36 @@ pub mod VRINTZ_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTZ_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTZ_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2043,6 +4059,36 @@ pub mod VCVT_sh_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_sh_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_sh_T1( D: ::aarchmrs_types::BitValue<1>, @@ -2074,6 +4120,36 @@ pub mod VCVT_hs_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_hs_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_hs_T1( D: ::aarchmrs_types::BitValue<1>, @@ -2105,6 +4181,36 @@ pub mod VRINTM_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2136,6 +4242,36 @@ pub mod VRINTM_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTM_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTM_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2167,6 +4303,36 @@ pub mod VRINTP_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2198,6 +4364,36 @@ pub mod VRINTP_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRINTP_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRINTP_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2229,6 +4425,42 @@ pub mod VCVTA_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2263,6 +4495,42 @@ pub mod VCVTA_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTA_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTA_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2297,6 +4565,42 @@ pub mod VCVTN_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2331,6 +4635,42 @@ pub mod VCVTN_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTN_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTN_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2365,6 +4705,42 @@ pub mod VCVTP_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2399,6 +4775,42 @@ pub mod VCVTP_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTP_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTP_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2433,6 +4845,42 @@ pub mod VCVTM_asimd_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_asimd_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_asimd_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2467,6 +4915,42 @@ pub mod VCVTM_asimd_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVTM_asimd_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVTM_asimd_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2501,6 +4985,42 @@ pub mod VRECPE_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPE_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPE_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2535,6 +5055,42 @@ pub mod VRECPE_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRECPE_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRECPE_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2569,6 +5125,42 @@ pub mod VRSQRTE_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTE_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTE_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2603,6 +5195,42 @@ pub mod VRSQRTE_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSQRTE_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSQRTE_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -2637,6 +5265,42 @@ pub mod VCVT_is_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_is_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_is_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -2671,6 +5335,42 @@ pub mod VCVT_is_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VCVT_is_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 18u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VCVT_is_T1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_sc.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_sc.rs index cb706ce0..5ad5b49d 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_sc.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_2r_sc.rs @@ -12,6 +12,54 @@ pub mod VMLA_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -48,6 +96,54 @@ pub mod VMLA_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLA_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLA_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -84,6 +180,48 @@ pub mod VQDMLAL_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLAL_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLAL_T2( D: ::aarchmrs_types::BitValue<1>, @@ -118,6 +256,54 @@ pub mod VMLAL_s_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLAL_s_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLAL_s_T1( U: ::aarchmrs_types::BitValue<1>, @@ -155,6 +341,48 @@ pub mod VQDMLSL_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLSL_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLSL_T2( D: ::aarchmrs_types::BitValue<1>, @@ -189,6 +417,54 @@ pub mod VMLS_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -225,6 +501,54 @@ pub mod VMLS_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLS_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMLS_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -261,6 +585,48 @@ pub mod VQDMULL_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULL_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULL_T2( D: ::aarchmrs_types::BitValue<1>, @@ -295,6 +661,54 @@ pub mod VMLSL_s_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLSL_s_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLSL_s_T1( U: ::aarchmrs_types::BitValue<1>, @@ -332,6 +746,54 @@ pub mod VMUL_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -368,6 +830,54 @@ pub mod VMUL_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMUL_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_F_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VMUL_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, @@ -404,6 +914,54 @@ pub mod VMULL_s_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMULL_s_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMULL_s_T1( U: ::aarchmrs_types::BitValue<1>, @@ -441,6 +999,48 @@ pub mod VQDMULH_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -475,6 +1075,48 @@ pub mod VQDMULH_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULH_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULH_T2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -509,6 +1151,48 @@ pub mod VQRDMULH_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -543,6 +1227,48 @@ pub mod VQRDMULH_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMULH_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMULH_T2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -577,6 +1303,48 @@ pub mod VQRDMLAH_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -611,6 +1379,48 @@ pub mod VQRDMLAH_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLAH_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLAH_T2_Q( D: ::aarchmrs_types::BitValue<1>, @@ -645,6 +1455,48 @@ pub mod VQRDMLSH_T2_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_T2_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_T2_D( D: ::aarchmrs_types::BitValue<1>, @@ -679,6 +1531,48 @@ pub mod VQRDMLSH_T2_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQRDMLSH_T2_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQRDMLSH_T2_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_3diff.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_3diff.rs index fd611069..17c15e76 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_3diff.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_3diff.rs @@ -12,6 +12,54 @@ pub mod VADDL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADDL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VADDL_T1( U: ::aarchmrs_types::BitValue<1>, @@ -49,6 +97,54 @@ pub mod VADDW_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADDW_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VADDW_T1( U: ::aarchmrs_types::BitValue<1>, @@ -86,6 +182,54 @@ pub mod VSUBL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUBL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSUBL_T1( U: ::aarchmrs_types::BitValue<1>, @@ -123,6 +267,48 @@ pub mod VADDHN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VADDHN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VADDHN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -157,6 +343,54 @@ pub mod VSUBW_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUBW_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSUBW_T1( U: ::aarchmrs_types::BitValue<1>, @@ -194,6 +428,48 @@ pub mod VSUBHN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSUBHN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSUBHN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -228,6 +504,48 @@ pub mod VQDMLAL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLAL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLAL_T1( D: ::aarchmrs_types::BitValue<1>, @@ -262,6 +580,54 @@ pub mod VABAL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABAL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABAL_T1( U: ::aarchmrs_types::BitValue<1>, @@ -299,6 +665,48 @@ pub mod VQDMLSL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMLSL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMLSL_T1( D: ::aarchmrs_types::BitValue<1>, @@ -333,6 +741,48 @@ pub mod VQDMULL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VQDMULL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VQDMULL_T1( D: ::aarchmrs_types::BitValue<1>, @@ -367,6 +817,54 @@ pub mod VABDL_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VABDL_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VABDL_i_T1( U: ::aarchmrs_types::BitValue<1>, @@ -404,6 +902,54 @@ pub mod VMLAL_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLAL_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLAL_i_T1( U: ::aarchmrs_types::BitValue<1>, @@ -441,6 +987,54 @@ pub mod VMLSL_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMLSL_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMLSL_i_T1( U: ::aarchmrs_types::BitValue<1>, @@ -478,6 +1072,48 @@ pub mod VRADDHN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRADDHN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRADDHN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -512,6 +1148,48 @@ pub mod VRSUBHN_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VRSUBHN_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VRSUBHN_T1( D: ::aarchmrs_types::BitValue<1>, @@ -546,6 +1224,60 @@ pub mod VMULL_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMULL_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_op_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 20u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 28u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMULL_i_T1( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_dup_sc.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_dup_sc.rs index d802d53f..1b301783 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_dup_sc.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_dup_sc.rs @@ -12,6 +12,36 @@ pub mod VDUP_s_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_s_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDUP_s_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -42,6 +72,36 @@ pub mod VDUP_s_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_s_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VDUP_s_T1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_ext.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_ext.rs index c9039cb8..bb8f5e03 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_ext.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_ext.rs @@ -12,6 +12,48 @@ pub mod VEXT_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEXT_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEXT_T1_D( D: ::aarchmrs_types::BitValue<1>, @@ -46,6 +88,48 @@ pub mod VEXT_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VEXT_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VEXT_T1_Q( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_tbl.rs b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_tbl.rs index 9ccc9091..123f0a40 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_tbl.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/simddp/t_simd_mulreg/simd_tbl.rs @@ -12,6 +12,48 @@ pub mod VTBL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTBL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTBL_T1( D: ::aarchmrs_types::BitValue<1>, @@ -47,6 +89,48 @@ pub mod VTBX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VTBX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_len_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VTBX_T1( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/cp_mov32.rs b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/cp_mov32.rs index 0304ea04..9a1f0784 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/cp_mov32.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/cp_mov32.rs @@ -12,6 +12,42 @@ pub mod MCR_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MCR_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 3u32; #[inline] pub const fn MCR_T1( opc1: ::aarchmrs_types::BitValue<3>, @@ -44,6 +80,42 @@ pub mod MRC_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRC_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 3u32; #[inline] pub const fn MRC_T1( opc1: ::aarchmrs_types::BitValue<3>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov16.rs b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov16.rs index ef99a7f0..47279d90 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov16.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov16.rs @@ -12,6 +12,24 @@ pub mod VMOV_toh_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_toh_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_toh_T1( Vn: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,24 @@ pub mod VMOV_h_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_h_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_h_T1( Vn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov32.rs b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov32.rs index 1decddde..78b5d818 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov32.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_mov32.rs @@ -12,6 +12,24 @@ pub mod VMOV_tos_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_tos_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_tos_T1( Vn: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,24 @@ pub mod VMOV_s_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_s_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_s_T1( Vn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_msr.rs b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_msr.rs index c7ef6a05..6f61da3a 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_msr.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/fp_msr.rs @@ -12,6 +12,18 @@ pub mod VMSR_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000011101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMSR_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_WIDTH: u32 = 4u32; #[inline] pub const fn VMSR_T1_AS( reg: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod VMRS_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000011101111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMRS_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_reg_WIDTH: u32 = 4u32; #[inline] pub const fn VMRS_T1_AS( reg: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/simd_dup_el.rs b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/simd_dup_el.rs index 34eba337..7879fca8 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/simd_dup_el.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sys_mov32/simd_dup_el.rs @@ -12,6 +12,36 @@ pub mod VMOV_rs_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_rs_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 2u32; #[inline] pub const fn VMOV_rs_T1( opc1: ::aarchmrs_types::BitValue<2>, @@ -42,6 +72,42 @@ pub mod VMOV_sr_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_sr_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_N_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VMOV_sr_T1( U: ::aarchmrs_types::BitValue<1>, @@ -74,6 +140,36 @@ pub mod VDUP_r_T1_Q { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_r_T1_Q"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_WIDTH: u32 = 1u32; #[inline] pub const fn VDUP_r_T1_Q( B: ::aarchmrs_types::BitValue<1>, @@ -105,6 +201,36 @@ pub mod VDUP_r_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "VDUP_r_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_E_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_B_WIDTH: u32 = 1u32; #[inline] pub const fn VDUP_r_T1_D( B: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_ldst.rs b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_ldst.rs index ba3b9c97..64454a3b 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_ldst.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_ldst.rs @@ -12,6 +12,30 @@ pub mod LDC_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; #[inline] pub const fn LDC_l_T1( P: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,24 @@ pub mod STC_T1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_T1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn STC_T1_off( U: ::aarchmrs_types::BitValue<1>, @@ -64,6 +106,24 @@ pub mod STC_T1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_T1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn STC_T1_post( U: ::aarchmrs_types::BitValue<1>, @@ -89,6 +149,24 @@ pub mod STC_T1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_T1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn STC_T1_pre( U: ::aarchmrs_types::BitValue<1>, @@ -114,6 +192,18 @@ pub mod STC_T1_unind { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STC_T1_unind"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STC_T1_unind( Rn: ::aarchmrs_types::BitValue<4>, @@ -136,6 +226,24 @@ pub mod LDC_i_T1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_T1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDC_i_T1_off( U: ::aarchmrs_types::BitValue<1>, @@ -161,6 +269,24 @@ pub mod LDC_i_T1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_T1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDC_i_T1_post( U: ::aarchmrs_types::BitValue<1>, @@ -186,6 +312,24 @@ pub mod LDC_i_T1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_T1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDC_i_T1_pre( U: ::aarchmrs_types::BitValue<1>, @@ -211,6 +355,18 @@ pub mod LDC_i_T1_unind { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDC_i_T1_unind"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDC_i_T1_unind( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_mov64.rs b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_mov64.rs index 0d0d3946..47f85c3c 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_mov64.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/cp_mov64.rs @@ -12,6 +12,36 @@ pub mod MCRR_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MCRR_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; #[inline] pub const fn MCRR_T1( Rt2: ::aarchmrs_types::BitValue<4>, @@ -40,6 +70,36 @@ pub mod MRRC_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MRRC_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_CRm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_opc1_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_cp15_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; #[inline] pub const fn MRRC_T1( Rt2: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_ldst.rs b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_ldst.rs index 86c28058..26531e83 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_ldst.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_ldst.rs @@ -12,6 +12,30 @@ pub mod VSTMDB_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTMDB_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSTMDB_T2( D: ::aarchmrs_types::BitValue<1>, @@ -39,6 +63,36 @@ pub mod VSTM_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTM_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSTM_T2( D: ::aarchmrs_types::BitValue<1>, @@ -68,6 +122,30 @@ pub mod VSTMDB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTMDB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSTMDB_T1( D: ::aarchmrs_types::BitValue<1>, @@ -96,6 +174,36 @@ pub mod VSTM_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTM_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VSTM_T1( D: ::aarchmrs_types::BitValue<1>, @@ -126,6 +234,30 @@ pub mod FSTMDBX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSTMDBX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn FSTMDBX_T1( D: ::aarchmrs_types::BitValue<1>, @@ -154,6 +286,36 @@ pub mod FSTMIAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FSTMIAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn FSTMIAX_T1( D: ::aarchmrs_types::BitValue<1>, @@ -184,6 +346,30 @@ pub mod VLDMDB_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDMDB_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLDMDB_T2( D: ::aarchmrs_types::BitValue<1>, @@ -211,6 +397,36 @@ pub mod VLDM_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDM_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLDM_T2( D: ::aarchmrs_types::BitValue<1>, @@ -240,6 +456,30 @@ pub mod VLDMDB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDMDB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLDMDB_T1( D: ::aarchmrs_types::BitValue<1>, @@ -268,6 +508,36 @@ pub mod VLDM_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDM_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLDM_T1( D: ::aarchmrs_types::BitValue<1>, @@ -298,6 +568,30 @@ pub mod FLDMDBX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FLDMDBX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn FLDMDBX_T1( D: ::aarchmrs_types::BitValue<1>, @@ -326,6 +620,36 @@ pub mod FLDMIAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "FLDMIAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 7u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn FLDMIAX_T1( D: ::aarchmrs_types::BitValue<1>, @@ -356,6 +680,36 @@ pub mod VSTR_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTR_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSTR_T1_H( U: ::aarchmrs_types::BitValue<1>, @@ -385,6 +739,36 @@ pub mod VSTR_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTR_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSTR_T1_S( U: ::aarchmrs_types::BitValue<1>, @@ -414,6 +798,36 @@ pub mod VSTR_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VSTR_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VSTR_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -443,6 +857,36 @@ pub mod VLDR_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VLDR_T1_H( U: ::aarchmrs_types::BitValue<1>, @@ -472,6 +916,36 @@ pub mod VLDR_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VLDR_T1_S( U: ::aarchmrs_types::BitValue<1>, @@ -501,6 +975,36 @@ pub mod VLDR_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VLDR_T1_D( U: ::aarchmrs_types::BitValue<1>, @@ -530,6 +1034,30 @@ pub mod VLDR_l_T1_H { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_l_T1_H"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VLDR_l_T1_H( U: ::aarchmrs_types::BitValue<1>, @@ -557,6 +1085,30 @@ pub mod VLDR_l_T1_S { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_l_T1_S"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VLDR_l_T1_S( U: ::aarchmrs_types::BitValue<1>, @@ -584,6 +1136,30 @@ pub mod VLDR_l_T1_D { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLDR_l_T1_D"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn VLDR_l_T1_D( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_mov64.rs b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_mov64.rs index ef6a3aef..888d6f22 100644 --- a/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_mov64.rs +++ b/aarchmrs-instructions/src/T32/w/cpaf/sysldst_mov64/simdfp_mov64.rs @@ -12,6 +12,30 @@ pub mod VMOV_toss_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_toss_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_toss_T1( Rt2: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod VMOV_ss_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_ss_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_ss_T1( Rt2: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,30 @@ pub mod VMOV_tod_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_tod_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_tod_T1( Rt2: ::aarchmrs_types::BitValue<4>, @@ -93,6 +165,30 @@ pub mod VMOV_d_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VMOV_d_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; #[inline] pub const fn VMOV_d_T1( Rt2: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/dpint_immm.rs b/aarchmrs-instructions/src/T32/w/dpint_immm.rs index cd28c396..7ddda74b 100644 --- a/aarchmrs-instructions/src/T32/w/dpint_immm.rs +++ b/aarchmrs-instructions/src/T32/w/dpint_immm.rs @@ -12,6 +12,36 @@ pub mod AND_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn AND_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod ANDS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ANDS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -70,6 +130,30 @@ pub mod TST_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn TST_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -98,6 +182,36 @@ pub mod BIC_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn BIC_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -127,6 +241,36 @@ pub mod BICS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn BICS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -156,6 +300,36 @@ pub mod ORR_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ORR_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -185,6 +359,36 @@ pub mod ORRS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORRS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ORRS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -214,6 +418,30 @@ pub mod MOV_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn MOV_i_T2( i: ::aarchmrs_types::BitValue<1>, @@ -240,6 +468,30 @@ pub mod MOVS_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn MOVS_i_T2( i: ::aarchmrs_types::BitValue<1>, @@ -266,6 +518,36 @@ pub mod ORNS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORNS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ORNS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -295,6 +577,36 @@ pub mod ORN_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORN_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ORN_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -324,6 +636,30 @@ pub mod MVN_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn MVN_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -350,6 +686,30 @@ pub mod MVNS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn MVNS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -376,6 +736,36 @@ pub mod EOR_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn EOR_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -405,6 +795,36 @@ pub mod EORS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EORS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn EORS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -434,6 +854,30 @@ pub mod TEQ_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEQ_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn TEQ_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -462,6 +906,36 @@ pub mod ADD_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -491,6 +965,36 @@ pub mod ADDS_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADDS_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -520,6 +1024,30 @@ pub mod ADD_SP_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_SP_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -546,6 +1074,30 @@ pub mod ADDS_SP_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_SP_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADDS_SP_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -572,6 +1124,30 @@ pub mod CMN_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn CMN_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -600,6 +1176,36 @@ pub mod ADC_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADC_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -629,6 +1235,36 @@ pub mod ADCS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADCS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -658,6 +1294,36 @@ pub mod SBC_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SBC_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -687,6 +1353,36 @@ pub mod SBCS_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SBCS_i_T1( i: ::aarchmrs_types::BitValue<1>, @@ -716,6 +1412,36 @@ pub mod SUB_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SUB_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -745,6 +1471,36 @@ pub mod SUBS_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SUBS_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -774,6 +1530,30 @@ pub mod SUB_SP_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SUB_SP_i_T2( i: ::aarchmrs_types::BitValue<1>, @@ -800,6 +1580,30 @@ pub mod SUBS_SP_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_SP_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SUBS_SP_i_T2( i: ::aarchmrs_types::BitValue<1>, @@ -826,6 +1630,30 @@ pub mod CMP_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn CMP_i_T2( i: ::aarchmrs_types::BitValue<1>, @@ -854,6 +1682,36 @@ pub mod RSB_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn RSB_i_T2( i: ::aarchmrs_types::BitValue<1>, @@ -883,6 +1741,36 @@ pub mod RSBS_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSBS_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn RSBS_i_T2( i: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/dpint_shiftr.rs b/aarchmrs-instructions/src/T32/w/dpint_shiftr.rs index cc5851da..af20e682 100644 --- a/aarchmrs-instructions/src/T32/w/dpint_shiftr.rs +++ b/aarchmrs-instructions/src/T32/w/dpint_shiftr.rs @@ -12,6 +12,24 @@ pub mod AND_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn AND_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,42 @@ pub mod AND_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "AND_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn AND_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -67,6 +121,24 @@ pub mod ANDS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ANDS_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -92,6 +164,42 @@ pub mod ANDS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ANDS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ANDS_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -122,6 +230,18 @@ pub mod TST_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn TST_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -144,6 +264,36 @@ pub mod TST_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TST_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn TST_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -173,6 +323,24 @@ pub mod BIC_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn BIC_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -198,6 +366,42 @@ pub mod BIC_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BIC_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn BIC_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -228,6 +432,24 @@ pub mod BICS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn BICS_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -253,6 +475,42 @@ pub mod BICS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BICS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn BICS_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -283,6 +541,24 @@ pub mod ORR_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORR_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -308,6 +584,42 @@ pub mod ORR_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORR_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORR_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -338,6 +650,24 @@ pub mod ORRS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORRS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORRS_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -363,6 +693,42 @@ pub mod ORRS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORRS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORRS_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -393,6 +759,18 @@ pub mod MOV_r_T3_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_r_T3_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn MOV_r_T3_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -415,6 +793,36 @@ pub mod MOV_r_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_r_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn MOV_r_T3( imm3: ::aarchmrs_types::BitValue<3>, @@ -442,6 +850,18 @@ pub mod MOVS_r_T3_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_r_T3_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn MOVS_r_T3_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -464,6 +884,36 @@ pub mod MOVS_r_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_r_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn MOVS_r_T3( imm3: ::aarchmrs_types::BitValue<3>, @@ -491,6 +941,24 @@ pub mod ORN_r_T1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORN_r_T1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORN_r_T1_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -516,6 +984,42 @@ pub mod ORN_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORN_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORN_r_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -546,6 +1050,24 @@ pub mod ORNS_r_T1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORNS_r_T1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORNS_r_T1_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -571,6 +1093,42 @@ pub mod ORNS_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ORNS_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ORNS_r_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -601,6 +1159,18 @@ pub mod MVN_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn MVN_r_T2_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -623,6 +1193,36 @@ pub mod MVN_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVN_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn MVN_r_T2( imm3: ::aarchmrs_types::BitValue<3>, @@ -650,6 +1250,18 @@ pub mod MVNS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn MVNS_r_T2_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -672,6 +1284,36 @@ pub mod MVNS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MVNS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn MVNS_r_T2( imm3: ::aarchmrs_types::BitValue<3>, @@ -699,6 +1341,24 @@ pub mod EOR_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn EOR_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -724,6 +1384,42 @@ pub mod EOR_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EOR_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn EOR_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -754,6 +1450,24 @@ pub mod EORS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EORS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn EORS_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -779,6 +1493,42 @@ pub mod EORS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "EORS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn EORS_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -809,6 +1559,18 @@ pub mod TEQ_r_T1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEQ_r_T1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn TEQ_r_T1_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -831,6 +1593,36 @@ pub mod TEQ_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TEQ_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn TEQ_r_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -860,6 +1652,36 @@ pub mod PKHBT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PKHBT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PKHBT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -889,6 +1711,36 @@ pub mod PKHTB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PKHTB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PKHTB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -918,6 +1770,24 @@ pub mod ADD_r_T3_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_r_T3_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_r_T3_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -943,6 +1813,42 @@ pub mod ADD_r_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_r_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_r_T3( Rn: ::aarchmrs_types::BitValue<4>, @@ -973,6 +1879,24 @@ pub mod ADDS_r_T3_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_r_T3_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_r_T3_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -998,6 +1922,42 @@ pub mod ADDS_r_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_r_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_r_T3( Rn: ::aarchmrs_types::BitValue<4>, @@ -1028,6 +1988,18 @@ pub mod ADD_SP_r_T3_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_r_T3_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn ADD_SP_r_T3_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -1050,6 +2022,36 @@ pub mod ADD_SP_r_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_r_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn ADD_SP_r_T3( imm3: ::aarchmrs_types::BitValue<3>, @@ -1077,6 +2079,18 @@ pub mod ADDS_SP_r_T3_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_SP_r_T3_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn ADDS_SP_r_T3_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -1099,6 +2113,36 @@ pub mod ADDS_SP_r_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADDS_SP_r_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn ADDS_SP_r_T3( imm3: ::aarchmrs_types::BitValue<3>, @@ -1126,6 +2170,18 @@ pub mod CMN_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CMN_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1148,6 +2204,36 @@ pub mod CMN_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMN_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CMN_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -1177,6 +2263,24 @@ pub mod ADC_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADC_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1202,6 +2306,42 @@ pub mod ADC_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADC_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADC_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -1232,6 +2372,24 @@ pub mod ADCS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADCS_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1257,6 +2415,42 @@ pub mod ADCS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADCS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn ADCS_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -1287,6 +2481,24 @@ pub mod SBC_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SBC_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1312,6 +2524,42 @@ pub mod SBC_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBC_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SBC_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -1342,6 +2590,24 @@ pub mod SBCS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SBCS_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1367,6 +2633,42 @@ pub mod SBCS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBCS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SBCS_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -1397,6 +2699,24 @@ pub mod SUB_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1422,6 +2742,42 @@ pub mod SUB_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -1452,6 +2808,24 @@ pub mod SUBS_r_T2_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_r_T2_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_r_T2_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1477,6 +2851,42 @@ pub mod SUBS_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -1507,6 +2917,18 @@ pub mod SUB_SP_r_T1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_r_T1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn SUB_SP_r_T1_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -1529,6 +2951,36 @@ pub mod SUB_SP_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn SUB_SP_r_T1( imm3: ::aarchmrs_types::BitValue<3>, @@ -1556,6 +3008,18 @@ pub mod SUBS_SP_r_T1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_SP_r_T1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn SUBS_SP_r_T1_RRX( Rd: ::aarchmrs_types::BitValue<4>, @@ -1578,6 +3042,36 @@ pub mod SUBS_SP_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUBS_SP_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn SUBS_SP_r_T1( imm3: ::aarchmrs_types::BitValue<3>, @@ -1605,6 +3099,18 @@ pub mod CMP_r_T3_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_r_T3_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CMP_r_T3_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1627,6 +3133,36 @@ pub mod CMP_r_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CMP_r_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CMP_r_T3( Rn: ::aarchmrs_types::BitValue<4>, @@ -1656,6 +3192,24 @@ pub mod RSB_r_T1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_r_T1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn RSB_r_T1_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1681,6 +3235,42 @@ pub mod RSB_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSB_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn RSB_r_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -1711,6 +3301,24 @@ pub mod RSBS_r_T1_RRX { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSBS_r_T1_RRX"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn RSBS_r_T1_RRX( Rn: ::aarchmrs_types::BitValue<4>, @@ -1736,6 +3344,42 @@ pub mod RSBS_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RSBS_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn RSBS_r_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/ldastl.rs b/aarchmrs-instructions/src/T32/w/dstd/ldastl.rs index 912737b8..6956ff15 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/ldastl.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/ldastl.rs @@ -12,6 +12,18 @@ pub mod STLB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STLB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod STLH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STLH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -56,6 +80,18 @@ pub mod STL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "STL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STL_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -78,6 +114,24 @@ pub mod STLEXB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEXB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STLEXB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -102,6 +156,24 @@ pub mod STLEXH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEXH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STLEXH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -126,6 +198,24 @@ pub mod STLEX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STLEX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -150,6 +240,30 @@ pub mod STLEXD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STLEXD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STLEXD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -176,6 +290,18 @@ pub mod LDAB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDAB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -198,6 +324,18 @@ pub mod LDAH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDAH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -220,6 +358,18 @@ pub mod LDA_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDA_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDA_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -242,6 +392,18 @@ pub mod LDAEXB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEXB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEXB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -264,6 +426,18 @@ pub mod LDAEXH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEXH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEXH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -286,6 +460,18 @@ pub mod LDAEX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -308,6 +494,24 @@ pub mod LDAEXD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDAEXD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDAEXD_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/lddlit.rs b/aarchmrs-instructions/src/T32/w/dstd/lddlit.rs index 173098b8..fac42f60 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/lddlit.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/lddlit.rs @@ -12,6 +12,42 @@ pub mod LDRD_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 24u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; #[inline] pub const fn LDRD_l_T1( P: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/ldstd_imm.rs b/aarchmrs-instructions/src/T32/w/dstd/ldstd_imm.rs index 3ff524b5..8160a87a 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/ldstd_imm.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/ldstd_imm.rs @@ -12,6 +12,36 @@ pub mod STRD_i_T1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_i_T1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn STRD_i_T1_off( U: ::aarchmrs_types::BitValue<1>, @@ -40,6 +70,36 @@ pub mod LDRD_i_T1_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_i_T1_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDRD_i_T1_off( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/ldstd_post.rs b/aarchmrs-instructions/src/T32/w/dstd/ldstd_post.rs index 38168edc..dda3c3b3 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/ldstd_post.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/ldstd_post.rs @@ -12,6 +12,36 @@ pub mod STRD_i_T1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_i_T1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn STRD_i_T1_post( U: ::aarchmrs_types::BitValue<1>, @@ -40,6 +70,36 @@ pub mod LDRD_i_T1_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_i_T1_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDRD_i_T1_post( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/ldstd_pre.rs b/aarchmrs-instructions/src/T32/w/dstd/ldstd_pre.rs index c94f0ba2..e9444969 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/ldstd_pre.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/ldstd_pre.rs @@ -12,6 +12,36 @@ pub mod STRD_i_T1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRD_i_T1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn STRD_i_T1_pre( U: ::aarchmrs_types::BitValue<1>, @@ -40,6 +70,36 @@ pub mod LDRD_i_T1_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRD_i_T1_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDRD_i_T1_pre( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/ldstex.rs b/aarchmrs-instructions/src/T32/w/dstd/ldstex.rs index 83d0f17f..4ae796d7 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/ldstex.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/ldstex.rs @@ -12,6 +12,30 @@ pub mod STREX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STREX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -37,6 +61,24 @@ pub mod LDREX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDREX_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/ldstex_bhd.rs b/aarchmrs-instructions/src/T32/w/dstd/ldstex_bhd.rs index e8de6b25..bfb5170b 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/ldstex_bhd.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/ldstex_bhd.rs @@ -12,6 +12,24 @@ pub mod STREXB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREXB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STREXB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod STREXH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREXH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STREXH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,30 @@ pub mod STREXD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STREXD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STREXD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -86,6 +146,18 @@ pub mod LDREXB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREXB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDREXB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -108,6 +180,18 @@ pub mod LDREXH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREXH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDREXH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -130,6 +214,24 @@ pub mod LDREXD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000001111u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDREXD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt2_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDREXD_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/dstd/tblbr.rs b/aarchmrs-instructions/src/T32/w/dstd/tblbr.rs index 21ecbd1a..01534bc2 100644 --- a/aarchmrs-instructions/src/T32/w/dstd/tblbr.rs +++ b/aarchmrs-instructions/src/T32/w/dstd/tblbr.rs @@ -12,6 +12,18 @@ pub mod TBB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn TBB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -34,6 +46,18 @@ pub mod TBH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111100000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "TBH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn TBH_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/imm/dpint_imms.rs b/aarchmrs-instructions/src/T32/w/imm/dpint_imms.rs index f266de3c..41fce003 100644 --- a/aarchmrs-instructions/src/T32/w/imm/dpint_imms.rs +++ b/aarchmrs-instructions/src/T32/w/imm/dpint_imms.rs @@ -12,6 +12,36 @@ pub mod ADD_i_T4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_i_T4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_i_T4( i: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,30 @@ pub mod ADD_SP_i_T4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADD_SP_i_T4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADD_SP_i_T4( i: ::aarchmrs_types::BitValue<1>, @@ -67,6 +121,30 @@ pub mod ADR_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADR_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADR_T3( i: ::aarchmrs_types::BitValue<1>, @@ -93,6 +171,36 @@ pub mod SUB_i_T4 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_i_T4"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SUB_i_T4( i: ::aarchmrs_types::BitValue<1>, @@ -122,6 +230,30 @@ pub mod SUB_SP_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SUB_SP_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn SUB_SP_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -148,6 +280,30 @@ pub mod ADR_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "ADR_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn ADR_T2( i: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/imm/movw.rs b/aarchmrs-instructions/src/T32/w/imm/movw.rs index 2b7047f5..43c4fa33 100644 --- a/aarchmrs-instructions/src/T32/w/imm/movw.rs +++ b/aarchmrs-instructions/src/T32/w/imm/movw.rs @@ -12,6 +12,36 @@ pub mod MOV_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn MOV_i_T3( i: ::aarchmrs_types::BitValue<1>, @@ -41,6 +71,36 @@ pub mod MOVT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm4_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_OFFSET: u32 = 26u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_i_WIDTH: u32 = 1u32; #[inline] pub const fn MOVT_T1( i: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/imm/sat_bit.rs b/aarchmrs-instructions/src/T32/w/imm/sat_bit.rs index 2ff67677..6a34f9bf 100644 --- a/aarchmrs-instructions/src/T32/w/imm/sat_bit.rs +++ b/aarchmrs-instructions/src/T32/w/imm/sat_bit.rs @@ -12,6 +12,36 @@ pub mod SSAT_T1_ASR { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAT_T1_ASR"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SSAT_T1_ASR( Rn: ::aarchmrs_types::BitValue<4>, @@ -41,6 +71,36 @@ pub mod SSAT_T1_LSL { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAT_T1_LSL"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SSAT_T1_LSL( Rn: ::aarchmrs_types::BitValue<4>, @@ -70,6 +130,24 @@ pub mod SSAT16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000110000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAT16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SSAT16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -95,6 +173,36 @@ pub mod SBFX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SBFX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SBFX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -124,6 +232,36 @@ pub mod BFI_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFI_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn BFI_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -153,6 +291,30 @@ pub mod BFC_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "BFC_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_msb_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; #[inline] pub const fn BFC_T1( imm3: ::aarchmrs_types::BitValue<3>, @@ -179,6 +341,36 @@ pub mod USAT_T1_ASR { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAT_T1_ASR"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USAT_T1_ASR( Rn: ::aarchmrs_types::BitValue<4>, @@ -208,6 +400,36 @@ pub mod USAT_T1_LSL { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAT_T1_LSL"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USAT_T1_LSL( Rn: ::aarchmrs_types::BitValue<4>, @@ -237,6 +459,24 @@ pub mod USAT16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000110000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAT16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_sat_imm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USAT16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -262,6 +502,36 @@ pub mod UBFX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000100000000000000000000100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UBFX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_widthm1_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm3_WIDTH: u32 = 3u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UBFX_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldlit_signed.rs b/aarchmrs-instructions/src/T32/w/ldst/ldlit_signed.rs index d52c2cbe..6360f3e2 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldlit_signed.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldlit_signed.rs @@ -13,6 +13,24 @@ pub mod LDRSB_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDRSB_l_T1( U: ::aarchmrs_types::BitValue<1>, @@ -37,6 +55,18 @@ pub mod PLI_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLI_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLI_i_T3( U: ::aarchmrs_types::BitValue<1>, @@ -59,6 +89,24 @@ pub mod LDRSH_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDRSH_l_T1( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldlit_unsigned.rs b/aarchmrs-instructions/src/T32/w/ldst/ldlit_unsigned.rs index 2475b670..d8b09eec 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldlit_unsigned.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldlit_unsigned.rs @@ -12,6 +12,18 @@ pub mod PLD_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000001000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn PLD_l_T1( U: ::aarchmrs_types::BitValue<1>, @@ -34,6 +46,24 @@ pub mod LDRB_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDRB_l_T1( U: ::aarchmrs_types::BitValue<1>, @@ -58,6 +88,24 @@ pub mod LDRH_l_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_l_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDRH_l_T1( U: ::aarchmrs_types::BitValue<1>, @@ -82,6 +130,24 @@ pub mod LDR_l_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_l_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 23u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; #[inline] pub const fn LDR_l_T2( U: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_nimm.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_nimm.rs index dfa9c601..ddc7ad56 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_nimm.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_nimm.rs @@ -13,6 +13,24 @@ pub mod LDRSB_i_T2_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_i_T2_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_i_T2_off( Rn: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,18 @@ pub mod PLI_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLI_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLI_i_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -59,6 +89,24 @@ pub mod LDRSH_i_T2_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_i_T2_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_i_T2_off( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pimm.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pimm.rs index c47c42b3..b0e1dc92 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pimm.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pimm.rs @@ -13,6 +13,24 @@ pub mod LDRSB_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_i_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,18 @@ pub mod PLI_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLI_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLI_i_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -58,6 +88,24 @@ pub mod LDRSH_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_i_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_post.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_post.rs index 1965d461..e52004fa 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_post.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_post.rs @@ -12,6 +12,30 @@ pub mod LDRSB_i_T2_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_i_T2_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_i_T2_post( Rn: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod LDRSH_i_T2_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_i_T2_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_i_T2_post( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pre.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pre.rs index 2dc33640..2434482f 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pre.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_pre.rs @@ -12,6 +12,30 @@ pub mod LDRSB_i_T2_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_i_T2_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_i_T2_pre( Rn: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod LDRSH_i_T2_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_i_T2_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_i_T2_pre( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_reg.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_reg.rs index 2ed0647d..0258b8dd 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_reg.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_reg.rs @@ -13,6 +13,30 @@ pub mod LDRSB_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSB_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSB_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,24 @@ pub mod PLI_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLI_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLI_r_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -63,6 +105,30 @@ pub mod LDRSH_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSH_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSH_r_T2( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_unpriv.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_unpriv.rs index 6acd82d0..1f7dbb8b 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_unpriv.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_signed_unpriv.rs @@ -12,6 +12,24 @@ pub mod LDRSBT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSBT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSBT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod LDRSHT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRSHT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRSHT_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_nimm.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_nimm.rs index f65a2dd2..638a82f8 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_nimm.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_nimm.rs @@ -12,6 +12,24 @@ pub mod STRB_i_T3_offn { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_T3_offn"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_i_T3_offn( Rn: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod LDRB_i_T3_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_T3_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_i_T3_off( Rn: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,18 @@ pub mod PLD_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLD_i_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -82,6 +130,24 @@ pub mod STRH_i_T3_offn { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_T3_offn"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_i_T3_offn( Rn: ::aarchmrs_types::BitValue<4>, @@ -106,6 +172,24 @@ pub mod LDRH_i_T3_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_T3_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_i_T3_off( Rn: ::aarchmrs_types::BitValue<4>, @@ -130,6 +214,18 @@ pub mod PLDW_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLDW_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLDW_i_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -152,6 +248,24 @@ pub mod STR_i_T4_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_T4_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STR_i_T4_off( Rn: ::aarchmrs_types::BitValue<4>, @@ -176,6 +290,24 @@ pub mod LDR_i_T4_off { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_T4_off"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_i_T4_off( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pimm.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pimm.rs index f691ec7a..e09101c8 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pimm.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pimm.rs @@ -12,6 +12,24 @@ pub mod STRB_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_i_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -35,6 +53,24 @@ pub mod LDRB_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_i_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -58,6 +94,18 @@ pub mod PLD_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLD_i_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -80,6 +128,18 @@ pub mod PLDW_i_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLDW_i_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLDW_i_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -102,6 +162,24 @@ pub mod STRH_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_i_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -125,6 +203,24 @@ pub mod LDRH_i_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_i_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -148,6 +244,24 @@ pub mod STR_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STR_i_T3( Rn: ::aarchmrs_types::BitValue<4>, @@ -171,6 +285,24 @@ pub mod LDR_i_T3 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_T3"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm12_WIDTH: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_i_T3( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_post.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_post.rs index 28e17171..570218b6 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_post.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_post.rs @@ -12,6 +12,30 @@ pub mod STRB_i_T3_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_T3_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_i_T3_post( Rn: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod LDRB_i_T3_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_T3_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_i_T3_post( Rn: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,30 @@ pub mod STRH_i_T3_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_T3_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_i_T3_post( Rn: ::aarchmrs_types::BitValue<4>, @@ -93,6 +165,30 @@ pub mod LDRH_i_T3_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_T3_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_i_T3_post( Rn: ::aarchmrs_types::BitValue<4>, @@ -120,6 +216,30 @@ pub mod STR_i_T4_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_T4_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STR_i_T4_post( Rn: ::aarchmrs_types::BitValue<4>, @@ -147,6 +267,30 @@ pub mod LDR_i_T4_post { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_T4_post"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_i_T4_post( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pre.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pre.rs index f0d352ea..22e72cd8 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pre.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_pre.rs @@ -12,6 +12,30 @@ pub mod STRB_i_T3_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_i_T3_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_i_T3_pre( Rn: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,30 @@ pub mod LDRB_i_T3_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_i_T3_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_i_T3_pre( Rn: ::aarchmrs_types::BitValue<4>, @@ -66,6 +114,30 @@ pub mod STRH_i_T3_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_i_T3_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_i_T3_pre( Rn: ::aarchmrs_types::BitValue<4>, @@ -93,6 +165,30 @@ pub mod LDRH_i_T3_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_i_T3_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_i_T3_pre( Rn: ::aarchmrs_types::BitValue<4>, @@ -120,6 +216,30 @@ pub mod STR_i_T4_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_i_T4_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STR_i_T4_pre( Rn: ::aarchmrs_types::BitValue<4>, @@ -147,6 +267,30 @@ pub mod LDR_i_T4_pre { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_i_T4_pre"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_OFFSET: u32 = 9u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_U_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_i_T4_pre( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_reg.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_reg.rs index 719f496d..3a8c6b48 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_reg.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_reg.rs @@ -12,6 +12,30 @@ pub mod STRB_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRB_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRB_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod LDRB_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRB_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRB_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,24 @@ pub mod PLD_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLD_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLD_r_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -88,6 +154,24 @@ pub mod PLDW_r_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "PLDW_r_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn PLDW_r_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -112,6 +196,30 @@ pub mod STRH_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRH_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRH_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -138,6 +246,30 @@ pub mod LDRH_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRH_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRH_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -164,6 +296,30 @@ pub mod STR_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STR_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STR_r_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -190,6 +346,30 @@ pub mod LDR_r_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDR_r_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm2_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDR_r_T2( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_unpriv.rs b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_unpriv.rs index 61f0d1ee..1abaa9a5 100644 --- a/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_unpriv.rs +++ b/aarchmrs-instructions/src/T32/w/ldst/ldst_unsigned_unpriv.rs @@ -12,6 +12,24 @@ pub mod STRBT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRBT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRBT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -36,6 +54,24 @@ pub mod LDRBT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRBT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRBT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -60,6 +96,24 @@ pub mod STRHT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRHT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRHT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -84,6 +138,24 @@ pub mod LDRHT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRHT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRHT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -108,6 +180,24 @@ pub mod STRT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STRT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn STRT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -132,6 +222,24 @@ pub mod LDRT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDRT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_imm8_WIDTH: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rt_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn LDRT_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/ldstm.rs b/aarchmrs-instructions/src/T32/w/ldstm.rs index de23683f..964c07a8 100644 --- a/aarchmrs-instructions/src/T32/w/ldstm.rs +++ b/aarchmrs-instructions/src/T32/w/ldstm.rs @@ -12,6 +12,18 @@ pub mod SRS_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111111100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRS_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn SRS_T1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -34,6 +46,18 @@ pub mod RFE_T1_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "RFE_T1_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn RFE_T1_AS( W: ::aarchmrs_types::BitValue<1>, @@ -57,6 +81,30 @@ pub mod STM_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STM_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn STM_T2( W: ::aarchmrs_types::BitValue<1>, @@ -84,6 +132,36 @@ pub mod LDM_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDM_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn LDM_T2( W: ::aarchmrs_types::BitValue<1>, @@ -112,6 +190,30 @@ pub mod STMDB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "STMDB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn STMDB_T1( W: ::aarchmrs_types::BitValue<1>, @@ -139,6 +241,36 @@ pub mod LDMDB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "LDMDB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_register_list_WIDTH: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_OFFSET: u32 = 14u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_M_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_OFFSET: u32 = 15u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_P_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn LDMDB_T1( W: ::aarchmrs_types::BitValue<1>, @@ -167,6 +299,18 @@ pub mod SRS_T2_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000011111111111111100000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SRS_T2_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_mode_WIDTH: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn SRS_T2_AS( W: ::aarchmrs_types::BitValue<1>, @@ -189,6 +333,18 @@ pub mod RFE_T2_AS { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111111111111111u32; #[cfg(feature = "meta")] pub const NAME: &str = "RFE_T2_AS"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_W_WIDTH: u32 = 1u32; #[inline] pub const fn RFE_T2_AS( W: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/lmul_div/div.rs b/aarchmrs-instructions/src/T32/w/lmul_div/div.rs index 2a1bf575..63acf500 100644 --- a/aarchmrs-instructions/src/T32/w/lmul_div/div.rs +++ b/aarchmrs-instructions/src/T32/w/lmul_div/div.rs @@ -12,6 +12,24 @@ pub mod SDIV_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SDIV_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SDIV_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,24 @@ pub mod UDIV_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000001111000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UDIV_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UDIV_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/lmul_div/lmul.rs b/aarchmrs-instructions/src/T32/w/lmul_div/lmul.rs index 56e14336..0eba67f5 100644 --- a/aarchmrs-instructions/src/T32/w/lmul_div/lmul.rs +++ b/aarchmrs-instructions/src/T32/w/lmul_div/lmul.rs @@ -12,6 +12,30 @@ pub mod SMULL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMULL_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod UMULL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMULL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UMULL_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,30 @@ pub mod SMLAL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAL_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -90,6 +162,30 @@ pub mod SMLALBB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALBB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALBB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -116,6 +212,30 @@ pub mod SMLALBT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALBT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALBT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -142,6 +262,30 @@ pub mod SMLALTB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALTB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALTB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -168,6 +312,30 @@ pub mod SMLALTT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALTT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALTT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -194,6 +362,30 @@ pub mod SMLALD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -220,6 +412,30 @@ pub mod SMLALDX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLALDX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLALDX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -246,6 +462,30 @@ pub mod SMLSLD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSLD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSLD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -272,6 +512,30 @@ pub mod SMLSLDX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSLDX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSLDX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -298,6 +562,30 @@ pub mod UMLAL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMLAL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UMLAL_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -324,6 +612,30 @@ pub mod UMAAL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UMAAL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdHi_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_RdLo_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UMAAL_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/mul/mul_abd.rs b/aarchmrs-instructions/src/T32/w/mul/mul_abd.rs index 3c1328d4..4d1812f8 100644 --- a/aarchmrs-instructions/src/T32/w/mul/mul_abd.rs +++ b/aarchmrs-instructions/src/T32/w/mul/mul_abd.rs @@ -12,6 +12,30 @@ pub mod MLA_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLA_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn MLA_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -38,6 +62,30 @@ pub mod MLS_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MLS_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn MLS_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -64,6 +112,24 @@ pub mod MUL_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MUL_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn MUL_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -89,6 +155,30 @@ pub mod SMLABB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLABB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLABB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -115,6 +205,30 @@ pub mod SMLABT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLABT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLABT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -141,6 +255,30 @@ pub mod SMLATB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLATB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLATB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -167,6 +305,30 @@ pub mod SMLATT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLATT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLATT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -193,6 +355,24 @@ pub mod SMULBB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULBB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMULBB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -218,6 +398,24 @@ pub mod SMULBT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULBT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMULBT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -243,6 +441,24 @@ pub mod SMULTB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULTB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMULTB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -268,6 +484,24 @@ pub mod SMULTT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULTT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMULTT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -293,6 +527,30 @@ pub mod SMLAD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -319,6 +577,30 @@ pub mod SMLADX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLADX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLADX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -345,6 +627,24 @@ pub mod SMUAD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUAD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMUAD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -370,6 +670,24 @@ pub mod SMUADX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUADX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMUADX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -395,6 +713,30 @@ pub mod SMLAWB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAWB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAWB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -421,6 +763,30 @@ pub mod SMLAWT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLAWT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLAWT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -447,6 +813,24 @@ pub mod SMULWB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULWB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMULWB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -472,6 +856,24 @@ pub mod SMULWT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMULWT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMULWT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -497,6 +899,30 @@ pub mod SMLSD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -523,6 +949,30 @@ pub mod SMLSDX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMLSDX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMLSDX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -549,6 +999,24 @@ pub mod SMUSD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUSD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMUSD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -574,6 +1042,24 @@ pub mod SMUSDX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMUSDX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMUSDX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -599,6 +1085,30 @@ pub mod SMMLA_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLA_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLA_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -625,6 +1135,30 @@ pub mod SMMLAR_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLAR_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLAR_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -651,6 +1185,24 @@ pub mod SMMUL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMUL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMMUL_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -676,6 +1228,24 @@ pub mod SMMULR_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMULR_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMMULR_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -701,6 +1271,30 @@ pub mod SMMLS_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLS_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLS_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -727,6 +1321,30 @@ pub mod SMMLSR_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SMMLSR_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SMMLSR_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -753,6 +1371,30 @@ pub mod USADA8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USADA8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Ra_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USADA8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -779,6 +1421,24 @@ pub mod USAD8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAD8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USAD8_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/reg/addsub_par.rs b/aarchmrs-instructions/src/T32/w/reg/addsub_par.rs index 1b75edd5..806cc6b8 100644 --- a/aarchmrs-instructions/src/T32/w/reg/addsub_par.rs +++ b/aarchmrs-instructions/src/T32/w/reg/addsub_par.rs @@ -12,6 +12,24 @@ pub mod SADD8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADD8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SADD8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -37,6 +55,24 @@ pub mod QADD8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QADD8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QADD8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -62,6 +98,24 @@ pub mod SHADD8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHADD8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SHADD8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -87,6 +141,24 @@ pub mod UADD8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADD8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UADD8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -112,6 +184,24 @@ pub mod UQADD8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQADD8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UQADD8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -137,6 +227,24 @@ pub mod UHADD8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHADD8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UHADD8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -162,6 +270,24 @@ pub mod SADD16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SADD16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SADD16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -187,6 +313,24 @@ pub mod QADD16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QADD16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QADD16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -212,6 +356,24 @@ pub mod SHADD16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHADD16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SHADD16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -237,6 +399,24 @@ pub mod UADD16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UADD16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UADD16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -262,6 +442,24 @@ pub mod UQADD16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQADD16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UQADD16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -287,6 +485,24 @@ pub mod UHADD16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHADD16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UHADD16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -312,6 +528,24 @@ pub mod SASX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SASX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SASX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -337,6 +571,24 @@ pub mod QASX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QASX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QASX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -362,6 +614,24 @@ pub mod SHASX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHASX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SHASX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -387,6 +657,24 @@ pub mod UASX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UASX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UASX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -412,6 +700,24 @@ pub mod UQASX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQASX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UQASX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -437,6 +743,24 @@ pub mod UHASX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHASX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UHASX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -462,6 +786,24 @@ pub mod SSUB8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSUB8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SSUB8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -487,6 +829,24 @@ pub mod QSUB8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSUB8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QSUB8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -512,6 +872,24 @@ pub mod SHSUB8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHSUB8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SHSUB8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -537,6 +915,24 @@ pub mod USUB8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USUB8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USUB8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -562,6 +958,24 @@ pub mod UQSUB8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSUB8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UQSUB8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -587,6 +1001,24 @@ pub mod UHSUB8_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHSUB8_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UHSUB8_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -612,6 +1044,24 @@ pub mod SSUB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSUB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SSUB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -637,6 +1087,24 @@ pub mod QSUB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSUB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QSUB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -662,6 +1130,24 @@ pub mod SHSUB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHSUB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SHSUB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -687,6 +1173,24 @@ pub mod USUB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USUB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USUB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -712,6 +1216,24 @@ pub mod UQSUB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSUB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UQSUB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -737,6 +1259,24 @@ pub mod UHSUB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHSUB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UHSUB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -762,6 +1302,24 @@ pub mod SSAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SSAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SSAX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -787,6 +1345,24 @@ pub mod QSAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QSAX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -812,6 +1388,24 @@ pub mod SHSAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SHSAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SHSAX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -837,6 +1431,24 @@ pub mod USAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "USAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn USAX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -862,6 +1474,24 @@ pub mod UQSAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UQSAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UQSAX_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -887,6 +1517,24 @@ pub mod UHSAX_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UHSAX_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UHSAX_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/reg/dpint_2r.rs b/aarchmrs-instructions/src/T32/w/reg/dpint_2r.rs index 5e89e71f..fdbbb0ec 100644 --- a/aarchmrs-instructions/src/T32/w/reg/dpint_2r.rs +++ b/aarchmrs-instructions/src/T32/w/reg/dpint_2r.rs @@ -14,6 +14,24 @@ pub mod QADD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QADD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QADD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -39,6 +57,24 @@ pub mod QDADD_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QDADD_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QDADD_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -64,6 +100,24 @@ pub mod QSUB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QSUB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QSUB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -89,6 +143,24 @@ pub mod QDSUB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "QDSUB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn QDSUB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -114,6 +186,24 @@ pub mod REV_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn REV_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -139,6 +229,24 @@ pub mod REV16_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REV16_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn REV16_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -164,6 +272,24 @@ pub mod RBIT_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "RBIT_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn RBIT_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -189,6 +315,24 @@ pub mod REVSH_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "REVSH_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn REVSH_T2( Rn: ::aarchmrs_types::BitValue<4>, @@ -214,6 +358,24 @@ pub mod SEL_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SEL_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SEL_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -239,6 +401,24 @@ pub mod CLZ_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CLZ_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CLZ_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -264,6 +444,24 @@ pub mod CRC32B_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32B_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32B_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -289,6 +487,24 @@ pub mod CRC32H_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32H_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32H_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -314,6 +530,24 @@ pub mod CRC32W_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32W_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32W_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -339,6 +573,24 @@ pub mod CRC32CB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32CB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -364,6 +616,24 @@ pub mod CRC32CH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32CH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -389,6 +659,24 @@ pub mod CRC32CW_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "CRC32CW_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn CRC32CW_T1( Rn: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/reg/extendr.rs b/aarchmrs-instructions/src/T32/w/reg/extendr.rs index 72a6f70d..86f45b4b 100644 --- a/aarchmrs-instructions/src/T32/w/reg/extendr.rs +++ b/aarchmrs-instructions/src/T32/w/reg/extendr.rs @@ -12,6 +12,30 @@ pub mod SXTAH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTAH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SXTAH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -39,6 +63,24 @@ pub mod SXTH_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTH_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn SXTH_T2( Rd: ::aarchmrs_types::BitValue<4>, @@ -63,6 +105,30 @@ pub mod UXTAH_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTAH_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UXTAH_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -90,6 +156,24 @@ pub mod UXTH_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTH_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn UXTH_T2( Rd: ::aarchmrs_types::BitValue<4>, @@ -114,6 +198,30 @@ pub mod SXTAB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTAB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SXTAB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -141,6 +249,24 @@ pub mod SXTB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn SXTB16_T1( Rd: ::aarchmrs_types::BitValue<4>, @@ -165,6 +291,30 @@ pub mod UXTAB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTAB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UXTAB16_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -192,6 +342,24 @@ pub mod UXTB16_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTB16_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn UXTB16_T1( Rd: ::aarchmrs_types::BitValue<4>, @@ -216,6 +384,30 @@ pub mod SXTAB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTAB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn SXTAB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -243,6 +435,24 @@ pub mod SXTB_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "SXTB_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn SXTB_T2( Rd: ::aarchmrs_types::BitValue<4>, @@ -267,6 +477,30 @@ pub mod UXTAB_T1 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTAB_T1"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; #[inline] pub const fn UXTAB_T1( Rn: ::aarchmrs_types::BitValue<4>, @@ -294,6 +528,24 @@ pub mod UXTB_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000001000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "UXTB_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_rotate_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; #[inline] pub const fn UXTB_T2( Rd: ::aarchmrs_types::BitValue<4>, diff --git a/aarchmrs-instructions/src/T32/w/reg/shiftr.rs b/aarchmrs-instructions/src/T32/w/reg/shiftr.rs index bdc7ed35..140bdd23 100644 --- a/aarchmrs-instructions/src/T32/w/reg/shiftr.rs +++ b/aarchmrs-instructions/src/T32/w/reg/shiftr.rs @@ -12,6 +12,30 @@ pub mod MOVS_rr_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOVS_rr_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; #[inline] pub const fn MOVS_rr_T2( stype: ::aarchmrs_types::BitValue<2>, @@ -40,6 +64,30 @@ pub mod MOV_rr_T2 { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "MOV_rr_T2"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rs_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_OFFSET: u32 = 21u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_stype_WIDTH: u32 = 2u32; #[inline] pub const fn MOV_rr_T2( stype: ::aarchmrs_types::BitValue<2>, diff --git a/aarchmrs-instructions/src/T32/w/vldst/asimldall.rs b/aarchmrs-instructions/src/T32/w/vldst/asimldall.rs index ae854bf6..f9341eb3 100644 --- a/aarchmrs-instructions/src/T32/w/vldst/asimldall.rs +++ b/aarchmrs-instructions/src/T32/w/vldst/asimldall.rs @@ -12,6 +12,42 @@ pub mod VLD1_a_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_a_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_a_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -44,6 +80,42 @@ pub mod VLD1_a_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_a_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_a_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -76,6 +148,48 @@ pub mod VLD1_a_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_a_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_a_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -109,6 +223,42 @@ pub mod VLD2_a_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_a_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_a_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -141,6 +291,42 @@ pub mod VLD2_a_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_a_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_a_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -173,6 +359,48 @@ pub mod VLD2_a_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_a_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_a_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -206,6 +434,36 @@ pub mod VLD3_a_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_a_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_a_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -236,6 +494,36 @@ pub mod VLD3_a_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_a_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_a_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -266,6 +554,42 @@ pub mod VLD3_a_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_a_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_a_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -298,6 +622,42 @@ pub mod VLD4_a_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_a_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_a_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -330,6 +690,42 @@ pub mod VLD4_a_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_a_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_a_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -362,6 +758,48 @@ pub mod VLD4_a_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_a_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_a_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_OFFSET: u32 = 5u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_T_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_a_T1_postr( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/vldst/asimldstms.rs b/aarchmrs-instructions/src/T32/w/vldst/asimldstms.rs index 6e8f5e00..63bbe68d 100644 --- a/aarchmrs-instructions/src/T32/w/vldst/asimldstms.rs +++ b/aarchmrs-instructions/src/T32/w/vldst/asimldstms.rs @@ -12,6 +12,42 @@ pub mod VST4_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -44,6 +80,42 @@ pub mod VST4_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -76,6 +148,48 @@ pub mod VST4_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -109,6 +223,36 @@ pub mod VST1_m_T4_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T4_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T4_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -139,6 +283,36 @@ pub mod VST1_m_T4_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T4_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T4_posti( D: ::aarchmrs_types::BitValue<1>, @@ -169,6 +343,42 @@ pub mod VST1_m_T4_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T4_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T4_postr( D: ::aarchmrs_types::BitValue<1>, @@ -200,6 +410,36 @@ pub mod VST2_m_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -230,6 +470,36 @@ pub mod VST2_m_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -260,6 +530,42 @@ pub mod VST2_m_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -291,6 +597,42 @@ pub mod VST3_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -323,6 +665,42 @@ pub mod VST3_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -355,6 +733,48 @@ pub mod VST3_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -388,6 +808,36 @@ pub mod VST1_m_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -418,6 +868,36 @@ pub mod VST1_m_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -448,6 +928,42 @@ pub mod VST1_m_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -479,6 +995,36 @@ pub mod VST1_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -509,6 +1055,36 @@ pub mod VST1_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -539,6 +1115,42 @@ pub mod VST1_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -570,6 +1182,42 @@ pub mod VST2_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -602,6 +1250,42 @@ pub mod VST2_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -634,6 +1318,48 @@ pub mod VST2_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -667,6 +1393,36 @@ pub mod VST1_m_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -697,6 +1453,36 @@ pub mod VST1_m_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -727,6 +1513,42 @@ pub mod VST1_m_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_m_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_m_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -758,6 +1580,42 @@ pub mod VLD4_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -790,6 +1648,42 @@ pub mod VLD4_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -822,6 +1716,48 @@ pub mod VLD4_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -855,6 +1791,36 @@ pub mod VLD1_m_T4_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T4_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T4_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -885,6 +1851,36 @@ pub mod VLD1_m_T4_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T4_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T4_posti( D: ::aarchmrs_types::BitValue<1>, @@ -915,6 +1911,42 @@ pub mod VLD1_m_T4_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T4_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T4_postr( D: ::aarchmrs_types::BitValue<1>, @@ -946,6 +1978,36 @@ pub mod VLD2_m_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -976,6 +2038,36 @@ pub mod VLD2_m_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1006,6 +2098,42 @@ pub mod VLD2_m_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1037,6 +2165,42 @@ pub mod VLD3_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1069,6 +2233,42 @@ pub mod VLD3_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1101,6 +2301,48 @@ pub mod VLD3_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1134,6 +2376,36 @@ pub mod VLD1_m_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1164,6 +2436,36 @@ pub mod VLD1_m_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1194,6 +2496,42 @@ pub mod VLD1_m_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1225,6 +2563,36 @@ pub mod VLD1_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1255,6 +2623,36 @@ pub mod VLD1_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1285,6 +2683,42 @@ pub mod VLD1_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1316,6 +2750,42 @@ pub mod VLD2_m_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1348,6 +2818,42 @@ pub mod VLD2_m_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1380,6 +2886,48 @@ pub mod VLD2_m_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_m_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_OFFSET: u32 = 8u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_itype_WIDTH: u32 = 1u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_m_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1413,6 +2961,36 @@ pub mod VLD1_m_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1443,6 +3021,36 @@ pub mod VLD1_m_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1473,6 +3081,42 @@ pub mod VLD1_m_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_m_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_align_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_OFFSET: u32 = 6u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_size_WIDTH: u32 = 2u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_m_T2_postr( D: ::aarchmrs_types::BitValue<1>, diff --git a/aarchmrs-instructions/src/T32/w/vldst/asimldstss.rs b/aarchmrs-instructions/src/T32/w/vldst/asimldstss.rs index 4834675f..1f025272 100644 --- a/aarchmrs-instructions/src/T32/w/vldst/asimldstss.rs +++ b/aarchmrs-instructions/src/T32/w/vldst/asimldstss.rs @@ -12,6 +12,30 @@ pub mod VST1_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -40,6 +64,30 @@ pub mod VST1_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -68,6 +116,36 @@ pub mod VST1_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -97,6 +175,30 @@ pub mod VST2_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -125,6 +227,30 @@ pub mod VST2_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -153,6 +279,36 @@ pub mod VST2_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -182,6 +338,30 @@ pub mod VST3_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -210,6 +390,30 @@ pub mod VST3_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -238,6 +442,36 @@ pub mod VST3_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -267,6 +501,30 @@ pub mod VST4_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -295,6 +553,30 @@ pub mod VST4_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -323,6 +605,36 @@ pub mod VST4_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -352,6 +664,30 @@ pub mod VST1_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -380,6 +716,30 @@ pub mod VST1_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -408,6 +768,36 @@ pub mod VST1_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -437,6 +827,30 @@ pub mod VST2_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -465,6 +879,30 @@ pub mod VST2_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -493,6 +931,36 @@ pub mod VST2_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -522,6 +990,30 @@ pub mod VST3_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -550,6 +1042,30 @@ pub mod VST3_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -578,6 +1094,36 @@ pub mod VST3_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -607,6 +1153,30 @@ pub mod VST4_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -635,6 +1205,30 @@ pub mod VST4_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -663,6 +1257,36 @@ pub mod VST4_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -692,6 +1316,30 @@ pub mod VST1_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -720,6 +1368,30 @@ pub mod VST1_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -748,6 +1420,36 @@ pub mod VST1_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST1_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST1_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -777,6 +1479,30 @@ pub mod VST2_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -805,6 +1531,30 @@ pub mod VST2_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -833,6 +1583,36 @@ pub mod VST2_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST2_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST2_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -862,6 +1642,30 @@ pub mod VST3_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -890,6 +1694,30 @@ pub mod VST3_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -918,6 +1746,36 @@ pub mod VST3_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST3_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST3_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -947,6 +1805,30 @@ pub mod VST4_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -975,6 +1857,36 @@ pub mod VST4_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1004,6 +1916,30 @@ pub mod VST4_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VST4_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VST4_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1032,6 +1968,30 @@ pub mod VLD1_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1060,6 +2020,30 @@ pub mod VLD1_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1088,6 +2072,36 @@ pub mod VLD1_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1117,6 +2131,30 @@ pub mod VLD2_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1145,6 +2183,30 @@ pub mod VLD2_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1173,6 +2235,36 @@ pub mod VLD2_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1202,6 +2294,30 @@ pub mod VLD3_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1230,6 +2346,30 @@ pub mod VLD3_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1258,6 +2398,36 @@ pub mod VLD3_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1287,6 +2457,30 @@ pub mod VLD4_1_T1_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T1_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T1_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1315,6 +2509,30 @@ pub mod VLD4_1_T1_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T1_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T1_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1343,6 +2561,36 @@ pub mod VLD4_1_T1_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T1_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T1_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1372,6 +2620,30 @@ pub mod VLD1_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1400,6 +2672,30 @@ pub mod VLD1_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1428,6 +2724,36 @@ pub mod VLD1_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1457,6 +2783,30 @@ pub mod VLD2_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1485,6 +2835,30 @@ pub mod VLD2_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1513,6 +2887,36 @@ pub mod VLD2_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1542,6 +2946,30 @@ pub mod VLD3_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1570,6 +2998,30 @@ pub mod VLD3_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1598,6 +3050,36 @@ pub mod VLD3_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1627,6 +3109,30 @@ pub mod VLD4_1_T2_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T2_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T2_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1655,6 +3161,30 @@ pub mod VLD4_1_T2_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T2_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T2_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1683,6 +3213,36 @@ pub mod VLD4_1_T2_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T2_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T2_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1712,6 +3272,30 @@ pub mod VLD1_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1740,6 +3324,30 @@ pub mod VLD1_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1768,6 +3376,36 @@ pub mod VLD1_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD1_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD1_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1797,6 +3435,30 @@ pub mod VLD2_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1825,6 +3487,30 @@ pub mod VLD2_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1853,6 +3539,36 @@ pub mod VLD2_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD2_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD2_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1882,6 +3598,30 @@ pub mod VLD3_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1910,6 +3650,30 @@ pub mod VLD3_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -1938,6 +3702,36 @@ pub mod VLD3_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD3_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD3_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, @@ -1967,6 +3761,30 @@ pub mod VLD4_1_T3_nowb { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T3_nowb"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T3_nowb( D: ::aarchmrs_types::BitValue<1>, @@ -1995,6 +3813,30 @@ pub mod VLD4_1_T3_posti { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T3_posti"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T3_posti( D: ::aarchmrs_types::BitValue<1>, @@ -2023,6 +3865,36 @@ pub mod VLD4_1_T3_postr { pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32; #[cfg(feature = "meta")] pub const NAME: &str = "VLD4_1_T3_postr"; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_OFFSET: u32 = 0u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rm_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_OFFSET: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_index_align_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_OFFSET: u32 = 12u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Vd_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_OFFSET: u32 = 16u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_Rn_WIDTH: u32 = 4u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_OFFSET: u32 = 22u32; + #[cfg(feature = "meta_field")] + #[allow(nonstandard_style)] + pub const FIELD_D_WIDTH: u32 = 1u32; #[inline] pub const fn VLD4_1_T3_postr( D: ::aarchmrs_types::BitValue<1>, From 4eceea9e1ec832d74f1939b51029f03871ef752a Mon Sep 17 00:00:00 2001 From: Ivan Boldyrev Date: Sun, 1 Mar 2026 11:17:24 +0100 Subject: [PATCH 2/3] fix tests --- aarchmrs-gen/src/generation.rs | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/aarchmrs-gen/src/generation.rs b/aarchmrs-gen/src/generation.rs index e6656596..9eca9a89 100644 --- a/aarchmrs-gen/src/generation.rs +++ b/aarchmrs-gen/src/generation.rs @@ -241,6 +241,42 @@ mod tests { "pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;\n", "#[cfg(feature = \"meta\")]\n", "pub const NAME: &str = \"ADD_64_addsub_shift\";\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_Rd_OFFSET: u32 = 0u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_Rd_WIDTH: u32 = 5u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_Rn_OFFSET: u32 = 5u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_Rn_WIDTH: u32 = 5u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_im3_OFFSET: u32 = 10u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_im3_WIDTH: u32 = 3u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_option_OFFSET: u32 = 13u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_option_WIDTH: u32 = 3u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_Rm_OFFSET: u32 = 16u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_Rm_WIDTH: u32 = 5u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_s_OFFSET: u32 = 31u32;\n", + "#[cfg(feature = \"meta_field\")]\n", + "#[allow(nonstandard_style)]\n", + "pub const FIELD_s_WIDTH: u32 = 1u32;\n", "#[inline]\n", "pub const fn ADD_64_addsub_shift(\n", " s: ::aarchmrs_types::BitValue<1>,\n", From 7ba42127771da3253d841e6aa7721e4d30e7ef27 Mon Sep 17 00:00:00 2001 From: Ivan Boldyrev Date: Sun, 1 Mar 2026 12:29:00 +0100 Subject: [PATCH 3/3] Fixes --- aarchmrs-gen/src/downloads.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/aarchmrs-gen/src/downloads.rs b/aarchmrs-gen/src/downloads.rs index acb612fe..333e41ff 100644 --- a/aarchmrs-gen/src/downloads.rs +++ b/aarchmrs-gen/src/downloads.rs @@ -20,7 +20,7 @@ pub enum DownloadError { } pub(crate) fn ensure_archive(cache_dir: &Path) -> Result { - let archive_file = dbg!(cache_dir.join(AARCHMRS_2025_12_FILE)); + let archive_file = cache_dir.join(AARCHMRS_2025_12_FILE); if !is_valid_archive(&archive_file) { eprintln!("Downloading an archive file..."); download_archive(&archive_file)?;