How do I generate resource reports

[chaojun-gengboy]

Hello author, I see that Verilog code is generated here and testbench is generated. May I ask how do you check his hardware resource occupation (such as LUT, FF) and his Latency? What simulation software is used? Could you tell me in detail? Thank you

[kiabuzz]

For evaluating the hardware resource utilization, you could use Vivado to synthesize and place-and-route the generated Verilog files. Then, the software provides the resource utilization and timing analysis. -Kia

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On Mon, Apr 7, 2025 at 3:10 AM chaojun-gengboy ***@***.***> wrote: Hello author, I see that Verilog code is generated here and testbench is generated. May I ask how do you check his hardware resource occupation (such as LUT, FF) and his Latency? What simulation software is used? Could you tell me in detail? Thank you — Reply to this email directly, view it on GitHub <#2>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AZASNEC2EFUTENW65FKCLY32YIXIFAVCNFSM6AAAAAB2S45QXSVHI2DSMVQWIX3LMV43ASLTON2WKOZSHE3TKOJZG43DGNI> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***> [image: chaojun-gengboy]*chaojun-gengboy* created an issue (kiabuzz/TreeLUT#2) <#2> Hello author, I see that Verilog code is generated here and testbench is generated. May I ask how do you check his hardware resource occupation (such as LUT, FF) and his Latency? What simulation software is used? Could you tell me in detail? Thank you — Reply to this email directly, view it on GitHub <#2>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AZASNEC2EFUTENW65FKCLY32YIXIFAVCNFSM6AAAAAB2S45QXSVHI2DSMVQWIX3LMV43ASLTON2WKOZSHE3TKOJZG43DGNI> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

-- -Kia