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CPU Simulation Guide (ModelSim / QuestaSim)

This guide provides the steps necessary to compile the CPU design files and run a simulation using ModelSim or QuestaSim (which typically use the vlog and vsim commands).

Prerequisites

  1. ModelSim / QuestaSim must be installed and configured on your system, with vlog and vsim available in your terminal path.

  2. A compiled binary file (program.bin) must be available. This file is generated by the assembler/compiler and contains the raw machine code instructions that the CPU will execute.

Step 1: Generate the Program Binary

First, use your compiler and assembler to generate the machine code binary file. This file must be named program.bin and should be placed inside the cpu/ directory for the testbench to automatically locate and load it into the instruction memory.

1. Compile FS code to binary (program.bin)

./fsrvc path/to/your/program.fs --emit-bin program.bin

2. Move the binary into the CPU directory

cp program.bin ./cpu/

Step 2: Compile the Design Files (vlog)

Navigate to the root directory of your project and use vlog to compile all necessary SystemVerilog source files into a library (usually work).

Compile all CPU and Testbench files

Note: Adjust the file paths if your testbench or memory files have different names.

vlog -sv ./cpu/*.sv

This command compiles the files in the cpu/ directory (which should contain the CPU core, the testbench, and the memory model that handles loading program.bin).

Step 3: Run the Simulation (vsim)

Start the simulator and run the top-level testbench module.

Start the simulator with the top-level testbench module (e.g., 'main_tb')

vsim -c -do "run -all; quit" cpu_tb

Running with Waveform Viewer If you want to view the signals in the waveform window, omit the -c (command line) and quit commands:

vsim main_tb

The simulator GUI will open. You can then add signals and run the simulation manually.

The simulation will execute your program.bin file, and the results (such as register file contents or final output) will be displayed in the simulator console or logged to a file as defined by the testbench