ProgramCounter.syr

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.10 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.10 secs
 
--> Reading design: ProgramCounter.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ProgramCounter.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ProgramCounter"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : ProgramCounter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir"  }

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Users/dbake/Desktop/sandbox/ProjectLab1/ProgramCounter.vhd" in Library work.
Architecture behavioral of Entity programcounter is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <ProgramCounter> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ProgramCounter> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/dbake/Desktop/sandbox/ProjectLab1/ProgramCounter.vhd" line 34: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <Address>
Entity <ProgramCounter> analyzed. Unit <ProgramCounter> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <ProgramCounter>.
    Related source file is "C:/Users/dbake/Desktop/sandbox/ProjectLab1/ProgramCounter.vhd".
    Found 9-bit register for signal <Address>.
    Found 9-bit adder for signal <Address$addsub0000>.
    Found 9-bit comparator greatequal for signal <Address$cmp_ge0000> created at line 37.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <ProgramCounter> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 9-bit adder                                           : 1
# Registers                                            : 1
 9-bit register                                        : 1
# Comparators                                          : 1
 9-bit comparator greatequal                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <ProgramCounter>.
The following registers are absorbed into accumulator <Address>: 1 register on signal <Address>.
Unit <ProgramCounter> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Accumulators                                         : 1
 9-bit up loadable accumulator                         : 1
# Comparators                                          : 1
 9-bit comparator greatequal                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ProgramCounter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ProgramCounter, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 9
 Flip-Flops                                            : 9

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ProgramCounter.ngr
Top Level Output File Name         : ProgramCounter
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 31

Cell Usage :
# BELS                             : 49
#      GND                         : 1
#      INV                         : 1
#      LUT3                        : 10
#      LUT4                        : 11
#      MULT_AND                    : 8
#      MUXCY                       : 8
#      MUXF5                       : 1
#      XORCY                       : 9
# FlipFlops/Latches                : 9
#      FDC                         : 9
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 30
#      IBUF                        : 21
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                       12  out of   4656     0%  
 Number of Slice Flip Flops:              9  out of   9312     0%  
 Number of 4 input LUTs:                 22  out of   9312     0%  
 Number of IOs:                          31
 Number of bonded IOBs:                  31  out of    232    13%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
Address_or0000(Address_or000022:O) | NONE(Address_0)        | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.276ns (Maximum Frequency: 233.863MHz)
   Minimum input arrival time before clock: 6.778ns
   Maximum output required time after clock: 4.394ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 4.276ns (frequency: 233.863MHz)
  Total number of paths / destination ports: 81 / 9
-------------------------------------------------------------------------
Delay:               4.276ns (Levels of Logic = 10)
  Source:            Address_0 (FF)
  Destination:       Address_8 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: Address_0 to Address_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.591   0.531  Address_0 (Address_0)
     MULT_AND:I0->LO       0   0.741   0.000  Eqn_0_mand (Eqn_0_mand1)
     MUXCY:DI->O           1   0.888   0.000  Maccum_Address_cy<0> (Maccum_Address_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<1> (Maccum_Address_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<2> (Maccum_Address_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<3> (Maccum_Address_cy<3>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<4> (Maccum_Address_cy<4>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<5> (Maccum_Address_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<6> (Maccum_Address_cy<6>)
     MUXCY:CI->O           0   0.059   0.000  Maccum_Address_cy<7> (Maccum_Address_cy<7>)
     XORCY:CI->O           1   0.804   0.000  Maccum_Address_xor<8> (Result<8>)
     FDC:D                     0.308          Address_8
    ----------------------------------------
    Total                      4.276ns (3.745ns logic, 0.531ns route)
                                       (87.6% logic, 12.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 261 / 9
-------------------------------------------------------------------------
Offset:              6.778ns (Levels of Logic = 12)
  Source:            JUMP_FLG (PAD)
  Destination:       Address_8 (FF)
  Destination Clock: CLK rising

  Data Path: JUMP_FLG to Address_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   1.218   0.882  JUMP_FLG_IBUF (JUMP_FLG_IBUF)
     INV:I->O              9   0.704   0.820  Eqn_011_INV_0 (Eqn_0_mand)
     MULT_AND:I1->LO       0   0.741   0.000  Eqn_0_mand (Eqn_0_mand1)
     MUXCY:DI->O           1   0.888   0.000  Maccum_Address_cy<0> (Maccum_Address_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<1> (Maccum_Address_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<2> (Maccum_Address_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<3> (Maccum_Address_cy<3>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<4> (Maccum_Address_cy<4>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<5> (Maccum_Address_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  Maccum_Address_cy<6> (Maccum_Address_cy<6>)
     MUXCY:CI->O           0   0.059   0.000  Maccum_Address_cy<7> (Maccum_Address_cy<7>)
     XORCY:CI->O           1   0.804   0.000  Maccum_Address_xor<8> (Result<8>)
     FDC:D                     0.308          Address_8
    ----------------------------------------
    Total                      6.778ns (5.076ns logic, 1.702ns route)
                                       (74.9% logic, 25.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              4.394ns (Levels of Logic = 1)
  Source:            Address_8 (FF)
  Destination:       Addr<8> (PAD)
  Source Clock:      CLK rising

  Data Path: Address_8 to Addr<8>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.591   0.531  Address_8 (Address_8)
     OBUF:I->O                 3.272          Addr_8_OBUF (Addr<8>)
    ----------------------------------------
    Total                      4.394ns (3.863ns logic, 0.531ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.30 secs
 
--> 

Total memory usage is 310056 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    1 (   0 filtered)