[REG and APB4] Do not ignore the two lower bits of addresses

Author: diskouna

rtl/apb4_booth_algorithm.vhd

@@ -9,7 +9,7 @@ entity apb4_booth_algorithm is
         PCLK     : in  std_logic; 
         PRESETn  : in  std_logic;
 
-        PADDR    : in  std_logic_vector(4 downto 2);
+        PADDR    : in  std_logic_vector(4 downto 0);
         PSEL     : in  std_logic; 
         PENABLE  : in  std_logic;
         PWRITE   : in  std_logic;
@@ -27,7 +27,7 @@ architecture behavioral of apb4_booth_algorithm is
             rst_i    : in  std_logic;
             sel_i    : in  std_logic;
             we_i     : in  std_logic; -- 1|0 : write|read
-            addr_i   : in  std_logic_vector(4 downto 2); -- 4 bytes aligned addresses
+            addr_i   : in  std_logic_vector(4 downto 0); -- 4 bytes aligned addresses
             wdata_i  : in  std_logic_vector(31 downto 0);
             rdata_o  : out std_logic_vector(31 downto 0)
         );

rtl/reg_booth_algorithm.vhd

@@ -30,7 +30,7 @@ entity reg_booth_algorithm is
         rst_i    : in  std_logic;
         sel_i    : in  std_logic;
         we_i     : in  std_logic; -- 1|0 : write|read
-        addr_i   : in  std_logic_vector(4 downto 2); -- 4 bytes aligned addresses
+        addr_i   : in  std_logic_vector(4 downto 0); -- 4 bytes aligned addresses
         wdata_i  : in  std_logic_vector(31 downto 0);
         rdata_o  : out std_logic_vector(31 downto 0)
     );

rtl/utils.vhd

@@ -8,12 +8,12 @@ package utils is
     function clog2(number : positive) return positive;
 
     -- Registers interface 
-    constant OP_1_ADDR    : std_logic_vector(4 downto 2) := b"000";  
-    constant OP_2_ADDR    : std_logic_vector(4 downto 2) := b"001";  
-    constant RESULT_ADDR  : std_logic_vector(4 downto 2) := b"010"; 
-    constant CTRL_ADDR    : std_logic_vector(4 downto 2) := b"011"; 
-    constant STAT_ADDR    : std_logic_vector(4 downto 2) := b"100"; 
-    constant CORE_ID_ADDR : std_logic_vector(4 downto 2) := b"101"; 
+    constant OP_1_ADDR    : std_logic_vector(4 downto 0) := b"000_00";  
+    constant OP_2_ADDR    : std_logic_vector(4 downto 0) := b"001_00";  
+    constant RESULT_ADDR  : std_logic_vector(4 downto 0) := b"010_00"; 
+    constant CTRL_ADDR    : std_logic_vector(4 downto 0) := b"011_00"; 
+    constant STAT_ADDR    : std_logic_vector(4 downto 0) := b"100_00"; 
+    constant CORE_ID_ADDR : std_logic_vector(4 downto 0) := b"101_00"; 
 
     constant CTRL_MASK : std_logic_vector(31 downto 0) := x"0000_0001";
     constant STAT_MASK : std_logic_vector(31 downto 0) := x"0000_0003";

tb/tb_apb4_booth_algorithm.vhd

@@ -12,7 +12,7 @@ architecture behavioral of tb_apb4_booth_algorithm is
             PCLK     : in  std_logic; 
             PRESETn  : in  std_logic;
 
-            PADDR    : in  std_logic_vector(4 downto 2);
+            PADDR    : in  std_logic_vector(4 downto 0);
             PSEL     : in  std_logic; 
             PENABLE  : in  std_logic;
             PWRITE   : in  std_logic;
@@ -27,7 +27,7 @@ architecture behavioral of tb_apb4_booth_algorithm is
     signal rstn   : std_logic := '1';
 
     type booth_if_t is record
-        PADDR    :  std_logic_vector(4 downto 2);
+        PADDR    :  std_logic_vector(4 downto 0);
         PSEL     :  std_logic; 
         PENABLE  :  std_logic;
         PWRITE   :  std_logic;

tb/tb_reg_booth_algorithm.vhd

@@ -13,7 +13,7 @@ architecture behavioral of tb_reg_booth_algorithm is
             rst_i    : in  std_logic;
             sel_i    : in  std_logic;
             we_i     : in  std_logic; -- 1|0 : write|read
-            addr_i   : in  std_logic_vector(4 downto 2); -- 4 bytes aligned addresses
+            addr_i   : in  std_logic_vector(4 downto 0); -- 4 bytes aligned addresses
             wdata_i  : in  std_logic_vector(31 downto 0);
             rdata_o  : out std_logic_vector(31 downto 0)
         );
@@ -25,7 +25,7 @@ architecture behavioral of tb_reg_booth_algorithm is
     type booth_if_t is record
         sel_i    : std_logic;
         we_i     : std_logic;
-        addr_i   : std_logic_vector(4 downto 2);        
+        addr_i   : std_logic_vector(4 downto 0);
         wdata_i  : std_logic_vector(31 downto 0);
         rdata_o  : std_logic_vector(31 downto 0);
     end record;