From 5fa3ed128f55ea79dc755dfa6dcf637dbd5cd579 Mon Sep 17 00:00:00 2001 From: danielkwan2004 Date: Wed, 9 Apr 2025 19:05:14 +0800 Subject: [PATCH 01/21] scroll wheel done for graph to zoom in/out, scroll wheel also done for andy's polynomial table, overlaid cursor for further fix, but have not test yet --- .../blk_mem_gen_const/blk_mem_gen_const.xml | 12 +-- .../blk_mem_gen_const_sim_netlist.v | 16 ++-- .../blk_mem_gen_const_sim_netlist.vhdl | 22 +---- .../blk_mem_gen_const_stub.v | 8 +- .../ip/blk_mem_gen_img/blk_mem_gen_img.xml | 12 +-- .../blk_mem_gen_img_sim_netlist.v | 15 ++-- .../blk_mem_gen_img_sim_netlist.vhdl | 20 +---- .../ip/blk_mem_gen_img/blk_mem_gen_img_stub.v | 8 +- FDP.srcs/sources_1/new/Top_Student.v | 82 ++++++++++++++++++- FDP.srcs/sources_1/new/graph_display_cached.v | 10 ++- FDP.srcs/sources_1/new/mouse_module.v | 2 + FDP.srcs/sources_1/new/pan_graph.v | 53 +++++------- FDP.srcs/sources_1/new/phase_control.v | 17 ++-- FDP.srcs/sources_1/new/phase_three_wrapper.v | 12 ++- .../new/polynomial_table_cursor_controller.v | 26 +++++- .../sources_1/new/polynomial_table_module.v | 14 +++- FDP.xpr | 9 +- 17 files changed, 211 insertions(+), 127 deletions(-) diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml index ab847db..b6de1cb 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml @@ -1498,11 +1498,11 @@ GENtimestamp - Tue Apr 08 17:47:39 UTC 2025 + Wed Apr 09 09:46:10 UTC 2025 outputProductCRC - 8:55356a36 + 8:d19c862a @@ -1518,11 +1518,11 @@ GENtimestamp - Tue Apr 08 17:47:39 UTC 2025 + Wed Apr 09 09:46:10 UTC 2025 outputProductCRC - 8:55356a36 + 8:d19c862a @@ -1536,11 +1536,11 @@ GENtimestamp - Tue Apr 08 17:48:48 UTC 2025 + Wed Apr 09 09:46:15 UTC 2025 outputProductCRC - 8:55356a36 + 8:d19c862a diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v index d784299..257d335 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:48 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v} +// Date : Sun Mar 16 15:21:27 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top blk_mem_gen_const -prefix +// blk_mem_gen_const_ blk_mem_gen_const_sim_netlist.v // Design : blk_mem_gen_const // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -192,7 +192,6 @@ module blk_mem_gen_const .web(1'b0)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module blk_mem_gen_const_blk_mem_gen_generic_cstr (douta, addra, @@ -577,7 +576,6 @@ module blk_mem_gen_const_blk_mem_gen_generic_cstr .wea(wea)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_mux" *) module blk_mem_gen_const_blk_mem_gen_mux (douta, p_7_out, @@ -1414,7 +1412,6 @@ module blk_mem_gen_const_blk_mem_gen_mux .R(1'b0)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module blk_mem_gen_const_blk_mem_gen_prim_width (\douta[0] , clka, @@ -2266,7 +2263,6 @@ module blk_mem_gen_const_blk_mem_gen_prim_width__parameterized9 .wea(wea)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) module blk_mem_gen_const_blk_mem_gen_prim_wrapper_init (\douta[0] , clka, @@ -8624,7 +8620,6 @@ module blk_mem_gen_const_blk_mem_gen_prim_wrapper_init__parameterized9 .O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 )); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_top" *) module blk_mem_gen_const_blk_mem_gen_top (douta, addra, @@ -8675,7 +8670,7 @@ endmodule (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50890" *) (* C_WRITE_DEPTH_B = "50890" *) (* C_WRITE_MODE_A = "READ_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "16" *) (* C_WRITE_WIDTH_B = "16" *) -(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_4_1" *) (* downgradeipidentifiedwarnings = "yes" *) +(* C_XDEVICEFAMILY = "artix7" *) (* downgradeipidentifiedwarnings = "yes" *) module blk_mem_gen_const_blk_mem_gen_v8_4_1 (clka, rsta, @@ -8909,7 +8904,6 @@ module blk_mem_gen_const_blk_mem_gen_v8_4_1 .wea(wea)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_1_synth" *) module blk_mem_gen_const_blk_mem_gen_v8_4_1_synth (douta, addra, diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl index 2623f82..71b70b6 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 --- Date : Wed Apr 9 01:48:48 2025 --- Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim {C:/Uni --- Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl} +-- Date : Sun Mar 16 15:21:27 2025 +-- Host : Daniel running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top blk_mem_gen_const -prefix +-- blk_mem_gen_const_ blk_mem_gen_const_sim_netlist.vhdl -- Design : blk_mem_gen_const -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -59,8 +59,6 @@ entity blk_mem_gen_const_blk_mem_gen_mux is \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_mux : entity is "blk_mem_gen_mux"; end blk_mem_gen_const_blk_mem_gen_mux; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_mux is @@ -1007,8 +1005,6 @@ entity blk_mem_gen_const_blk_mem_gen_prim_wrapper_init is dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end blk_mem_gen_const_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_prim_wrapper_init is @@ -7616,8 +7612,6 @@ entity blk_mem_gen_const_blk_mem_gen_prim_width is dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end blk_mem_gen_const_blk_mem_gen_prim_width; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_prim_width is @@ -8419,8 +8413,6 @@ entity blk_mem_gen_const_blk_mem_gen_generic_cstr is dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end blk_mem_gen_const_blk_mem_gen_generic_cstr; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_generic_cstr is @@ -9036,8 +9028,6 @@ entity blk_mem_gen_const_blk_mem_gen_top is dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_top : entity is "blk_mem_gen_top"; end blk_mem_gen_const_blk_mem_gen_top; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_top is @@ -9063,8 +9053,6 @@ entity blk_mem_gen_const_blk_mem_gen_v8_4_1_synth is dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_v8_4_1_synth : entity is "blk_mem_gen_v8_4_1_synth"; end blk_mem_gen_const_blk_mem_gen_v8_4_1_synth; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_v8_4_1_synth is @@ -9294,8 +9282,6 @@ entity blk_mem_gen_const_blk_mem_gen_v8_4_1 is attribute C_WRITE_WIDTH_B of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is 16; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "artix7"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "blk_mem_gen_v8_4_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "yes"; end blk_mem_gen_const_blk_mem_gen_v8_4_1; diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v index eb1df66..97083a6 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:48 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v} +// Date : Sun Mar 16 15:21:27 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top blk_mem_gen_const -prefix +// blk_mem_gen_const_ blk_mem_gen_const_stub.v // Design : blk_mem_gen_const // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcpg236-1 diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml index c715465..262cc64 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml @@ -1498,11 +1498,11 @@ GENtimestamp - Tue Apr 08 17:47:40 UTC 2025 + Wed Apr 09 09:46:10 UTC 2025 outputProductCRC - 8:ac951226 + 8:8537c8d0 @@ -1518,11 +1518,11 @@ GENtimestamp - Tue Apr 08 17:47:40 UTC 2025 + Wed Apr 09 09:46:10 UTC 2025 outputProductCRC - 8:ac951226 + 8:8537c8d0 @@ -1536,11 +1536,11 @@ GENtimestamp - Tue Apr 08 17:48:22 UTC 2025 + Wed Apr 09 09:46:15 UTC 2025 outputProductCRC - 8:ac951226 + 8:8537c8d0 diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v index 3502179..f9ee9ef 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:22 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v} +// Date : Sun Mar 16 15:20:40 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top blk_mem_gen_img -prefix +// blk_mem_gen_img_ blk_mem_gen_img_sim_netlist.v // Design : blk_mem_gen_img // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -198,7 +198,6 @@ module blk_mem_gen_img .web(1'b0)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module blk_mem_gen_img_blk_mem_gen_generic_cstr (doutb, clka, @@ -233,7 +232,6 @@ module blk_mem_gen_img_blk_mem_gen_generic_cstr .wea(wea)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module blk_mem_gen_img_blk_mem_gen_prim_width (doutb, clka, @@ -268,7 +266,6 @@ module blk_mem_gen_img_blk_mem_gen_prim_width .wea(wea)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) module blk_mem_gen_img_blk_mem_gen_prim_wrapper_init (doutb, clka, @@ -438,7 +435,6 @@ module blk_mem_gen_img_blk_mem_gen_prim_wrapper_init .WEBWE({1'b0,1'b0,1'b0,1'b0})); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_top" *) module blk_mem_gen_img_blk_mem_gen_top (doutb, clka, @@ -497,7 +493,7 @@ endmodule (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "784" *) (* C_WRITE_DEPTH_B = "784" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "1" *) (* C_WRITE_WIDTH_B = "1" *) -(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_4_1" *) (* downgradeipidentifiedwarnings = "yes" *) +(* C_XDEVICEFAMILY = "artix7" *) (* downgradeipidentifiedwarnings = "yes" *) module blk_mem_gen_img_blk_mem_gen_v8_4_1 (clka, rsta, @@ -693,7 +689,6 @@ module blk_mem_gen_img_blk_mem_gen_v8_4_1 .wea(wea)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_1_synth" *) module blk_mem_gen_img_blk_mem_gen_v8_4_1_synth (doutb, clka, diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl index b9f25c7..3ab4869 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 --- Date : Wed Apr 9 01:48:22 2025 --- Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim {C:/Uni --- Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl} +-- Date : Sun Mar 16 15:20:40 2025 +-- Host : Daniel running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top blk_mem_gen_img -prefix +-- blk_mem_gen_img_ blk_mem_gen_img_sim_netlist.vhdl -- Design : blk_mem_gen_img -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -24,8 +24,6 @@ entity blk_mem_gen_img_blk_mem_gen_prim_wrapper_init is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end blk_mem_gen_img_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_prim_wrapper_init is @@ -211,8 +209,6 @@ entity blk_mem_gen_img_blk_mem_gen_prim_width is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end blk_mem_gen_img_blk_mem_gen_prim_width; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_prim_width is @@ -242,8 +238,6 @@ entity blk_mem_gen_img_blk_mem_gen_generic_cstr is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end blk_mem_gen_img_blk_mem_gen_generic_cstr; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_generic_cstr is @@ -273,8 +267,6 @@ entity blk_mem_gen_img_blk_mem_gen_top is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_top : entity is "blk_mem_gen_top"; end blk_mem_gen_img_blk_mem_gen_top; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_top is @@ -304,8 +296,6 @@ entity blk_mem_gen_img_blk_mem_gen_v8_4_1_synth is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_v8_4_1_synth : entity is "blk_mem_gen_v8_4_1_synth"; end blk_mem_gen_img_blk_mem_gen_v8_4_1_synth; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_v8_4_1_synth is @@ -537,8 +527,6 @@ entity blk_mem_gen_img_blk_mem_gen_v8_4_1 is attribute C_WRITE_WIDTH_B of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is 1; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is "artix7"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is "blk_mem_gen_v8_4_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is "yes"; end blk_mem_gen_img_blk_mem_gen_v8_4_1; diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v index b684e7d..fd85d1e 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:22 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v} +// Date : Sun Mar 16 15:20:40 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top blk_mem_gen_img -prefix +// blk_mem_gen_img_ blk_mem_gen_img_stub.v // Design : blk_mem_gen_img // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcpg236-1 diff --git a/FDP.srcs/sources_1/new/Top_Student.v b/FDP.srcs/sources_1/new/Top_Student.v index 1a190be..0a49349 100644 --- a/FDP.srcs/sources_1/new/Top_Student.v +++ b/FDP.srcs/sources_1/new/Top_Student.v @@ -24,13 +24,67 @@ module Top_Student ( output [3:0] an ); + //mouse part + // Default input values for the mouse_module + wire [11:0] value; + assign value = 12'b0; // Default value is 0 (origin) + + wire setx; + assign setx = 1'b0; // No update command, keep current position + + wire sety; + assign sety = 1'b0; // No update command, keep current position + + wire setmax_x; + assign setmax_x= 1'b0; // Do not update max_x + + wire setmax_y; + assign setmax_y = 1'b0; // Do not update max_y + wire [11:0] xpos; + wire [11:0] ypos; + wire [3:0] zpos; + wire left; + wire middle; + wire right; + wire new_event; + wire rst; // Reset signal + assign rst = sw[0]; + mouse_module unit_0 ( + .clk (basys_clock), + .rst (rst), + .value (value), + .setmax_x (setmax_x), + .setmax_y (setmax_y), + .setx (setx), + .sety (sety), + .ps2_clk (ps2_clk), + .ps2_data (ps2_data), + .xpos (xpos), + .ypos (ypos), + .zpos (zpos), + .left (left), + .middle (middle), + .right (right), + .new_event (new_event) + ); + //end of mouse part + //part that tracks the number of scroll wheel inputs + wire [3:0] scroll_leds; + scroll_led_accum scroll_test ( + .clk (basys_clock), + .rst (rst), + .new_event (new_event), + .zpos (zpos), + .scroll_dir (scroll_leds)); + //end of part that tracks the number of scroll wheel inputs, shift this around if needed + // 6.25MHz clock for OLED displays wire clk_6p25MHz; flexible_clock_divider clk_6p25MHz_gen( .main_clock(basys_clock), .ticks(7), .output_clock(clk_6p25MHz) - ); + ); // 1kHz clock for cursor_controller wire clk_1kHz; @@ -87,14 +141,14 @@ module Top_Student ( .vccen(JA[6]), .pmoden(JA[7]) ); - + wire [15:0] JB_bg_data; phase_control phase( .clk_100MHz(basys_clock), .clk_1kHz(clk_1kHz), .clk_6p25MHz(clk_6p25MHz), .one_pixel_index(JB_pixel_index), .two_pixel_index(JA_pixel_index), - .one_oled_data(JB_oled_data), + .one_oled_data(JB_bg_data), .two_oled_data(JA_oled_data), .btnU(btnU), .btnD(btnD), @@ -102,9 +156,29 @@ module Top_Student ( .btnL(btnL), .btnR(btnR), .back_switch(sw[15]), + .rst(rst), .led(led), .an(an), - .seg(seg) + .seg(seg), + .xpos(xpos), + .ypos(ypos), + .use_mouse(1), + .mouse_left(left), + .mouse_middle(middle), + .mouse_right(right), + .zpos(zpos) //here, scroll_leds starts at 0, then if we scroll up is 0001, + //then 0011, 0111, 1111, scroll back down is 1111, 0111, 0011, 0001, 0000 ); + wire [6:0] curr_x, curr_y; + on_screen_cursor unit_1 (.basys_clock(clk_6p25MHz), + .pixel_index(JB_pixel_index), + .graph_mode_check(1), //change this if ncessary, when to use the mouse and wben not to use the mouse + .value(value),.setx(setx), + .sety(sety), + .setmax_x(setmax_x),.setmax_y(setmax_y), + .xpos(xpos), .ypos(ypos),.bg_data(JB_bg_data), + .oled_data(JB_oled_data), + .cursor_x(curr_x), .cursor_y(curr_y)); + //curr_x and curr_y is an output that stores the value of the current cursor position in the screen endmodule diff --git a/FDP.srcs/sources_1/new/graph_display_cached.v b/FDP.srcs/sources_1/new/graph_display_cached.v index 153c405..58d4679 100644 --- a/FDP.srcs/sources_1/new/graph_display_cached.v +++ b/FDP.srcs/sources_1/new/graph_display_cached.v @@ -21,12 +21,14 @@ module graph_display_cached( - input clk, + input clk, //6p25MHz clock input btnU, btnD, btnL, btnR, btnC, input [12:0] pixel_index, input signed [31:0] coeff_a, coeff_b, coeff_c, coeff_d, input [11:0] curr_x, curr_y, input [3:0] zoom_level, + input rst, + input [3:0] zpos, input mouse_left, mouse_right, mouse_middle, new_event, input [31:0] colour, input is_graphing_mode, @@ -36,6 +38,7 @@ module graph_display_cached( output reg [15:0] oled_data ); + // Constants parameter SCREEN_WIDTH = 96; parameter SCREEN_HEIGHT = 64; @@ -100,7 +103,7 @@ module graph_display_cached( .y_value(computed_y), .computation_complete(compute_complete) ); - + // Connect pan_graph module for pan and zoom functionality pan_graph panning_unit( .basys_clk(clk), @@ -109,10 +112,11 @@ module graph_display_cached( .btnL(btnL), .btnR(btnR), .btnC(btnC), + .rst(rst), .is_pan(is_pan), .mouse_x(curr_x), .mouse_y(curr_y), - .zpos(zoom_level), + .zpos(zpos), .new_event(new_event), .left(mouse_left), .right(mouse_right), diff --git a/FDP.srcs/sources_1/new/mouse_module.v b/FDP.srcs/sources_1/new/mouse_module.v index ffa4bf5..8b1a7e2 100644 --- a/FDP.srcs/sources_1/new/mouse_module.v +++ b/FDP.srcs/sources_1/new/mouse_module.v @@ -62,5 +62,7 @@ module mouse_module ( .ps2_clk (ps2_clk), .ps2_data (ps2_data) ); + + endmodule \ No newline at end of file diff --git a/FDP.srcs/sources_1/new/pan_graph.v b/FDP.srcs/sources_1/new/pan_graph.v index 8bfe5a0..0c7cd23 100644 --- a/FDP.srcs/sources_1/new/pan_graph.v +++ b/FDP.srcs/sources_1/new/pan_graph.v @@ -21,7 +21,7 @@ module pan_graph( - input basys_clk, + input basys_clk, //6p25MHz clock input is_pan, input left, input right, @@ -29,11 +29,12 @@ module pan_graph( input mouse_y, input zpos, input new_event, + input rst, input btnU, btnD, btnL, btnR, btnC, output reg signed [15:0]pan_offset_x, output reg signed [15:0]pan_offset_y, output reg [3:0]zoom_level_x, - output reg [3:0]zoom_level_y , + output reg [3:0]zoom_level_y, output reg [15:0]led ); @@ -72,42 +73,32 @@ module pan_graph( reg prevBtnC = 0; reg prevleft = 0; - //scroll wheel debouncing - reg signed [3:0] zpos_prev = 0; - reg [19:0] cooldown_counter = 0; - reg cooldown_active = 0; - //end of scroll wheel debounce + wire [1:0] scroll_dir; + scroll_led_accum scroll_test ( + .clk (basys_clk), + .rst (rst), + .new_event (new_event), + .zpos (zpos), + .scroll_dir (scroll_dir)); + //scroll up is 10, scroll down is 01, no input is 00 on the next clk cycle always @ (posedge basys_clk) begin //Zooming if (~is_pan) begin - if (cooldown_active) begin - if (cooldown_counter > 0) - cooldown_counter <= cooldown_counter - 1; - else - cooldown_active <= 0; - end -// if (new_event) begin - else if (new_event && $signed(zpos) != 0) begin // Only trigger if scroll input is non-zero - if ($signed(zpos) > zpos_prev) begin - if (right) + if (scroll_dir == 01) begin + if (right) //scroll down = zoom out - zoom_level_x = (zoom_level_x > 1) ? zoom_level_x / 2 : 1; - else zoom_level_y = (zoom_level_y > 1) ? zoom_level_y / 2 : 1; - - end - else if ($signed(zpos) < zpos_prev) begin - //scroll up = zoom in - if (right) zoom_level_x = (zoom_level_x < 8) ? zoom_level_x * 2 : 8; - else zoom_level_y = (zoom_level_y < 8) ? zoom_level_y * 2 : 8; - end - zpos_prev <= $signed(zpos); - - // Start cooldown - cooldown_active <= 1; - cooldown_counter <= 20'd1000000; // ~10ms cooldown + zoom_level_x = (zoom_level_x > 1) ? zoom_level_x / 2 : 1; + else zoom_level_y = (zoom_level_y > 1) ? zoom_level_y / 2 : 1; + end + else if (scroll_dir == 10) begin + //scroll up = zoom in + if (right) zoom_level_x = (zoom_level_x < 8) ? zoom_level_x * 2 : 8; + else zoom_level_y = (zoom_level_y < 8) ? zoom_level_y * 2 : 8; + end + //try this logic: zoom wrt y is regular scroll //if want to zoom wrt x, hold down right click if (prevBtnU & ~btnU) begin diff --git a/FDP.srcs/sources_1/new/phase_control.v b/FDP.srcs/sources_1/new/phase_control.v index 2c4be1f..c650d16 100644 --- a/FDP.srcs/sources_1/new/phase_control.v +++ b/FDP.srcs/sources_1/new/phase_control.v @@ -26,8 +26,8 @@ module phase_control( input clk_1kHz, input [12:0] one_pixel_index, input [12:0] two_pixel_index, - output [15:0] one_oled_data, - output [15:0] two_oled_data, + output reg [15:0] one_oled_data, + output reg [15:0] two_oled_data, input btnU, btnD, btnC, btnL, btnR, input back_switch, input [11:0] xpos, @@ -35,7 +35,10 @@ module phase_control( input use_mouse, input mouse_left, input mouse_middle, + input mouse_right, + input [3:0] zpos, output [15:0] led, + input rst, output [3:0] an, output [7:0] seg ); @@ -104,17 +107,19 @@ module phase_control( .back_switch(back_switch), .xpos(xpos), .ypos(ypos), + .zpos(zpos), .use_mouse(use_mouse), .mouse_left(mouse_left), .mouse_middle(mouse_middle) ); // Output selection based on active phase - assign one_oled_data = is_phase_three ? phase_three_one_oled_data : - (is_phase_two ? phase_two_oled_data : phase_one_oled_data); - - assign two_oled_data = is_phase_three ? phase_three_two_oled_data : 16'h0000; + always @ (posedge clk_100MHz) begin + one_oled_data = is_phase_three ? phase_three_one_oled_data : + (is_phase_two ? phase_two_oled_data : phase_one_oled_data); + two_oled_data = is_phase_three ? phase_three_two_oled_data : 16'h0000; + end // Controlling the seven segment display seven_seg_controller ssc( .seg(seg), diff --git a/FDP.srcs/sources_1/new/phase_three_wrapper.v b/FDP.srcs/sources_1/new/phase_three_wrapper.v index 2008715..76a4cf9 100644 --- a/FDP.srcs/sources_1/new/phase_three_wrapper.v +++ b/FDP.srcs/sources_1/new/phase_three_wrapper.v @@ -35,6 +35,7 @@ module phase_three_wrapper( input clk_100MHz, input clk_1kHz, input clk_6p25MHz, + input rst, input [12:0] one_pixel_index, input [12:0] two_pixel_index, output [15:0] one_oled_data, @@ -46,9 +47,11 @@ module phase_three_wrapper( input back_switch, input [11:0] xpos, input [11:0] ypos, + input [3:0] zpos, input use_mouse, input mouse_left, - input mouse_middle + input mouse_middle, + input new_event ); // State signals from controller @@ -195,6 +198,7 @@ module phase_three_wrapper( .btnL(0), .btnR(0), .btnC(0), + .rst(rst), .pixel_index(two_pixel_index), .coeff_a(coeff_a), .coeff_b(coeff_b), @@ -203,6 +207,7 @@ module phase_three_wrapper( .curr_x(xpos), .curr_y(ypos), .zoom_level(4'h5), // Default zoom level + .zpos(zpos), .mouse_left(mouse_left), .mouse_right(1'b0), .mouse_middle(mouse_middle), @@ -238,7 +243,10 @@ module phase_three_wrapper( .one_pixel_index(one_pixel_index), .two_pixel_index(two_pixel_index), .one_oled_data(table_one_oled_data), - .two_oled_data(table_two_oled_data) + .two_oled_data(table_two_oled_data), + .new_event(new_event), + .rst(rst), + .zpos(zpos) ); // Integral module diff --git a/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v b/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v index 779a548..84ec789 100644 --- a/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v +++ b/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v @@ -39,6 +39,9 @@ module polynomial_table_cursor_controller( input btnL, input btnR, input is_table_mode, + input new_event, + input rst, + input zpos, input use_mouse, //flip sw[0] if want to use mouse // From input_bcd_to_fp_builder_table @@ -75,6 +78,16 @@ module polynomial_table_cursor_controller( counter = 0; debounced = 1'b0; end + //for scroll wheel + wire [1:0] scroll_dir; + scroll_led_accum scroll_test ( + .clk (clk_100MHz), + .rst (rst), + .new_event (new_event), + .zpos (zpos), + .scroll_dir (scroll_dir)); + //scroll up is 10, scroll down is 01, no input is 00 on the next clk cycle + //end of scroll wheel part always @(posedge clk_100MHz) begin if (mouse_left == debounced) counter <= 0; @@ -90,6 +103,15 @@ module polynomial_table_cursor_controller( // Flag to track if on the checkmark wire on_checkmark = (cursor_col == 3'd3 && is_table_input_mode); + wire [1:0] scroll_state; + scroll_led_accum scroll_status ( + .clk (clk), + .rst (rst), + .new_event (new_event), + .zpos (zpos), + .scroll_dir (scroll_state)); + //scroll up is 10, scroll down is 01, no input is 00 on the next clk cycle + always @ (posedge clk) begin @@ -223,12 +245,12 @@ module polynomial_table_cursor_controller( // Navigation Mode - if (btnU && !prev_btnU && debounce_U == 0) begin + if ((btnU && !prev_btnU && debounce_U == 0) || (use_mouse && scroll_state == 10)) begin debounce_U <= 200; starting_x <= starting_x + 32'h00010000; // Add 1.0 in fixed point end - if (btnD && !prev_btnD && debounce_D == 0) begin + if (btnD && !prev_btnD && debounce_D == 0 || (use_mouse && scroll_state == 01)) begin debounce_D <= 200; starting_x <= starting_x - 32'h00010000; // Subtract 1.0 in fixed point end diff --git a/FDP.srcs/sources_1/new/polynomial_table_module.v b/FDP.srcs/sources_1/new/polynomial_table_module.v index a0160f7..1e577cf 100644 --- a/FDP.srcs/sources_1/new/polynomial_table_module.v +++ b/FDP.srcs/sources_1/new/polynomial_table_module.v @@ -53,7 +53,12 @@ module polynomial_table_module( // Two outgoing display data output [15:0] one_oled_data, - output [15:0] two_oled_data + output [15:0] two_oled_data, + + //for mouse stuff + input new_event, + input rst, + input zpos ); // Internal signals and states @@ -100,7 +105,10 @@ module polynomial_table_module( .cursor_col(cursor_col), .keypad_btn_pressed(keypad_btn_pressed), .keypad_selected_value(keypad_selected_value), - .starting_x(starting_x) + .starting_x(starting_x), + .new_event(new_event), + .rst(rst), + .zpos(zpos) ); // Input builder @@ -132,7 +140,7 @@ module polynomial_table_module( .input_index(input_index), .oled_data(keypad_oled_data) ); - + // Table display polynomial_table_table_display table_display( .clk(clk_6p25MHz), diff --git a/FDP.xpr b/FDP.xpr index 0a8287c..df5552b 100644 --- a/FDP.xpr +++ b/FDP.xpr @@ -3,7 +3,7 @@ - +