diff --git a/FDP.srcs/sources_1/imports/Desktop/Mouse_Control.vhd b/FDP.srcs/sources_1/imports/Desktop/Mouse_Control.vhd index abb3a62..c6cd20e 100644 --- a/FDP.srcs/sources_1/imports/Desktop/Mouse_Control.vhd +++ b/FDP.srcs/sources_1/imports/Desktop/Mouse_Control.vhd @@ -257,11 +257,15 @@ constant SAMPLE_RATE : std_logic_vector(7 downto 0) := x"28"; -- (40 samples/s) -- default maximum value for the horizontal mouse position -constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"3C0"; +--constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"3C0"; -- 1279 +constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"063"; +-- 99 MAX_X -- default maximum value for the vertical mouse position -constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"280"; +--constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"280"; -- 1023 +constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"041"; +-- 65 MAX_Y -- Mouse check tick constants constant CHECK_PERIOD_CLOCKS : integer := ((CHECK_PERIOD_MS*1000000)/(1000000000/SYSCLK_FREQUENCY_HZ)); diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0.xml b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0.xml index 1b3fd38..0fe8a4b 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0.xml +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0.xml @@ -1536,7 +1536,7 @@ GENtimestamp - Tue Apr 08 17:48:22 UTC 2025 + Sat Apr 12 14:31:47 UTC 2025 outputProductCRC diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v index 9cfe00c..30ef658 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:22 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v} +// Date : Sat Apr 12 22:31:47 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.v // Design : blk_mem_gen_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl index 5b91ee6..6ec96a7 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 --- Date : Wed Apr 9 01:48:22 2025 --- Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim {C:/Uni --- Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl} +-- Date : Sat Apr 12 22:31:47 2025 +-- Host : Daniel running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_sim_netlist.vhdl -- Design : blk_mem_gen_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v index a734cca..90885db 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:22 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v} +// Date : Sat Apr 12 22:31:47 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_0_1/blk_mem_gen_0_stub.v // Design : blk_mem_gen_0 // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcpg236-1 diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml index b04cc4e..ff2aa08 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const.xml @@ -1498,11 +1498,11 @@ GENtimestamp - Fri Apr 11 05:20:05 UTC 2025 + Sat Apr 12 14:30:57 UTC 2025 outputProductCRC - 8:1a76e1f2 + 8:8ad6b4c2 @@ -1518,11 +1518,11 @@ GENtimestamp - Fri Apr 11 05:20:05 UTC 2025 + Sat Apr 12 14:30:57 UTC 2025 outputProductCRC - 8:1a76e1f2 + 8:8ad6b4c2 @@ -1536,11 +1536,11 @@ GENtimestamp - Fri Apr 11 05:20:16 UTC 2025 + Sat Apr 12 14:32:15 UTC 2025 outputProductCRC - 8:1a76e1f2 + 8:8ad6b4c2 diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v index 4200cea..8dcc78d 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Sat Mar 29 17:09:05 2025 -// Host : DESKTOP-4JEN3JE running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top blk_mem_gen_const -prefix -// blk_mem_gen_const_ blk_mem_gen_const_sim_netlist.v +// Date : Sat Apr 12 22:32:15 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.v // Design : blk_mem_gen_const // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -192,6 +192,7 @@ module blk_mem_gen_const .web(1'b0)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module blk_mem_gen_const_blk_mem_gen_generic_cstr (douta, addra, @@ -576,6 +577,7 @@ module blk_mem_gen_const_blk_mem_gen_generic_cstr .wea(wea)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_mux" *) module blk_mem_gen_const_blk_mem_gen_mux (douta, p_7_out, @@ -1412,6 +1414,7 @@ module blk_mem_gen_const_blk_mem_gen_mux .R(1'b0)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module blk_mem_gen_const_blk_mem_gen_prim_width (\douta[0] , clka, @@ -2263,6 +2266,7 @@ module blk_mem_gen_const_blk_mem_gen_prim_width__parameterized9 .wea(wea)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) module blk_mem_gen_const_blk_mem_gen_prim_wrapper_init (\douta[0] , clka, @@ -8620,6 +8624,7 @@ module blk_mem_gen_const_blk_mem_gen_prim_wrapper_init__parameterized9 .O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 )); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_top" *) module blk_mem_gen_const_blk_mem_gen_top (douta, addra, @@ -8670,7 +8675,7 @@ endmodule (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50890" *) (* C_WRITE_DEPTH_B = "50890" *) (* C_WRITE_MODE_A = "READ_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "16" *) (* C_WRITE_WIDTH_B = "16" *) -(* C_XDEVICEFAMILY = "artix7" *) (* downgradeipidentifiedwarnings = "yes" *) +(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_4_1" *) (* downgradeipidentifiedwarnings = "yes" *) module blk_mem_gen_const_blk_mem_gen_v8_4_1 (clka, rsta, @@ -8904,6 +8909,7 @@ module blk_mem_gen_const_blk_mem_gen_v8_4_1 .wea(wea)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_v8_4_1_synth" *) module blk_mem_gen_const_blk_mem_gen_v8_4_1_synth (douta, addra, diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl index 1866df9..7792e05 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 --- Date : Sat Mar 29 17:09:05 2025 --- Host : DESKTOP-4JEN3JE running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top blk_mem_gen_const -prefix --- blk_mem_gen_const_ blk_mem_gen_const_sim_netlist.vhdl +-- Date : Sat Apr 12 22:32:15 2025 +-- Host : Daniel running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_sim_netlist.vhdl -- Design : blk_mem_gen_const -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -59,6 +59,8 @@ entity blk_mem_gen_const_blk_mem_gen_mux is \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_mux : entity is "blk_mem_gen_mux"; end blk_mem_gen_const_blk_mem_gen_mux; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_mux is @@ -1005,6 +1007,8 @@ entity blk_mem_gen_const_blk_mem_gen_prim_wrapper_init is dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end blk_mem_gen_const_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_prim_wrapper_init is @@ -7612,6 +7616,8 @@ entity blk_mem_gen_const_blk_mem_gen_prim_width is dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end blk_mem_gen_const_blk_mem_gen_prim_width; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_prim_width is @@ -8413,6 +8419,8 @@ entity blk_mem_gen_const_blk_mem_gen_generic_cstr is dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end blk_mem_gen_const_blk_mem_gen_generic_cstr; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_generic_cstr is @@ -9028,6 +9036,8 @@ entity blk_mem_gen_const_blk_mem_gen_top is dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_top : entity is "blk_mem_gen_top"; end blk_mem_gen_const_blk_mem_gen_top; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_top is @@ -9053,6 +9063,8 @@ entity blk_mem_gen_const_blk_mem_gen_v8_4_1_synth is dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_v8_4_1_synth : entity is "blk_mem_gen_v8_4_1_synth"; end blk_mem_gen_const_blk_mem_gen_v8_4_1_synth; architecture STRUCTURE of blk_mem_gen_const_blk_mem_gen_v8_4_1_synth is @@ -9282,6 +9294,8 @@ entity blk_mem_gen_const_blk_mem_gen_v8_4_1 is attribute C_WRITE_WIDTH_B of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is 16; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "artix7"; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "blk_mem_gen_v8_4_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of blk_mem_gen_const_blk_mem_gen_v8_4_1 : entity is "yes"; end blk_mem_gen_const_blk_mem_gen_v8_4_1; diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v index 3d876c4..09be8ee 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Sat Mar 29 17:09:05 2025 -// Host : DESKTOP-4JEN3JE running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top blk_mem_gen_const -prefix -// blk_mem_gen_const_ blk_mem_gen_const_stub.v +// Date : Sat Apr 12 22:32:15 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_const/blk_mem_gen_const_stub.v // Design : blk_mem_gen_const // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcpg236-1 diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml index d580b64..d52ce08 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img.xml @@ -1498,11 +1498,11 @@ GENtimestamp - Fri Apr 11 05:20:06 UTC 2025 + Sat Apr 12 14:30:57 UTC 2025 outputProductCRC - 8:2f47c7ae + 8:c38ac6e6 @@ -1518,11 +1518,11 @@ GENtimestamp - Fri Apr 11 05:20:06 UTC 2025 + Sat Apr 12 14:30:57 UTC 2025 outputProductCRC - 8:2f47c7ae + 8:c38ac6e6 @@ -1536,11 +1536,11 @@ GENtimestamp - Fri Apr 11 05:20:16 UTC 2025 + Sat Apr 12 14:31:47 UTC 2025 outputProductCRC - 8:2f47c7ae + 8:c38ac6e6 diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v index 563432b..3d06a60 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Sat Mar 29 17:07:55 2025 -// Host : DESKTOP-4JEN3JE running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top blk_mem_gen_img -prefix -// blk_mem_gen_img_ blk_mem_gen_img_sim_netlist.v +// Date : Sat Apr 12 22:31:47 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.v // Design : blk_mem_gen_img // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -198,6 +198,7 @@ module blk_mem_gen_img .web(1'b0)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module blk_mem_gen_img_blk_mem_gen_generic_cstr (doutb, clka, @@ -232,6 +233,7 @@ module blk_mem_gen_img_blk_mem_gen_generic_cstr .wea(wea)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module blk_mem_gen_img_blk_mem_gen_prim_width (doutb, clka, @@ -266,6 +268,7 @@ module blk_mem_gen_img_blk_mem_gen_prim_width .wea(wea)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) module blk_mem_gen_img_blk_mem_gen_prim_wrapper_init (doutb, clka, @@ -435,6 +438,7 @@ module blk_mem_gen_img_blk_mem_gen_prim_wrapper_init .WEBWE({1'b0,1'b0,1'b0,1'b0})); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_top" *) module blk_mem_gen_img_blk_mem_gen_top (doutb, clka, @@ -493,7 +497,7 @@ endmodule (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "784" *) (* C_WRITE_DEPTH_B = "784" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "1" *) (* C_WRITE_WIDTH_B = "1" *) -(* C_XDEVICEFAMILY = "artix7" *) (* downgradeipidentifiedwarnings = "yes" *) +(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_4_1" *) (* downgradeipidentifiedwarnings = "yes" *) module blk_mem_gen_img_blk_mem_gen_v8_4_1 (clka, rsta, @@ -689,6 +693,7 @@ module blk_mem_gen_img_blk_mem_gen_v8_4_1 .wea(wea)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_v8_4_1_synth" *) module blk_mem_gen_img_blk_mem_gen_v8_4_1_synth (doutb, clka, diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl index 5506fd8..7062ff6 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 --- Date : Sat Mar 29 17:07:55 2025 --- Host : DESKTOP-4JEN3JE running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top blk_mem_gen_img -prefix --- blk_mem_gen_img_ blk_mem_gen_img_sim_netlist.vhdl +-- Date : Sat Apr 12 22:31:47 2025 +-- Host : Daniel running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_sim_netlist.vhdl -- Design : blk_mem_gen_img -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -24,6 +24,8 @@ entity blk_mem_gen_img_blk_mem_gen_prim_wrapper_init is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end blk_mem_gen_img_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_prim_wrapper_init is @@ -209,6 +211,8 @@ entity blk_mem_gen_img_blk_mem_gen_prim_width is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end blk_mem_gen_img_blk_mem_gen_prim_width; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_prim_width is @@ -238,6 +242,8 @@ entity blk_mem_gen_img_blk_mem_gen_generic_cstr is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end blk_mem_gen_img_blk_mem_gen_generic_cstr; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_generic_cstr is @@ -267,6 +273,8 @@ entity blk_mem_gen_img_blk_mem_gen_top is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_top : entity is "blk_mem_gen_top"; end blk_mem_gen_img_blk_mem_gen_top; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_top is @@ -296,6 +304,8 @@ entity blk_mem_gen_img_blk_mem_gen_v8_4_1_synth is addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_v8_4_1_synth : entity is "blk_mem_gen_v8_4_1_synth"; end blk_mem_gen_img_blk_mem_gen_v8_4_1_synth; architecture STRUCTURE of blk_mem_gen_img_blk_mem_gen_v8_4_1_synth is @@ -527,6 +537,8 @@ entity blk_mem_gen_img_blk_mem_gen_v8_4_1 is attribute C_WRITE_WIDTH_B of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is 1; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is "artix7"; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is "blk_mem_gen_v8_4_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of blk_mem_gen_img_blk_mem_gen_v8_4_1 : entity is "yes"; end blk_mem_gen_img_blk_mem_gen_v8_4_1; diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v index 29953ec..befe186 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Sat Mar 29 17:07:55 2025 -// Host : DESKTOP-4JEN3JE running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top blk_mem_gen_img -prefix -// blk_mem_gen_img_ blk_mem_gen_img_stub.v +// Date : Sat Apr 12 22:31:47 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_img/blk_mem_gen_img_stub.v // Design : blk_mem_gen_img // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcpg236-1 diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter.xml b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter.xml index 5deafb9..a636067 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter.xml +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter.xml @@ -1536,7 +1536,7 @@ GENtimestamp - Tue Apr 08 17:48:22 UTC 2025 + Sat Apr 12 14:31:47 UTC 2025 outputProductCRC diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.v b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.v index 25e1d55..f9dd100 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:22 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.v} +// Date : Sat Apr 12 22:31:47 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.v // Design : blk_mem_gen_inter // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.vhdl b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.vhdl index db296fd..a59065a 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.vhdl +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 --- Date : Wed Apr 9 01:48:22 2025 --- Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim {C:/Uni --- Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.vhdl} +-- Date : Sat Apr 12 22:31:47 2025 +-- Host : Daniel running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_sim_netlist.vhdl -- Design : blk_mem_gen_inter -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. diff --git a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_stub.v b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_stub.v index fdf16dc..b2fb495 100644 --- a/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_stub.v +++ b/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -// Date : Wed Apr 9 01:48:22 2025 -// Host : DESKTOP-DVNBCH1 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub {C:/Uni -// Stuff/Y2S2/EE2026/Final_project/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_stub.v} +// Date : Sat Apr 12 22:31:47 2025 +// Host : Daniel running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// C:/Users/danan/Documents/Y1_S2_mods/EE2026/EE2026-FPGA-Design-Project/FDP.srcs/sources_1/ip/blk_mem_gen_inter/blk_mem_gen_inter_stub.v // Design : blk_mem_gen_inter // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcpg236-1 diff --git a/FDP.srcs/sources_1/new/Top_Student.v b/FDP.srcs/sources_1/new/Top_Student.v index 2236e27..07aeab3 100644 --- a/FDP.srcs/sources_1/new/Top_Student.v +++ b/FDP.srcs/sources_1/new/Top_Student.v @@ -23,14 +23,67 @@ module Top_Student ( output [7:0] seg, output [3:0] an ); - - // 6.25MHz clock for OLED displays + // 6.25MHz clock for OLED displays wire clk_6p25MHz; flexible_clock_divider clk_6p25MHz_gen( .main_clock(basys_clock), .ticks(7), .output_clock(clk_6p25MHz) - ); + ); + //end of mouse part + //mouse part + // Default input values for the mouse_module + wire [11:0] value; + assign value = 12'b0; // Default value is 0 (origin) + + wire setx; + assign setx = 1'b0; // No update command, keep current position + + wire sety; + assign sety = 1'b0; // No update command, keep current position + + wire setmax_x; + assign setmax_x= 1'b0; // Do not update max_x + + wire setmax_y; + assign setmax_y = 1'b0; // Do not update max_y + wire [11:0] xpos; + wire [11:0] ypos; + wire [3:0] zpos; + wire left; + wire middle; + wire right; + wire new_event; + wire rst; // Reset signal + mouse_module unit_0 ( + .clk (clk_6p25MHz), + .rst (rst), + .value (value), + .setmax_x (setmax_x), + .setmax_y (setmax_y), + .setx (setx), + .sety (sety), + .ps2_clk (ps2_clk), + .ps2_data (ps2_data), + .xpos (xpos), + .ypos (ypos), + .zpos (zpos), + .left (left), + .middle (middle), + .right (right), + .new_event (new_event) + ); + + + //part that tracks the number of scroll wheel inputs +// wire [1:0] scroll_leds; +// scroll_led_accum scroll_test ( +// .clk (clk_6p25MHz), +// .rst (rst), +// .new_event (new_event), +// .zpos (zpos), +// .wow (scroll_leds)); + //end of part that tracks the number of scroll wheel inputs, shift this around if needed // 1kHz clock for cursor_controller wire clk_1kHz; @@ -46,12 +99,12 @@ module Top_Student ( wire [12:0]JB_pixel_index; wire one_sending_pixels; wire [15:0]JB_oled_data; - wire [12:0] JA_rotated_pixel_index; // Second OLED display unit wire two_frame_begin; wire two_sample_pixel; wire [12:0]JA_pixel_index; + wire [12:0] JA_rotated_pixel_index; wire two_sending_pixels; wire [15:0]JA_oled_data; @@ -88,14 +141,14 @@ module Top_Student ( .vccen(JA[6]), .pmoden(JA[7]) ); - + wire [15:0] JB_bg_data; phase_control phase( .clk_100MHz(basys_clock), .clk_1kHz(clk_1kHz), .clk_6p25MHz(clk_6p25MHz), .one_pixel_index(JB_pixel_index), .two_pixel_index(JA_rotated_pixel_index), - .one_oled_data(JB_oled_data), + .one_oled_data(JB_bg_data), .two_oled_data(JA_oled_data), .btnU(btnU), .btnD(btnD), @@ -103,11 +156,36 @@ module Top_Student ( .btnL(btnL), .btnR(btnR), .back_switch(sw[15]), + .rst(rst), .led(led), .an(an), .seg(seg), - .pan_zoom_toggle(sw[14]) + .xpos(xpos), + .ypos(ypos), + .pan_zoom_toggle(sw[14]), + .mouseonJB(~sw[5]), + .use_mouse(sw[3]), + .is_pan_mouse(sw[5]), +// .pan_zoom_toggle(sw[14]), + .mouse_left(left), + .mouse_middle(middle), + .mouse_right(right), + .new_event(new_event), + .zpos(zpos) //here, scroll_leds starts at 0, then if we scroll up is 0001, + //then 0011, 0111, 1111, scroll back down is 1111, 0111, 0011, 0001, 0000 ); - + wire [6:0] curr_x, curr_y; rotate_180_for_JA rotate180(JA_pixel_index, JA_rotated_pixel_index); + + on_screen_cursor unit_1 (.basys_clock(clk_6p25MHz), + .pixel_index(JB_pixel_index), + .graph_mode_check(sw[3]), //change this if ncessary, when to use the mouse and wben not to use the mouse + .value(value),.setx(setx), + .sety(sety), + .setmax_x(setmax_x),.setmax_y(setmax_y), + .xpos(xpos), .ypos(ypos),.bg_data(JB_bg_data), + .oled_data(JB_oled_data), + .cursor_x(curr_x), .cursor_y(curr_y)); + //curr_x and curr_y is an output that stores the value of the current cursor position in the screen + endmodule diff --git a/FDP.srcs/sources_1/new/arithmetic_backend.v b/FDP.srcs/sources_1/new/arithmetic_backend.v index e63da04..86a3258 100644 --- a/FDP.srcs/sources_1/new/arithmetic_backend.v +++ b/FDP.srcs/sources_1/new/arithmetic_backend.v @@ -38,7 +38,7 @@ parameter ADD = 2'd0; parameter SUBTRACT = 2'd1; parameter MULTIPLY = 2'd2; - parameter DIVIDE = 2'd3; + parameter DIVIDE = 2'd3; // Flag for first calculation reg is_first_calc = 1; diff --git a/FDP.srcs/sources_1/new/arithmetic_cursor_controller.v b/FDP.srcs/sources_1/new/arithmetic_cursor_controller.v index 1ab6ef5..be2dd42 100644 --- a/FDP.srcs/sources_1/new/arithmetic_cursor_controller.v +++ b/FDP.srcs/sources_1/new/arithmetic_cursor_controller.v @@ -1,5 +1,12 @@ module arithmetic_cursor_controller( input clk, + input clk_100MHz, + input clk_6p25MHz, + input mouse_left, + input use_mouse, + input middle, + input [11:0]xpos, + input [11:0]ypos, input reset, input btnC, input btnU, @@ -30,6 +37,34 @@ module arithmetic_cursor_controller( reg [7:0] debounce_D = 0; reg [7:0] debounce_L = 0; reg [7:0] debounce_R = 0; + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] ctr; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + initial begin + ctr = 0; + debounced = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + ctr <= 0; + else begin + ctr <= ctr + 1; + if (ctr >= DEBOUNCE_DELAY) debounced <= mouse_left; + end + end + reg mouse_left_prev; + initial begin mouse_left_prev = 1'b0; end + wire [6:0] mouse_xpos, mouse_ypos; + +//get current coordinates of the mouse + mouse_coordinate_extractor coord_extr( + clk_6p25MHz, //6p25MHz clock + xpos, // 12-bit mouse x position + ypos, // 12-bit mouse y position + mouse_xpos, mouse_ypos); + //end of getting current coordinates of the mouse + // Waiting counter reg [8:0] counter = 9'd500; @@ -77,6 +112,57 @@ module arithmetic_cursor_controller( if (!is_operand_mode) begin if (counter == 0) begin + if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 0 && mouse_ypos <= 15) begin + cursor_row_keypad <= 0; + cursor_col_keypad <= 0; + end + else if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 16 && mouse_ypos <= 31) begin + cursor_row_keypad <= 1; + cursor_col_keypad <= 0; + end + else if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 32 && mouse_ypos <= 47) begin + cursor_row_keypad <= 2; + cursor_col_keypad <= 0; + end + else if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 48 && mouse_ypos <= 63) begin + cursor_row_keypad <= 3; + cursor_col_keypad <= 0; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 0 && mouse_ypos <= 15) begin + cursor_row_keypad <= 0; + cursor_col_keypad <= 1; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 16 && mouse_ypos <= 31) begin + cursor_row_keypad <= 1; + cursor_col_keypad <= 1; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 32 && mouse_ypos <= 47) begin + cursor_row_keypad <= 2; + cursor_col_keypad <= 1; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 48 && mouse_ypos <= 63) begin + cursor_row_keypad <= 3; + cursor_col_keypad <= 1; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 0 && mouse_ypos <= 15) begin + cursor_row_keypad <= 0; + cursor_col_keypad <= 2; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 16 && mouse_ypos <= 31) begin + cursor_row_keypad <= 1; + cursor_col_keypad <= 2; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 32 && mouse_ypos <= 47) begin + cursor_row_keypad <= 2; + cursor_col_keypad <= 2; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 48 && mouse_ypos <= 63) begin + cursor_row_keypad <= 3; + cursor_col_keypad <= 2; + end + else if (use_mouse) begin //this is the checkmark side + cursor_col_keypad <= 3; + end // Up button processing if (btnU && !prev_btnU && debounce_U == 0) begin if (cursor_row_keypad > 0 && !on_checkmark) begin @@ -115,7 +201,7 @@ module arithmetic_cursor_controller( end // Center (Selection) - if (btnC && !prev_btnC && debounce_C == 0) begin + if (btnC && !prev_btnC && debounce_C == 0 || (use_mouse && debounced && !mouse_left_prev)) begin keypad_btn_pressed <= 1; counter <= 500; if (on_checkmark) begin @@ -141,11 +227,29 @@ module arithmetic_cursor_controller( end end else begin - counter <= counter -1; + counter <= counter - 1; end end else begin // OPERAND MODE + + if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 47 && mouse_ypos <= 31 && mouse_ypos >= 0) begin //for + + cursor_row_operand <= 0; + cursor_col_operand <= 0; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 95 && mouse_ypos <= 31 && mouse_ypos >= 0) begin //for - + cursor_row_operand <= 0; + cursor_col_operand <= 1; + end + else if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 47 && mouse_ypos <= 63 && mouse_ypos >= 32) begin //for x + cursor_row_operand <= 1; + cursor_col_operand <= 0; + end + else if (use_mouse) begin //for divide + cursor_row_operand <= 1; + cursor_col_operand <= 1; + end + // Up button handling if (btnU && !prev_btnU && debounce_U == 0) begin if (cursor_row_operand > 0) begin @@ -179,7 +283,7 @@ module arithmetic_cursor_controller( end // Center button handling (selection) - if (btnC && !prev_btnC && debounce_C == 0) begin + if (btnC && !prev_btnC && debounce_C == 0 || (use_mouse && debounced && !mouse_left_prev)) begin operand_btn_pressed <= 1; // Determine selected operand based on cursor position @@ -202,6 +306,7 @@ module arithmetic_cursor_controller( prev_btnL <= btnL; prev_btnR <= btnR; prev_btnC <= btnC; + mouse_left_prev <= debounced; end end endmodule \ No newline at end of file diff --git a/FDP.srcs/sources_1/new/arithmetic_module.v b/FDP.srcs/sources_1/new/arithmetic_module.v index 55aca21..38f8041 100644 --- a/FDP.srcs/sources_1/new/arithmetic_module.v +++ b/FDP.srcs/sources_1/new/arithmetic_module.v @@ -24,6 +24,7 @@ module arithmetic_module( // Clock inputs input clk_6p25MHz, input clk_1kHz, + input clk_100MHz, // Button inputs input btnC, btnU, btnD, btnL, btnR, @@ -33,11 +34,11 @@ module arithmetic_module( input is_arithmetic_mode, // Mouse inputs (for future compatibility) KIV Daniel - input [6:0] xpos, - input [6:0] ypos, + input [11:0] xpos, + input [11:0] ypos, input use_mouse, input mouse_left, - input mouse_middle, + input middle, // OLED outputs input [12:0] one_pixel_index, @@ -70,6 +71,13 @@ module arithmetic_module( // Cursor controller for handling user input arithmetic_cursor_controller cursor_ctrl( .clk(clk_1kHz), + .clk_100MHz(clk_100MHz), + .clk_6p25MHz(clk_6p25MHz), + .use_mouse(use_mouse), + .mouse_left(mouse_left), + .middle(middle), + .xpos(xpos), + .ypos(ypos), .reset(reset || !is_arithmetic_mode), .btnC(is_arithmetic_mode ? btnC : 1'b0), // Only process buttons when in arithmetic mode .btnU(is_arithmetic_mode ? btnU : 1'b0), diff --git a/FDP.srcs/sources_1/new/graph_display_cached.v b/FDP.srcs/sources_1/new/graph_display_cached.v index 0fab8a7..cb501b3 100644 --- a/FDP.srcs/sources_1/new/graph_display_cached.v +++ b/FDP.srcs/sources_1/new/graph_display_cached.v @@ -44,7 +44,6 @@ module graph_display_cached( input pan_zoom_toggle ); - // Constants parameter SCREEN_WIDTH = 96; parameter SCREEN_HEIGHT = 64; @@ -111,7 +110,7 @@ module graph_display_cached( .computation_complete(compute_complete), .is_graph(1) ); - + // Connect pan_graph module for pan and zoom functionality pan_graph panning_unit( .clk(clk), diff --git a/FDP.srcs/sources_1/new/integral_cursor_controller.v b/FDP.srcs/sources_1/new/integral_cursor_controller.v index 4998baf..1b2910d 100644 --- a/FDP.srcs/sources_1/new/integral_cursor_controller.v +++ b/FDP.srcs/sources_1/new/integral_cursor_controller.v @@ -22,12 +22,19 @@ module integral_cursor_controller( input clk, + input clk_6p25MHz, + input clk_100MHz, + input use_mouse, input reset, input btnC, input btnU, input btnD, input btnL, input btnR, + input middle, + input [11:0] xpos, + input [11:0] ypos, + input mouse_left, input is_integral_mode, input is_integral_input_mode, output reg [1:0] cursor_row = 0, @@ -42,6 +49,36 @@ module integral_cursor_controller( reg prev_btnD = 0; reg prev_btnL = 0; reg prev_btnR = 0; + + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] counter; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + initial begin + counter = 0; + debounced = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + counter <= 0; + else begin + counter <= counter + 1; + if (counter >= DEBOUNCE_DELAY) debounced <= mouse_left; + + end + end + reg mouse_left_prev; + initial begin mouse_left_prev = 1'b0; end + wire [6:0] mouse_xpos, mouse_ypos; + + //get current coordinates of the mouse + mouse_coordinate_extractor coord_extr( + clk_6p25MHz, //6p25MHz clock + xpos, // 12-bit mouse x position + ypos, // 12-bit mouse y position + mouse_xpos, mouse_ypos); + //end of getting current coordinates of the mouse + // Debouncing counters reg [7:0] debounce_C = 0; @@ -96,7 +133,63 @@ module integral_cursor_controller( end debounce_U <= 200; end - + + if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 0 && mouse_ypos <= 15) begin // for 7 + cursor_row <= 0; + cursor_col <= 0; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 0 && mouse_ypos <= 15) begin //for 8 + cursor_row <= 0; + cursor_col <= 1; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 0 && mouse_ypos <= 15) begin //for 9 + cursor_row <= 0; + cursor_col <= 2; + end + else if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 16 && mouse_ypos <= 31) begin //for 4 + cursor_row <= 1; + cursor_col <= 0; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 16 && mouse_ypos <= 31) begin //for 5 + cursor_row <= 1; + cursor_col <= 1; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 16 && mouse_ypos <= 31) begin //for 6 + cursor_row <= 1; + cursor_col <= 2; + end + else if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 32 && mouse_ypos <= 47) begin //for 1 + cursor_row <= 2; + cursor_col <= 0; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 32 && mouse_ypos <= 47) begin //for 2 + cursor_row <= 2; + cursor_col <= 1; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 32 && mouse_ypos <= 47) begin //for 3 + cursor_row <= 2; + cursor_col <= 2; + end + else if (use_mouse && mouse_xpos >= 0 && mouse_xpos <= 23 && mouse_ypos >= 48 && mouse_ypos <= 63) begin //for 0 + cursor_row <= 3; + cursor_col <= 0; + end + else if (use_mouse && mouse_xpos >= 24 && mouse_xpos <= 47 && mouse_ypos >= 48 && mouse_ypos <= 63) begin //for . + cursor_row <= 3; + cursor_col <= 1; + end + else if (use_mouse && mouse_xpos >= 48 && mouse_xpos <= 71 && mouse_ypos >= 48 && mouse_ypos <= 63) begin //for - + cursor_row <= 3; + cursor_col <= 2; + end + else if (use_mouse) begin //on equal sign/checkmark + cursor_col <= 3'd3; + end + + + + + // Down if (btnD && !prev_btnD && debounce_D == 0) begin if (cursor_row < 3 && !on_checkmark) begin @@ -127,7 +220,7 @@ module integral_cursor_controller( end // Center (Selection) - if (btnC && !prev_btnC && debounce_C == 0) begin + if (btnC && !prev_btnC && debounce_C == 0 || (use_mouse && debounced && !mouse_left_prev)) begin keypad_btn_pressed <= 1; if (on_checkmark) begin @@ -162,6 +255,8 @@ module integral_cursor_controller( prev_btnL <= btnL; prev_btnR <= btnR; prev_btnC <= btnC; + mouse_left_prev <= debounced; + end else begin count <= count - 1; diff --git a/FDP.srcs/sources_1/new/integral_module.v b/FDP.srcs/sources_1/new/integral_module.v index fc0f8cf..5b3ace8 100644 --- a/FDP.srcs/sources_1/new/integral_module.v +++ b/FDP.srcs/sources_1/new/integral_module.v @@ -24,7 +24,11 @@ module integral_module( // Clock inputs input clk_6p25MHz, input clk_1kHz, - + input clk_100MHz, + input [11:0] ypos, xpos, + input mouse_left, + input use_mouse, + input middle, // Button inputs input btnC, btnU, btnD, btnL, btnR, @@ -117,6 +121,13 @@ module integral_module( // Cursor controller integral_cursor_controller cursor_ctrl( .clk(clk_1kHz), + .clk_6p25MHz(clk_6p25MHz), + .clk_100MHz(clk_100MHz), + .xpos(xpos), + .ypos(ypos), + .mouse_left(mouse_left), + .use_mouse(use_mouse), + .middle(middle), .reset(reset || !is_integral_mode), .btnC(is_integral_mode ? btnC : 1'b0), .btnU(is_integral_mode ? btnU : 1'b0), diff --git a/FDP.srcs/sources_1/new/mouse_coordinate_extractor.v b/FDP.srcs/sources_1/new/mouse_coordinate_extractor.v index bc3c6ab..8f19824 100644 --- a/FDP.srcs/sources_1/new/mouse_coordinate_extractor.v +++ b/FDP.srcs/sources_1/new/mouse_coordinate_extractor.v @@ -21,7 +21,7 @@ module mouse_coordinate_extractor( - input basys_clock, + input basys_clock, //6p25MHz clock input [11:0] xpos, // 12-bit mouse x position input [11:0] ypos, // 12-bit mouse y position output reg [6:0] mouse_x, // 7-bit mouse x (0-95) diff --git a/FDP.srcs/sources_1/new/mouse_module.v b/FDP.srcs/sources_1/new/mouse_module.v index ffa4bf5..8b1a7e2 100644 --- a/FDP.srcs/sources_1/new/mouse_module.v +++ b/FDP.srcs/sources_1/new/mouse_module.v @@ -62,5 +62,7 @@ module mouse_module ( .ps2_clk (ps2_clk), .ps2_data (ps2_data) ); + + endmodule \ No newline at end of file diff --git a/FDP.srcs/sources_1/new/on_screen_cursor.v b/FDP.srcs/sources_1/new/on_screen_cursor.v index de128a4..0064017 100644 --- a/FDP.srcs/sources_1/new/on_screen_cursor.v +++ b/FDP.srcs/sources_1/new/on_screen_cursor.v @@ -105,4 +105,4 @@ output reg [6:0] cursor_y end -endmodule +endmodule \ No newline at end of file diff --git a/FDP.srcs/sources_1/new/phase_control.v b/FDP.srcs/sources_1/new/phase_control.v index d8d331f..5b9060e 100644 --- a/FDP.srcs/sources_1/new/phase_control.v +++ b/FDP.srcs/sources_1/new/phase_control.v @@ -36,9 +36,15 @@ module phase_control( input use_mouse, input mouse_left, input mouse_middle, + input mouse_right, + input [3:0] zpos, + input mouseonJB, output [15:0] led, + input rst, output [3:0] an, - output [7:0] seg + output [7:0] seg, + input new_event, + input is_pan_mouse ); // Phase state signals @@ -60,6 +66,7 @@ module phase_control( // Instantiate phase one wrapper phase_one_wrapper phase_one( + .clk_100MHz(clk_100MHz), .clk_6p25MHz(clk_6p25MHz), .clk_1kHz(clk_1kHz), .pixel_index(one_pixel_index), @@ -70,7 +77,12 @@ module phase_control( .btnL(btnL), .is_phase_two(is_phase_two), .is_phase_three(is_phase_three), - .back_switch(back_switch) + .back_switch(back_switch), + .xpos(xpos), + .ypos(ypos), + .use_mouse(use_mouse), + .mouse_left(mouse_left), + .middle(mouse_middle) ); // Instantiate phase two wrapper @@ -87,7 +99,13 @@ module phase_control( .is_phase_three(is_phase_three), .is_arithmetic_mode(is_arithmetic_mode), .is_getting_coefficients(is_getting_coefficients), - .back_switch(back_switch) + .back_switch(back_switch), + .xpos(xpos), + .ypos(ypos), + .use_mouse(use_mouse), + .mouse_left(mouse_left), + .clk_100MHz(clk_100MHz), + .middle(mouse_middle) ); // Instantiate phase three wrapper @@ -111,13 +129,19 @@ module phase_control( .back_switch(back_switch), .xpos(xpos), .ypos(ypos), + .zpos(zpos), + .mouseonJB(mouseonJB), + .is_pan_mouse(is_pan_mouse), .use_mouse(use_mouse), .mouse_left(mouse_left), .overflow_flag(overflow_flag), .integration_mode(is_integration_mode), - .plot_mode(is_plot_mode) + .plot_mode(is_plot_mode), + .mouse_right(mouse_right), + .middle(mouse_middle), + .new_event(new_event) ); - + wire [3:0] seven_segment_mode; // Output selection based on active phase assign one_oled_data = is_phase_three ? phase_three_one_oled_data : (is_phase_two ? phase_two_oled_data : phase_one_oled_data); diff --git a/FDP.srcs/sources_1/new/phase_one_menu_controller.v b/FDP.srcs/sources_1/new/phase_one_menu_controller.v index 03ca4a9..ac46bb2 100644 --- a/FDP.srcs/sources_1/new/phase_one_menu_controller.v +++ b/FDP.srcs/sources_1/new/phase_one_menu_controller.v @@ -23,12 +23,18 @@ This module handles both the cursor logic and some state transition logic */ module phase_one_menu_controller( + input clk_100MHz, + input clk_6p25MHz, input clock, input btnU, btnD, btnC, btnL, output reg cursor_row, output reg is_phase_two, input is_phase_three, - input back_switch + input back_switch, + input [11:0] xpos, ypos, + input use_mouse, + input mouse_left, + input middle ); // Previous button states for debouncing @@ -42,15 +48,64 @@ module phase_one_menu_controller( reg [7:0] debounce_U = 0; reg [7:0] debounce_D = 0; reg [7:0] debounce_L = 0; - + + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] counter; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + + reg mouse_left_prev; + //debouncing for middle mouse button + reg [21:0] middle_counter; // Counter for debounce delay (needs enough bits) + reg debounced_middle; // Stores the debounced state + initial begin + middle_counter = 0; + debounced_middle = 1'b0; + end + always @(posedge clk_100MHz) begin + if (middle == debounced_middle) + middle_counter <= 0; + else begin + middle_counter <= middle_counter + 1; + if (middle_counter >= DEBOUNCE_DELAY) debounced_middle <= middle; + + end + end + reg mouse_middle_prev; + initial begin mouse_middle_prev = 1'b0; end + + wire [6:0] curr_x, curr_y; + + + //get current coordinates of the mouse + mouse_coordinate_extractor coord_extr( + clk_6p25MHz, //6p25MHz clock + xpos, // 12-bit mouse x position + ypos, // 12-bit mouse y position + curr_x, curr_y); + //end of getting current coordinates of the mouse + initial begin cursor_row <= 0; is_phase_two <= 0; + mouse_left_prev = 1'b0; + counter = 0; + debounced = 1'b0; end reg current_state = 0; localparam START = 0; localparam WAIT_TO_GO_BACK = 1; + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + counter <= 0; + else begin + counter <= counter + 1; + if (counter >= DEBOUNCE_DELAY) debounced <= mouse_left; + + end + end + //end of LMB debouncing always @ (posedge clock) begin // Decrement debounce counters if active @@ -64,6 +119,25 @@ module phase_one_menu_controller( START: begin if (!is_phase_two) begin // Up Down movement + if (use_mouse) begin + if (curr_x >= 35 && curr_x <= 60 && curr_y >= 34 && curr_y <= 44) begin + cursor_row <= 0; + if (debounced && !mouse_left_prev) begin + if (!cursor_row) begin + is_phase_two <= 1; + current_state <= WAIT_TO_GO_BACK; end + end + end + else if (curr_x >= 35 && curr_x <= 60 && curr_y <= 56 && curr_y >= 46) begin + cursor_row <= 1; + if (debounced && !mouse_left_prev) begin + if (!cursor_row) begin + is_phase_two <= 1; + current_state <= WAIT_TO_GO_BACK; end + end + end + end + if (btnU && !prev_btnU && debounce_U == 0) begin cursor_row <= ~cursor_row; debounce_U <= 200; @@ -89,7 +163,7 @@ module phase_one_menu_controller( WAIT_TO_GO_BACK: begin // Check for conditions that flip is_phase_two to false // We can only go back iff we are at phase two - if (is_phase_two && btnL && back_switch && !is_phase_three) begin + if (is_phase_two && (btnL || (use_mouse && debounced_middle && !mouse_middle_prev)) && back_switch && !is_phase_three) begin is_phase_two <= 0; cursor_row <= 0; current_state <= START; @@ -100,5 +174,7 @@ module phase_one_menu_controller( prev_btnU <= btnU; prev_btnC <= btnC; prev_btnD <= btnD; + mouse_left_prev <= debounced; + mouse_middle_prev <= debounced_middle; end endmodule diff --git a/FDP.srcs/sources_1/new/phase_one_menu_display.v b/FDP.srcs/sources_1/new/phase_one_menu_display.v index 84271b6..d02d759 100644 --- a/FDP.srcs/sources_1/new/phase_one_menu_display.v +++ b/FDP.srcs/sources_1/new/phase_one_menu_display.v @@ -27,14 +27,48 @@ Listens on phase_one_menu_controller for cursor_row module phase_one_menu_display( input clock, + input mouse_left, + input clk_100MHz, input [12:0] pixel_index, output reg [15:0] oled_data, input cursor_row, // Only has 2 rows - input btnC + input btnC, + input use_mouse, + input [11:0] xpos, ypos, + input middle ); wire [6:0] x = pixel_index % 96; wire [6:0] y = pixel_index / 96; + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] counter; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + initial begin + counter = 0; + debounced = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + counter <= 0; + else begin + counter <= counter + 1; + if (counter >= DEBOUNCE_DELAY) debounced <= mouse_left; + + end + end + reg mouse_left_prev; + initial begin mouse_left_prev = 1'b0; end + wire [6:0] curr_x, curr_y; + + //get current coordinates of the mouse + mouse_coordinate_extractor coord_extr( + clock, //6p25MHz clock + xpos, // 12-bit mouse x position + ypos, // 12-bit mouse y position + curr_x, curr_y); + //end of getting current coordinates of the mouse + // Drawing the menu always @ (posedge clock) begin @@ -86,12 +120,14 @@ module phase_one_menu_display( // start "button" // the dimensions for the characters are: 3 bits wide, 5 bits tall if ((y >= 34 && y <= 44) && (x >= 35 && x <= 60)) begin - if (btnC && cursor_row == 0) begin + if ((btnC || (use_mouse && debounced && !mouse_left_prev && curr_x >= 35 && curr_x <= 60 && curr_y >= 34 && curr_y <= 44)) && cursor_row == 0) begin oled_data <= 16'b00000_111111_00000; // Green when selected end else begin // Draw the borders first + //draw the horizontal borders if ((x >= 35 && x <= 60 && y == 34) || (x >= 35 && x <= 60 && y == 44)) oled_data <= 16'b11111_111111_11111; + //draw the vertical borders if ((y >= 34 && y <= 44 && x == 35) || (y >= 34 && y <= 44 && x == 60)) oled_data <= 16'b11111_111111_11111; @@ -136,7 +172,7 @@ module phase_one_menu_display( // help "button" // the dimensions for the characters are: 3 bits wide, 5 bits tall if ((y >= 46 && y <= 56) && (x >= 35 && x <= 60)) begin - if (btnC && cursor_row == 1) begin + if ((btnC || (use_mouse && debounced && !mouse_left_prev && curr_x >= 35 && curr_x <= 60 && curr_y <= 56 && curr_y >= 46))&& cursor_row == 1) begin oled_data <= 16'b00000_111111_00000; // Green when selected end else begin // Draw the borders first @@ -185,5 +221,6 @@ module phase_one_menu_display( oled_data <= 16'b11111_111111_11111; end end + mouse_left_prev <= debounced; end endmodule diff --git a/FDP.srcs/sources_1/new/phase_one_wrapper.v b/FDP.srcs/sources_1/new/phase_one_wrapper.v index e840c44..2048b97 100644 --- a/FDP.srcs/sources_1/new/phase_one_wrapper.v +++ b/FDP.srcs/sources_1/new/phase_one_wrapper.v @@ -21,6 +21,7 @@ module phase_one_wrapper( + input clk_100MHz, input clk_6p25MHz, input clk_1kHz, input [12:0] pixel_index, @@ -28,7 +29,11 @@ module phase_one_wrapper( input btnU, btnD, btnC, btnL, output is_phase_two, input is_phase_three, - input back_switch + input back_switch, + input [11:0] xpos, ypos, + input use_mouse, + input mouse_left, + input middle ); // Internal connection between controller and display @@ -37,6 +42,8 @@ module phase_one_wrapper( // Instantiate controller phase_one_menu_controller controller( .clock(clk_1kHz), + .clk_100MHz(clk_100MHz), + .clk_6p25MHz(clk_6p25MHz), .btnU(btnU), .btnD(btnD), .btnC(btnC), @@ -44,7 +51,12 @@ module phase_one_wrapper( .cursor_row(cursor_row), .is_phase_two(is_phase_two), .is_phase_three(is_phase_three), - .back_switch(back_switch) + .back_switch(back_switch), + .xpos(xpos), + .ypos(ypos), + .use_mouse(use_mouse), + .mouse_left(mouse_left), + .middle(middle) ); // Instantiate display @@ -53,7 +65,13 @@ module phase_one_wrapper( .pixel_index(pixel_index), .oled_data(oled_data), .cursor_row(cursor_row), - .btnC(btnC) + .btnC(btnC), + .xpos(xpos), + .ypos(ypos), + .clk_100MHz(clk_100MHz), + .use_mouse(use_mouse), + .mouse_left(mouse_left), + .middle(middle) ); endmodule diff --git a/FDP.srcs/sources_1/new/phase_three_controller.v b/FDP.srcs/sources_1/new/phase_three_controller.v index 0b53179..52927e1 100644 --- a/FDP.srcs/sources_1/new/phase_three_controller.v +++ b/FDP.srcs/sources_1/new/phase_three_controller.v @@ -25,6 +25,13 @@ and SELECTED_FUNCTION, accounting for backwards transitions as well. */ module phase_three_controller( input clock, + input use_mouse, + input mouse_left, + input middle, + input clk_100MHz, + input clk_6p25MHz, + input [11:0] xpos, + input [11:0] ypos, input btnU, btnD, btnC, btnL, btnR, input back_switch, input is_phase_three, @@ -43,8 +50,56 @@ module phase_three_controller( // For keypad and input building interaction input input_complete, input signed [31:0] fp_value, - output reg keypad_active = 0 + output reg keypad_active = 0, + input mouseonJB ); + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] ctr; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + initial begin + ctr = 0; + debounced = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + ctr <= 0; + else begin + ctr <= ctr + 1; + if (ctr >= DEBOUNCE_DELAY) debounced <= mouse_left; + end + end + reg mouse_left_prev; + initial begin mouse_left_prev = 1'b0; end + wire [6:0] mouse_xpos, mouse_ypos; + + //get current coordinates of the mouse + mouse_coordinate_extractor coord_extr( + clk_6p25MHz, //6p25MHz clock + xpos, // 12-bit mouse x position + ypos, // 12-bit mouse y position + mouse_xpos, mouse_ypos); + //end of getting current coordinates of the mouse + + //debouncing for middle mouse button + reg [21:0] middle_counter; // Counter for debounce delay (needs enough bits) + reg debounced_middle; // Stores the debounced state + initial begin + middle_counter = 0; + debounced_middle = 1'b0; + end + always @(posedge clk_100MHz) begin + if (middle == debounced_middle) + middle_counter <= 0; + else begin + middle_counter <= middle_counter + 1; + if (middle_counter >= DEBOUNCE_DELAY) debounced_middle <= middle; + + end + end + reg mouse_middle_prev; + initial begin mouse_middle_prev = 1'b0; end + // Previous button states for debouncing reg prev_btnC = 0; @@ -186,6 +241,12 @@ module phase_three_controller( keypad_active <= 0; // Handle cursor movement + if (mouseonJB && use_mouse && mouse_xpos >= 30 && mouse_xpos <= 66 && mouse_ypos <= 30 && mouse_ypos >= 20) begin + cursor_row <= 0; + end + else if (mouseonJB && use_mouse && mouse_xpos >= 30 && mouse_xpos <= 66 && mouse_ypos <= 45 && mouse_ypos >= 35) begin + cursor_row <= 1; + end if (btnU && !prev_btnU && debounce_U == 0) begin cursor_row <= 0; // TABLE option debounce_U <= 200; @@ -197,7 +258,9 @@ module phase_three_controller( end // Handle selection - if (btnC && !prev_btnC && debounce_C == 0) begin + if ((btnC && !prev_btnC && debounce_C == 0) || ((use_mouse && debounced && !mouse_left_prev) && + ((mouseonJB && use_mouse && mouse_xpos >= 30 && mouse_xpos <= 66 && mouse_ypos <= 45 && mouse_ypos >= 35) || + (mouseonJB && use_mouse && mouse_xpos >= 30 && mouse_xpos <= 66 && mouse_ypos <= 30 && mouse_ypos >= 20)) )) begin is_menu_selection <= 0; if (cursor_row == 0) begin @@ -213,7 +276,7 @@ module phase_three_controller( end // Back button - go back to first coefficient - if (btnL && !prev_btnL && back_switch && debounce_L == 0) begin + if (((btnL && !prev_btnL && debounce_L == 0) || (use_mouse && debounced_middle && !mouse_middle_prev)) && back_switch) begin is_menu_selection <= 0; is_getting_coefficients <= 1; keypad_active <= 1; @@ -226,7 +289,7 @@ module phase_three_controller( // In this state, specific modules take over // Back button - go back to menu - if (btnL && !prev_btnL && back_switch && debounce_L == 0) begin + if (((btnL && !prev_btnL && debounce_L == 0) || (use_mouse && debounced_middle && !mouse_middle_prev)) && back_switch ) begin is_table_selected <= 0; is_integral_selected <= 0; is_menu_selection <= 1; @@ -252,5 +315,7 @@ module phase_three_controller( prev_btnD <= btnD; prev_btnC <= btnC; prev_btnL <= btnL; + mouse_left_prev <= debounced; + mouse_middle_prev <= debounced_middle; end endmodule diff --git a/FDP.srcs/sources_1/new/phase_three_menu_display.v b/FDP.srcs/sources_1/new/phase_three_menu_display.v index 0219e35..581c029 100644 --- a/FDP.srcs/sources_1/new/phase_three_menu_display.v +++ b/FDP.srcs/sources_1/new/phase_three_menu_display.v @@ -24,7 +24,11 @@ This module is merely responsible for showing the 2 button menu for choosing between Table and Integration */ module phase_three_menu_display( - input clock, + input clock, //clk is 6p25MHz + input [11:0] xpos, ypos, + input mouse_left, + input use_mouse, //use sw[0] + input clk_100MHz, input [12:0] pixel_index, input cursor_row, // 0 = TABLE, 1 = INTG input btnC, @@ -33,7 +37,25 @@ module phase_three_menu_display( wire [6:0] x = pixel_index % 96; wire [6:0] y = pixel_index / 96; - + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] counter; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + initial begin + counter = 0; + debounced = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + counter <= 0; + else begin + counter <= counter + 1; + if (counter >= DEBOUNCE_DELAY) debounced <= mouse_left; + + end + end + reg mouse_left_prev; + initial begin mouse_left_prev = 1'b0; end // Drawing the menu always @(posedge clock) begin // Set default background @@ -127,7 +149,7 @@ module phase_three_menu_display( // TABLE button (top option) if ((y >= 20 && y <= 30) && (x >= 30 && x <= 66)) begin - if (btnC && cursor_row == 0) begin + if ((btnC || (use_mouse && debounced && !mouse_left_prev)) && cursor_row == 0) begin oled_data <= 16'b00000_111111_00000; // Green when selected end else begin @@ -174,7 +196,7 @@ module phase_three_menu_display( // INTG button (bottom option) if ((y >= 35 && y <= 45) && (x >= 30 && x <= 66)) begin - if (btnC && cursor_row == 1) begin + if ((btnC || (use_mouse && debounced && !mouse_left_prev)) && cursor_row == 1) begin oled_data <= 16'b00000_111111_00000; // Green when selected end else begin @@ -229,5 +251,6 @@ module phase_three_menu_display( oled_data <= 16'b11111_111111_11111; end end + mouse_left_prev <= debounced; end endmodule diff --git a/FDP.srcs/sources_1/new/phase_three_wrapper.v b/FDP.srcs/sources_1/new/phase_three_wrapper.v index 59df7d4..b334950 100644 --- a/FDP.srcs/sources_1/new/phase_three_wrapper.v +++ b/FDP.srcs/sources_1/new/phase_three_wrapper.v @@ -35,20 +35,26 @@ module phase_three_wrapper( input clk_100MHz, input clk_1kHz, input clk_6p25MHz, + input rst, input [12:0] one_pixel_index, input [12:0] two_pixel_index, output [15:0] one_oled_data, output [15:0] two_oled_data, input btnU, btnD, btnC, btnL, btnR, input is_phase_three, + input is_pan_mouse, input is_arithmetic_mode, output is_getting_coefficients, input back_switch, input [11:0] xpos, input [11:0] ypos, + input [3:0] zpos, input use_mouse, input mouse_left, - input mouse_middle, + input middle, + input mouse_right, + input new_event, + input mouseonJB, input pan_zoom_toggle, output overflow_flag, output integration_mode, @@ -104,6 +110,13 @@ module phase_three_wrapper( // Controllers and modules phase_three_controller controller( .clock(clk_1kHz), + .use_mouse(use_mouse), + .clk_6p25MHz(clk_6p25MHz), + .mouse_left(mouse_left), + .middle(middle), + .clk_100MHz(clk_100MHz), + .xpos(xpos), + .ypos(ypos), .btnU(btnU), .btnD(btnD), .btnC(btnC & ~pan_zoom_toggle), @@ -124,7 +137,8 @@ module phase_three_wrapper( .coeff_d(coeff_d), .input_complete(input_complete), .fp_value(fp_value), - .keypad_active(keypad_active) + .keypad_active(keypad_active), + .mouseonJB(1) ); // Unified input builder for coefficients @@ -148,6 +162,12 @@ module phase_three_wrapper( // Coefficient input cursor controller (reused from integral), interfaces with the input builder integral_cursor_controller coeff_cursor_ctrl( .clk(clk_1kHz), + .use_mouse(use_mouse), + .clk_6p25MHz(clk_6p25MHz), + .clk_100MHz(clk_100MHz), + .xpos(xpos), + .ypos(ypos), + .mouse_left(mouse_left), .reset(!is_getting_coefficients || !is_phase_three), .btnC((is_getting_coefficients && keypad_active) ? btnC : 1'b0), .btnU((is_getting_coefficients && keypad_active) ? btnU : 1'b0), @@ -190,6 +210,11 @@ module phase_three_wrapper( // Phase three menu display (choosing between TABLE AND INTG) phase_three_menu_display menu_display( .clock(clk_6p25MHz), + .clk_100MHz(clk_100MHz), + .mouse_left(mouse_left), + .use_mouse(use_mouse), + .xpos(xpos), + .ypos(ypos), .pixel_index(one_pixel_index), .cursor_row(cursor_row), .btnC(btnC), @@ -199,13 +224,14 @@ module phase_three_wrapper( // Graph display for showing function graph_display_cached graph_display( .clk(clk_6p25MHz), - .clk_100MHz(clk_100MHz), + .clk_100MHz(clk_100MHz), .btnU(btnU), .btnD(btnD), .btnL(btnL), .btnR(btnR), .btnC(btnC || back_switch), .pan_zoom_toggle(pan_zoom_toggle), + .rst(rst), .pixel_index(two_pixel_index), .coeff_a(coeff_a), .coeff_b(coeff_b), @@ -214,10 +240,13 @@ module phase_three_wrapper( .curr_x(xpos), .curr_y(ypos), .zoom_level(4'h5), // Default zoom level + .zpos(zpos), + .is_pan_mouse(is_pan_mouse), + .use_mouse(use_mouse), .mouse_left(mouse_left), .mouse_right(1'b0), - .mouse_middle(mouse_middle), - .new_event(1'b0), + .mouse_middle(middle), + .new_event(new_event), .colour(16'hF800), // Red line for graph .is_graphing_mode(is_menu_selection || is_table_selected || is_integral_selected), .is_integrate(is_integral_selected), @@ -241,7 +270,8 @@ module phase_three_wrapper( .ypos(ypos), .use_mouse(use_mouse), .mouse_left(mouse_left), - .mouse_middle(mouse_middle), + .mouse_right(mouse_right), + .mouse_middle(middle), .is_table_mode(is_table_selected), .coeff_a(coeff_a), .coeff_b(coeff_b), @@ -251,7 +281,9 @@ module phase_three_wrapper( .two_pixel_index(two_pixel_index), .one_oled_data(table_one_oled_data), .two_oled_data(table_two_oled_data), - + .new_event(new_event), + .rst(rst), + .zpos(zpos), .is_table_input_mode_outgoing(is_table_input_mode_outgoing) ); @@ -259,6 +291,11 @@ module phase_three_wrapper( integral_module integral_module( .clk_6p25MHz(clk_6p25MHz), .clk_1kHz(clk_1kHz), + .clk_100MHz(clk_100MHz), + .use_mouse(use_mouse), + .xpos(xpos), + .ypos(ypos), + .mouse_left(mouse_left), .btnC(btnC), .btnU(btnU), .btnD(btnD), @@ -283,6 +320,7 @@ module phase_three_wrapper( // Arithmetic module (the simplest module lol) arithmetic_module arithmetic_module( .clk_6p25MHz(clk_6p25MHz), + .clk_100MHz(clk_100MHz), .clk_1kHz(clk_1kHz), .btnC(btnC), .btnU(btnU), @@ -295,7 +333,7 @@ module phase_three_wrapper( .ypos(ypos), .use_mouse(use_mouse), .mouse_left(mouse_left), - .mouse_middle(mouse_middle), + .middle(middle), .one_pixel_index(one_pixel_index), .two_pixel_index(two_pixel_index), .one_oled_data(arithmetic_one_oled_data), @@ -311,7 +349,7 @@ module phase_three_wrapper( (is_table_selected) ? table_one_oled_data : (is_integral_selected) ? integral_one_oled_data : 16'h0000; - + // Output multiplexing for the second OLED assign two_oled_data = (is_phase_three && is_arithmetic_mode) ? arithmetic_two_oled_data : diff --git a/FDP.srcs/sources_1/new/phase_two_menu_controller.v b/FDP.srcs/sources_1/new/phase_two_menu_controller.v index 1b44491..abc65cb 100644 --- a/FDP.srcs/sources_1/new/phase_two_menu_controller.v +++ b/FDP.srcs/sources_1/new/phase_two_menu_controller.v @@ -30,9 +30,20 @@ module phase_two_menu_controller( output reg is_arithmetic_mode, input is_getting_coefficients, input is_phase_two, - input back_switch + input back_switch, + input [6:0] curr_x, curr_y, + input mouse_left, + input middle, + input use_mouse, + input clk_100MHz, + input clk_6p25MHz ); - + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] counter; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + + reg mouse_left_prev; // Previous button states for debouncing reg prev_btnC = 0; reg prev_btnU = 0; @@ -49,11 +60,40 @@ module phase_two_menu_controller( cursor_row <= 0; is_phase_three <= 0; is_arithmetic_mode <= 0; + mouse_left_prev = 1'b0; + counter = 0; + debounced = 1'b0; end reg current_state = 0; localparam START = 0; localparam WAIT_TO_GO_BACK = 1; + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + counter <= 0; + else begin + counter <= counter + 1; + if (counter >= DEBOUNCE_DELAY) debounced <= mouse_left; + end + end + //debouncing for middle mouse button + reg [21:0] middle_counter; // Counter for debounce delay (needs enough bits) + reg debounced_middle; // Stores the debounced state + initial begin + middle_counter = 0; + debounced_middle = 1'b0; + end + always @(posedge clk_100MHz) begin + if (middle == debounced_middle) + middle_counter <= 0; + else begin + middle_counter <= middle_counter + 1; + if (middle_counter >= DEBOUNCE_DELAY) debounced_middle <= middle; + + end + end + reg mouse_middle_prev; + initial begin mouse_middle_prev = 1'b0; end always @ (posedge clock) begin // Decrement debounce counters if active @@ -66,6 +106,37 @@ module phase_two_menu_controller( // Only listen iff phase_two START: begin if (is_phase_two && !is_phase_three) begin + if (use_mouse && curr_x >= 32 && curr_x <= 66 & curr_y >= 15 && curr_y <= 24) begin + cursor_row <= 0; + if ((use_mouse && debounced && !mouse_left_prev)) begin + if (cursor_row) begin + is_phase_three <= 1; + is_arithmetic_mode <= 1; + end + else if (!cursor_row) begin + is_phase_three <= 1; + end + // Transition to a state that allows phase_two to be false + current_state <= WAIT_TO_GO_BACK; + end + end + + else if (use_mouse && curr_x >= 30 && curr_x <= 68 && curr_y >= 26 && curr_y <= 35) begin + cursor_row <= 1; + if ((use_mouse && debounced && !mouse_left_prev)) begin + if (cursor_row) begin + is_phase_three <= 1; + is_arithmetic_mode <= 1; + end + else if (!cursor_row) begin + is_phase_three <= 1; + end + // Transition to a state that allows phase_two to be false + current_state <= WAIT_TO_GO_BACK; + end + + end + // Up Down movement if (btnU && !prev_btnU && debounce_U == 0) begin cursor_row <= ~cursor_row; @@ -96,7 +167,7 @@ module phase_two_menu_controller( WAIT_TO_GO_BACK: begin // Go back iff at phase_three, we are either in arithmetic or obtaining coefficients - if (is_phase_three && back_switch && btnL && (is_arithmetic_mode || is_getting_coefficients)) begin + if (is_phase_three && back_switch && (btnL || (use_mouse && debounced_middle && !mouse_middle_prev)) && (is_arithmetic_mode || is_getting_coefficients)) begin is_arithmetic_mode <= 0; is_phase_three <= 0; cursor_row <= 0; @@ -107,6 +178,9 @@ module phase_two_menu_controller( prev_btnU <= btnU; prev_btnC <= btnC; - prev_btnD <= btnD; + prev_btnD <= btnD; + mouse_left_prev <= debounced; + mouse_middle_prev <= debounced_middle; + end endmodule diff --git a/FDP.srcs/sources_1/new/phase_two_menu_display.v b/FDP.srcs/sources_1/new/phase_two_menu_display.v index fe7342b..f4dc8fe 100644 --- a/FDP.srcs/sources_1/new/phase_two_menu_display.v +++ b/FDP.srcs/sources_1/new/phase_two_menu_display.v @@ -30,12 +30,36 @@ module phase_two_menu_display( input [12:0] pixel_index, output reg [15:0] oled_data, input cursor_row, // Only 2 options - input btnC + input btnC, + input [6:0] curr_x, curr_y, + input mouse_left, + input middle, + input use_mouse, + input clk_100MHz ); wire [6:0] x = pixel_index % 96; wire [6:0] y = pixel_index / 96; - + //debouncing for left mouse button + parameter DEBOUNCE_DELAY = 2000000; + reg [21:0] counter; // Counter for debounce delay (needs enough bits) + reg debounced; // Stores the debounced state + initial begin + counter = 0; + debounced = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_left == debounced) + counter <= 0; + else begin + counter <= counter + 1; + if (counter >= DEBOUNCE_DELAY) debounced <= mouse_left; + + end + end + reg mouse_left_prev; + initial begin mouse_left_prev = 1'b0; end + // Drawing the menu always @ (posedge clock) begin oled_data <= 16'b0; @@ -79,7 +103,7 @@ module phase_two_menu_display( // function button if ((y >= 15 && y <= 25) && (x >= 32 && x <= 66)) begin - if (btnC && cursor_row == 0) begin + if ((btnC || (use_mouse && debounced && !mouse_left_prev && curr_x >= 32 && curr_x <= 66 & curr_y >= 15 && curr_y <= 24)) && cursor_row == 0) begin oled_data <= 16'b00000_111111_00000; // Green when selected end else begin @@ -140,7 +164,7 @@ module phase_two_menu_display( // Arithmetic button if ((y >= 26 && y <= 35) && (x >= 30 && x <= 70)) begin - if (btnC && cursor_row == 1) begin + if ((btnC || (use_mouse && debounced && !mouse_left_prev &&curr_x >= 30 && curr_x <= 68 && curr_y >= 26 && curr_y <= 35)) && cursor_row == 1) begin oled_data <= 16'b00000_111111_00000; // Green when selected end else begin @@ -230,6 +254,7 @@ module phase_two_menu_display( if (y == 31 && x == 28) oled_data <= 16'b11111_111111_11111; end - end + end + mouse_left_prev <= debounced; end endmodule diff --git a/FDP.srcs/sources_1/new/phase_two_wrapper.v b/FDP.srcs/sources_1/new/phase_two_wrapper.v index 6703074..30eb84f 100644 --- a/FDP.srcs/sources_1/new/phase_two_wrapper.v +++ b/FDP.srcs/sources_1/new/phase_two_wrapper.v @@ -23,6 +23,7 @@ module phase_two_wrapper( input clk_6p25MHz, input clk_1kHz, + input clk_100MHz, input [12:0] pixel_index, output [15:0] oled_data, input btnU, btnD, btnC, btnL, @@ -30,9 +31,23 @@ module phase_two_wrapper( output is_phase_three, output is_arithmetic_mode, input is_getting_coefficients, - input back_switch + input back_switch, + input [11:0] xpos, ypos, + input use_mouse, + input mouse_left, + input middle ); + wire [6:0] curr_x, curr_y; + mouse_coordinate_extractor mouse_coord( + clk_6p25MHz, + xpos, // 12-bit mouse x position + ypos, // 12-bit mouse y position + curr_x,// 7-bit mouse x (0-95) + curr_y // 7-bit mouse y (0-63) + ); + + // Internal connection between controller and display wire cursor_row; @@ -48,7 +63,14 @@ module phase_two_wrapper( .is_arithmetic_mode(is_arithmetic_mode), .is_getting_coefficients(is_getting_coefficients), .is_phase_two(is_phase_two), - .back_switch(back_switch) + .back_switch(back_switch), + .curr_x(curr_x), + .curr_y(curr_y), + .use_mouse(use_mouse), + .mouse_left(mouse_left), + .clk_100MHz(clk_100MHz), + .clk_6p25MHz(clk_6p25MHz), + .middle(middle) ); // Instantiate display @@ -57,7 +79,13 @@ module phase_two_wrapper( .pixel_index(pixel_index), .oled_data(oled_data), .cursor_row(cursor_row), - .btnC(btnC) + .btnC(btnC), + .curr_x(curr_x), + .curr_y(curr_y), + .use_mouse(use_mouse), + .mouse_left(mouse_left), + .clk_100MHz(clk_100MHz), + .middle(middle) ); endmodule diff --git a/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v b/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v index c02ddd0..b516a00 100644 --- a/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v +++ b/FDP.srcs/sources_1/new/polynomial_table_cursor_controller.v @@ -31,7 +31,9 @@ module polynomial_table_cursor_controller( input [6:0] mouse_ypos, input mouse_left, //used to click input mouse_middle, //used only in table mode, want to switch back to the keypad + input mouse_right, input clk, + input clk_6p25MHz, input clk_100MHz, input btnC, input btnU, @@ -50,7 +52,10 @@ module polynomial_table_cursor_controller( output reg [2:0] cursor_col = 0, output reg keypad_btn_pressed = 0, output reg [3:0] keypad_selected_value = 0, - output reg signed [31:0] starting_x = 0 + output reg signed [31:0] starting_x = 0, + input new_event, + input rst, + input zpos ); // Previous button states for debouncing @@ -75,6 +80,42 @@ module polynomial_table_cursor_controller( counter = 0; debounced = 1'b0; end + //debouncing for right mouse button + reg [21:0] right_counter; // Counter for debounce delay (needs enough bits) + reg debounced_right; // Stores the debounced state + initial begin + right_counter = 0; + debounced_right = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_right == debounced_right) + right_counter <= 0; + else begin + right_counter <= right_counter + 1; + if (right_counter >= DEBOUNCE_DELAY) debounced_right <= mouse_right; + + end + end + reg mouse_right_prev; + initial begin mouse_right_prev = 1'b0; end + //debouncing for middle mouse button + reg [21:0] middle_counter; // Counter for debounce delay (needs enough bits) + reg debounced_middle; // Stores the debounced state + initial begin + middle_counter = 0; + debounced_middle = 1'b0; + end + always @(posedge clk_100MHz) begin + if (mouse_middle == debounced_middle) + middle_counter <= 0; + else begin + middle_counter <= middle_counter + 1; + if (middle_counter >= DEBOUNCE_DELAY) debounced_middle <= mouse_middle; + + end + end + reg mouse_middle_prev; + initial begin mouse_middle_prev = 1'b0; end always @(posedge clk_100MHz) begin if (mouse_left == debounced) counter <= 0; @@ -108,7 +149,7 @@ module polynomial_table_cursor_controller( if (is_table_mode) begin // Switching between table navigation mode and input mode - if (btnC && !prev_btnC && debounce_C == 0 || mouse_middle) begin + if (btnC && !prev_btnC && debounce_C == 0) begin //it will also switch if you press the scroll wheel btn debounce_C <= 200; @@ -250,7 +291,7 @@ module polynomial_table_cursor_controller( keypad_btn_pressed <= 0; if (debounce_C > 0) debounce_C <= debounce_C - 1; - if (btnC && !prev_btnC && debounce_C == 0 || mouse_middle) begin + if (btnC && !prev_btnC && debounce_C == 0 || (debounced && !mouse_left_prev)) begin //it will also switch if you press the scroll wheel btn debounce_C <= 200; @@ -348,11 +389,19 @@ module polynomial_table_cursor_controller( end end //this end is for table input mode else begin + if ((use_mouse) && (mouse_ypos >= 0) && (mouse_ypos <= 12) && (debounced_right && !mouse_right_prev)) begin + starting_x <= starting_x + 32'h00010000; // Add 1.0 in fixed point + end + if ((use_mouse) && (mouse_ypos >= 51) && (mouse_ypos <= 63) && (debounced_right && !mouse_right_prev)) begin + starting_x <= starting_x - 32'h00010000; // Subtract 1.0 in fixed point + end //fill this up later when figured how to use the scroll wheel, navigating the polynomial table end prev_btnC <= btnC; mouse_left_prev <= debounced; + mouse_middle_prev <= debounced_middle; + mouse_right_prev <= debounced_right; end //this end is for use mouse end //this end is for the always block -endmodule +endmodule \ No newline at end of file diff --git a/FDP.srcs/sources_1/new/polynomial_table_module.v b/FDP.srcs/sources_1/new/polynomial_table_module.v index ada6aa8..7d8af64 100644 --- a/FDP.srcs/sources_1/new/polynomial_table_module.v +++ b/FDP.srcs/sources_1/new/polynomial_table_module.v @@ -32,11 +32,12 @@ module polynomial_table_module( input btnD, input btnL, input btnR, - input [6:0] xpos, - input [6:0] ypos, + input [11:0] xpos, + input [11:0] ypos, input use_mouse, input mouse_left, input mouse_middle, + input mouse_right, // Control flag input is_table_mode, @@ -54,10 +55,21 @@ module polynomial_table_module( // Two outgoing display data output [15:0] one_oled_data, output [15:0] two_oled_data, - + //for mouse stuff + input new_event, + input rst, + input zpos, output is_table_input_mode_outgoing ); - + //for mouse: to find the current coordinates of the mouse + wire [6:0] curr_x; + wire [6:0] curr_y; + mouse_coordinate_extractor unit_t (clk_6p25MHz, + xpos, // 12-bit mouse x position + ypos, // 12-bit mouse y position + curr_x, + curr_y + ); // Internal signals and states wire is_table_input_mode; assign is_table_input_mode_outgoing = is_table_input_mode; @@ -83,13 +95,15 @@ module polynomial_table_module( // Cursor controller polynomial_table_cursor_controller cursor_controller( - .mouse_xpos(xpos), - .mouse_ypos(ypos), + .mouse_xpos(curr_x), + .mouse_ypos(curr_y), .mouse_left(mouse_left), + .mouse_right(mouse_right), .mouse_middle(mouse_middle), .use_mouse(use_mouse), .clk_100MHz(clk_100MHz), .clk(clk_1kHz), + .clk_6p25MHz(clk_6p25MHz), .btnC(btnC), .btnU(btnU), .btnD(btnD), @@ -103,7 +117,10 @@ module polynomial_table_module( .cursor_col(cursor_col), .keypad_btn_pressed(keypad_btn_pressed), .keypad_selected_value(keypad_selected_value), - .starting_x(starting_x) + .starting_x(starting_x), + .new_event(new_event), + .rst(rst), + .zpos(zpos) ); // Input builder @@ -135,7 +152,7 @@ module polynomial_table_module( .input_index(input_index), .oled_data(keypad_oled_data) ); - + // Table display polynomial_table_table_display table_display( .clk(clk_6p25MHz), diff --git a/FDP.srcs/sources_1/new/scroll_led_accum.v b/FDP.srcs/sources_1/new/scroll_led_accum.v new file mode 100644 index 0000000..d76c58b --- /dev/null +++ b/FDP.srcs/sources_1/new/scroll_led_accum.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10.04.2025 17:33:32 +// Design Name: +// Module Name: scroll_led_accum +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module scroll_led_accum( + input clk, // system clock (e.g., 100 MHz) + input rst, // active-high reset + input new_event, // one-clock-cycle pulse when a scroll event occurs + input [3:0] zpos, // scroll wheel delta + // (assumed: 4'b1111 = -1, 4'b0001 = +1) + output reg [1:0] wow // 4-bit LED output (expected 0 to 15) +); + + // 4-bit counter that tracks the current value. + reg [1:0] counter; + + initial begin + counter = 2'b00; + wow = 4'b0000; + end + + // Latch new_event and zpos for one clock cycle, then update counter. + always @(posedge clk or posedge rst) begin + if (rst) begin + counter <= 2'b00; + end + else if (new_event) begin + if (zpos == 4'b0001) + counter <= 10; // scroll up ? increment + else if (zpos == 4'b1111) + counter <= 01; // scroll down ? decrement + else + counter <= 00; + end + end + + // Update LED pattern based on the counter. + always @(posedge clk) begin + wow <= counter; + end + +endmodule \ No newline at end of file diff --git a/FDP.xpr b/FDP.xpr index f25f2bb..e5f61d4 100644 --- a/FDP.xpr +++ b/FDP.xpr @@ -3,7 +3,7 @@ - +