diff --git a/README.md b/README.md
index c0ac88af0..eb41048b9 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-# NVIDIA driver 595.45.04 with P2P for 4090 and 5090
+# NVIDIA driver 595.58.03 with P2P for 4090 and 5090
 
 This allows using P2P on 4090 and 5090 GPUs with the 595.45.04 driver version.
 See https://github.com/tinygrad/open-gpu-kernel-modules (various branches) for more info.
@@ -17,7 +17,7 @@ Note that this is very dangerous if you run untrusted software or devices.
     1) Edit `/etc/default/grub`
     2) Add `amd_iommu=on iommu=pt` to `GRUB_CMDLINE_LINUX_DEFAULT`
     3) Run `sudo update-grub`
-2) Install https://www.nvidia.com/en-us/drivers/details/265309/
+2) Install https://www.nvidia.com/fr-fr/drivers/details/265902/
 3) Run `./install.sh` in this repo
 4) Reboot the server
 
diff --git a/install-cachy.sh b/install-cachy.sh
new file mode 100644
index 000000000..bd44200b7
--- /dev/null
+++ b/install-cachy.sh
@@ -0,0 +1,10 @@
+
+#!/bin/bash
+
+export  IGNORE_CC_MISMATCH=1
+sudo rmmod nvidia_drm nvidia_modeset nvidia_uvm nvidia
+set -e
+make modules -j$(nproc) CC=clang LD=ld.lld AR=llvm-ar CXX=clang++ OBJCOPY=llvm-objcopy NV_VERBOSE=1
+sudo make modules_install -j$(nproc) CC=clang LD=ld.lld AR=llvm-ar CXX=clang++ OBJCOPY=llvm-objcopy NV_VERBOSE=1
+sudo depmod
+nvidia-smi
diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild
index 855d25cc3..9ec310cc0 100644
--- a/kernel-open/Kbuild
+++ b/kernel-open/Kbuild
@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
 ccflags-y += -I$(src)
 ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
-ccflags-y += -DNV_VERSION_STRING=\"595.45.04\"
+ccflags-y += -DNV_VERSION_STRING=\"595.58.03\"
 
 # Include and link Tegra out-of-tree modules.
 ifneq ($(wildcard /usr/src/nvidia/nvidia-public),)
diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h
index d6a49ad40..efc046136 100644
--- a/kernel-open/common/inc/nv-linux.h
+++ b/kernel-open/common/inc/nv-linux.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2001-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2001-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1353,7 +1353,6 @@ typedef struct nv_linux_state_s {
     struct reset_control *nvdisplay_reset;
     struct reset_control *dsi_core_reset;
     struct reset_control *mipi_cal_reset;
-    struct reset_control *hdacodec_reset;
 
     /*
      * nv_imp_icc_path represents the interconnect path across which display
diff --git a/kernel-open/common/inc/nv-mm.h b/kernel-open/common/inc/nv-mm.h
index 919dacde8..70e284eac 100644
--- a/kernel-open/common/inc/nv-mm.h
+++ b/kernel-open/common/inc/nv-mm.h
@@ -216,6 +216,16 @@ static inline void nv_vma_flags_clear_word(struct vm_area_struct *vma, unsigned
     ACCESS_PRIVATE(vma, __vm_flags) &= ~flags;
 #endif
 }
+
+static inline int nv_is_vma_write_locked(struct vm_area_struct *vma, unsigned int *mm_lock_seq)
+{
+#if defined(NV_IS_VMA_WRITE_LOCKED_HAS_MM_LOCK_SEQ_ARG)
+    return __is_vma_write_locked(vma, mm_lock_seq);
+#else
+    *mm_lock_seq = __vma_raw_mm_seqnum(vma);
+    return __is_vma_write_locked(vma);
+#endif
+}
 #endif // !NV_CAN_CALL_VMA_START_WRITE
 
 static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
diff --git a/kernel-open/common/inc/nvkms-kapi.h b/kernel-open/common/inc/nvkms-kapi.h
index 96a10061b..34ed6c8e7 100644
--- a/kernel-open/common/inc/nvkms-kapi.h
+++ b/kernel-open/common/inc/nvkms-kapi.h
@@ -604,7 +604,17 @@ struct NvKmsKapiGpuInfo {
     MIGDeviceId   migDevice;
 };
 
+/*
+ * Linux kernel options CONFIG_RANDSTRUCT_* randomize structs that are composed
+ * entirely of function pointers, but can only control struct layout for sources
+ * built by kbuild. NvKmsKapiCallbacks is shared between kbuild-built
+ * nvidia-drm.ko, and the "OS-agnostic" portions of nvidia-modeset.ko (not built
+ * by kbuild). Add a _padding member to disable struct randomization.
+ *
+ * Refer to https://github.com/NVIDIA/open-gpu-kernel-modules/issues/1033
+ */
 struct NvKmsKapiCallbacks {
+    int  _padding;
     void (*suspendResume)(NvBool suspend);
     void (*remove)(NvU32 gpuId);
     void (*probe)(const struct NvKmsKapiGpuInfo *gpu_info);
diff --git a/kernel-open/common/inc/nvtypes.h b/kernel-open/common/inc/nvtypes.h
index c1428a1e9..739a9969c 100644
--- a/kernel-open/common/inc/nvtypes.h
+++ b/kernel-open/common/inc/nvtypes.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -514,6 +514,16 @@ typedef struct
 #define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __declspec(align(ALIGN)) TYPE_VAR
 #elif defined(__arm)
 #define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __align(ALIGN) TYPE_VAR
+#endif
+
+#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)
+#define NV_ALIGNOF(type) _Alignof(type)
+#elif defined(__cplusplus) && (__cplusplus >= 201103L)
+#define NV_ALIGNOF(type) alignof(type)
+#elif defined(__GNUC__) || defined(__clang__)
+#define NV_ALIGNOF(type) __alignof__(type)
+#elif defined(_MSC_VER)
+#define NV_ALIGNOF(type) __alignof(type)
 #endif
 
  /***************************************************************************\
diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh
index 108df4365..6df97a5be 100755
--- a/kernel-open/conftest.sh
+++ b/kernel-open/conftest.sh
@@ -5117,6 +5117,26 @@ compile_test() {
             compile_check_conftest "$CODE" "NV_DRM_CRTC_FUNCS_HAS_GET_VBLANK_TIMESTAMP" "" "types"
         ;;
 
+        is_vma_write_locked_has_mm_lock_seq_arg)
+            #
+            # Determine if __is_vma_write_locked() takes only a single
+            # 'struct vm_area_struct *' argument.
+            #
+            # Commit 22f7639f2f03 ("mm/vma: improve and document
+            # __is_vma_write_locked()") removed the 'unsigned int *mm_lock_seq'
+            # parameter in v7.0-rc1.
+            #
+            CODE="
+            #include <linux/mm.h>
+            #include <linux/mmap_lock.h>
+            int conftest_is_vma_write_locked_has_mm_lock_seq_arg(struct vm_area_struct *vma) {
+                unsigned int mm_lock_seq;
+                return __is_vma_write_locked(vma, &mm_lock_seq);
+            }"
+
+            compile_check_conftest "$CODE" "NV_IS_VMA_WRITE_LOCKED_HAS_MM_LOCK_SEQ_ARG" "" "types"
+        ;;
+
         # When adding a new conftest entry, please use the correct format for
         # specifying the relevant upstream Linux kernel commit.  Please
         # avoid specifying -rc kernels, and only use SHAs that actually exist
diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
index 5de9809fe..8268ee088 100644
--- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
@@ -585,6 +585,14 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev,
     allocParams.compressible = &p->compressible;
 
     pMemory = nvKms->allocateMemory(nv_dev->pDevice, &allocParams);
+    if (pMemory == NULL && (p->flags & NV_GEM_ALLOC_NO_SCANOUT)) {
+        NV_DRM_DEV_LOG_INFO(
+                nv_dev,
+                "Failed to allocate NVKMS video memory for GEM object, trying to fall back to sysmem");
+        allocParams.useVideoMemory = false;
+        pMemory = nvKms->allocateMemory(nv_dev->pDevice, &allocParams);
+    }
+
     if (pMemory == NULL) {
         ret = -EINVAL;
         NV_DRM_DEV_LOG_ERR(nv_dev,
diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c
index 85ac47b38..4dedd4e3b 100644
--- a/kernel-open/nvidia-uvm/uvm_gpu.c
+++ b/kernel-open/nvidia-uvm/uvm_gpu.c
@@ -2921,7 +2921,7 @@ static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid,
 #if UVM_IS_CONFIG_HMM()
     // HMM was disabled when first initialising the parent so we can't support
     // it now. Tell the caller to retry with it disabled.
-    else if (!parent_gpu->devmem && enable_hmm) {
+    else if (!parent_gpu->devmem && enable_hmm && uvm_hmm_is_enabled_system_wide()) {
         status = NV_ERR_BUSY_RETRY;
         goto error;
     }
@@ -3222,10 +3222,25 @@ uvm_gpu_phys_address_t uvm_gpu_peer_phys_address(uvm_gpu_t *owning_gpu, NvU64 ad
 uvm_gpu_address_t uvm_gpu_peer_copy_address(uvm_gpu_t *owning_gpu, NvU64 address, uvm_gpu_t *accessing_gpu)
 {
     uvm_gpu_identity_mapping_t *gpu_peer_mapping;
+    const bool mig_peers_use_phys = uvm_gpus_are_smc_peers(owning_gpu, accessing_gpu) &&
+        accessing_gpu->parent->ce_phys_vidmem_write_supported;
 
-    if (accessing_gpu->parent->peer_copy_mode == UVM_GPU_PEER_COPY_MODE_PHYSICAL)
+    // MIG peers do not create peer vidmem mappings like other peers. They do
+    // create their vidmem identity mappings to cover all possible physical
+    // addresses, even those of other MIG peers.
+    // Use vidmem this identity mapping if CEs need to use virtual addresses.
+    if (uvm_gpus_are_smc_peers(owning_gpu, accessing_gpu) && !mig_peers_use_phys) {
+        uvm_gpu_phys_address_t phys_address = uvm_gpu_peer_phys_address(owning_gpu, address, accessing_gpu);
+        return uvm_gpu_address_virtual_from_vidmem_phys(accessing_gpu, phys_address.address);
+    }
+
+    // Use physical addresses for MIGs peers if CE allows it. Irespective of
+    // the peer copy mode.
+    if (accessing_gpu->parent->peer_copy_mode == UVM_GPU_PEER_COPY_MODE_PHYSICAL || mig_peers_use_phys)
         return uvm_gpu_address_from_phys(uvm_gpu_peer_phys_address(owning_gpu, address, accessing_gpu));
 
+    // MIG peers do not create peer GPU mappings so it should never reach here.
+    UVM_ASSERT(!uvm_gpus_are_smc_peers(owning_gpu, accessing_gpu));
     UVM_ASSERT(accessing_gpu->parent->peer_copy_mode == UVM_GPU_PEER_COPY_MODE_VIRTUAL);
     gpu_peer_mapping = uvm_gpu_get_peer_mapping(accessing_gpu, owning_gpu->id);
 
diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c
index 5ba0024cd..35cd8fb97 100644
--- a/kernel-open/nvidia-uvm/uvm_hmm.c
+++ b/kernel-open/nvidia-uvm/uvm_hmm.c
@@ -2152,7 +2152,10 @@ static void fill_dst_pfn(uvm_va_block_t *va_block,
 
         UVM_ASSERT(!page_count(dpage));
         UVM_ASSERT(!dpage->zone_device_data);
-        nv_zone_device_page_init(dpage);
+
+
+          zone_device_page_init(dpage, 0, 0);
+
         dpage->zone_device_data = gpu_chunk;
         atomic64_inc(&va_block->hmm.va_space->hmm.allocated_page_count);
     }
diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c
index 373eca943..d575ce7d5 100644
--- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c
+++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c
@@ -177,6 +177,8 @@
 #include "uvm_test.h"
 #include "uvm_linux.h"
 
+#include <linux/version.h>
+
 #if defined(CONFIG_PCI_P2PDMA) && defined(NV_STRUCT_PAGE_HAS_ZONE_DEVICE_DATA)
 #include <linux/pci-p2pdma.h>
 #endif
@@ -3019,6 +3021,7 @@ static bool uvm_pmm_gpu_check_orphan_pages(uvm_pmm_gpu_t *pmm)
     return ret;
 }
 
+
 static void devmem_page_free(struct page *page)
 {
     uvm_gpu_chunk_t *chunk = uvm_pmm_devmem_page_to_chunk(page);
@@ -3271,6 +3274,7 @@ static void device_p2p_page_free_wake(struct nv_kref *ref)
     wake_up(&p2p_mem->waitq);
 }
 
+
 static void device_p2p_page_free(struct page *page)
 {
     uvm_device_p2p_mem_t *p2p_mem = page->zone_device_data;
@@ -3286,6 +3290,7 @@ static void device_p2p_folio_free(struct folio *folio)
 #endif
 
 #if UVM_CDMM_PAGES_SUPPORTED()
+
 static void device_coherent_page_free(struct page *page)
 {
     device_p2p_page_free(page);
diff --git a/kernel-open/nvidia/nv-mmap.c b/kernel-open/nvidia/nv-mmap.c
index c518847c0..8a90f56e9 100644
--- a/kernel-open/nvidia/nv-mmap.c
+++ b/kernel-open/nvidia/nv-mmap.c
@@ -957,15 +957,22 @@ void NV_API_CALL nv_set_safe_to_mmap_locked(
 }
 
 #if !NV_CAN_CALL_VMA_START_WRITE
+
+#if defined(VM_REFCNT_EXCLUDE_READERS_FLAG)
+#define NV_VMA_LOCK_OFFSET VM_REFCNT_EXCLUDE_READERS_FLAG
+#else
+#define NV_VMA_LOCK_OFFSET VMA_LOCK_OFFSET
+#endif
+
 static NvBool nv_vma_enter_locked(struct vm_area_struct *vma, NvBool detaching)
 {
-    NvU32 tgt_refcnt = VMA_LOCK_OFFSET;
+    NvU32 tgt_refcnt = NV_VMA_LOCK_OFFSET;
     NvBool interrupted = NV_FALSE;
     if (!detaching)
     {
         tgt_refcnt++;
     }
-    if (!refcount_add_not_zero(VMA_LOCK_OFFSET, &vma->vm_refcnt))
+    if (!refcount_add_not_zero(NV_VMA_LOCK_OFFSET, &vma->vm_refcnt))
     {
         return NV_FALSE;
     }
@@ -995,7 +1002,7 @@ static NvBool nv_vma_enter_locked(struct vm_area_struct *vma, NvBool detaching)
     if (interrupted)
     {
         // Clean up on error: release refcount and dep_map
-        refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
+        refcount_sub_and_test(NV_VMA_LOCK_OFFSET, &vma->vm_refcnt);
         rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
         return NV_FALSE;
     }
@@ -1011,7 +1018,7 @@ void nv_vma_start_write(struct vm_area_struct *vma)
 {
     NvU32 mm_lock_seq;
     NvBool locked;
-    if (__is_vma_write_locked(vma, &mm_lock_seq))
+    if (nv_is_vma_write_locked(vma, &mm_lock_seq))
         return;
 
     locked = nv_vma_enter_locked(vma, NV_FALSE);
@@ -1020,7 +1027,7 @@ void nv_vma_start_write(struct vm_area_struct *vma)
     if (locked)
     {
         NvBool detached;
-        detached = refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
+        detached = refcount_sub_and_test(NV_VMA_LOCK_OFFSET, &vma->vm_refcnt);
         rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
         WARN_ON_ONCE(detached);
     }
diff --git a/kernel-open/nvidia/nv-platform.c b/kernel-open/nvidia/nv-platform.c
index 6a456755e..f251265d3 100644
--- a/kernel-open/nvidia/nv-platform.c
+++ b/kernel-open/nvidia/nv-platform.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -497,26 +497,6 @@ NV_STATUS NV_API_CALL nv_soc_device_reset(nv_state_t *nv)
                 goto out;
             }
         }
-
-        if (nvl->hdacodec_reset != NULL)
-        {
-            /*
-             * HDACODEC reset control is shared between display driver and audio driver.
-             * Since reset_control_reset toggles the reset signal, we prefer to use
-             * reset_control_deassert. Additionally, since Audio driver uses
-             * reset_control_bulk_deassert() which internally calls reset_control_deassert,
-             * we must use reset_control_deassert, because consumers must not use
-             * reset_control_reset on shared reset lines when reset_control_deassert has
-             * been used.
-             */
-            rc = reset_control_deassert(nvl->hdacodec_reset);
-            if (rc != 0)
-            {
-                status = NV_ERR_GENERIC;
-                nv_printf(NV_DBG_ERRORS, "NVRM: hdacodec reset_control_deassert failed, rc: %d\n", rc);
-                goto out;
-            }
-        }
     }
 out:
     return status;
@@ -1078,26 +1058,6 @@ static int nv_platform_device_display_probe(struct platform_device *plat_dev)
             nv_printf(NV_DBG_ERRORS, "NVRM: mipi_cal devm_reset_control_get failed, err: %ld\n",  PTR_ERR(nvl->mipi_cal_reset));
             nvl->mipi_cal_reset = NULL;
         }
-
-        /*
-         * In T23x, HDACODEC is part of the same power domain as NVDisplay, so
-         * unpowergating the DISP domain also results in the HDACODEC reset
-         * being de-asserted. However, in T26x, HDACODEC is being moved
-         * out to a separate always-on domain, so we need to explicitly de-assert
-         * the HDACODEC reset in RM. We don't have good way to differentiate
-         * between T23x vs T264x at this place. So if there is failure to read
-         * "hdacodec_reset" from DT silently ignore it for now. In long term we
-         * should really look into using the devm_reset_control_bulk* APIs and
-         * see if this is feasible if we're ultimately just getting and
-         * asserting/deasserting all of the resets specified in DT together all of
-         * the time, and if there's no scenarios in which we need to only use a 
-         * specific set of reset(s) at a given point.
-         */
-        nvl->hdacodec_reset = devm_reset_control_get(nvl->dev, "hdacodec_reset");
-        if (IS_ERR(nvl->hdacodec_reset))
-        {
-            nvl->hdacodec_reset = NULL;
-        }
     }
 
     status = nv_imp_icc_get(nv);
diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild
index c065f6b16..6996bad11 100644
--- a/kernel-open/nvidia/nvidia.Kbuild
+++ b/kernel-open/nvidia/nvidia.Kbuild
@@ -226,6 +226,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += has_enum_pidtype_tgid
 NV_CONFTEST_TYPE_COMPILE_TESTS += bpmp_mrq_has_strap_set
 NV_CONFTEST_TYPE_COMPILE_TESTS += register_shrinker_has_format_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += pci_resize_resource_has_exclude_bars_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += is_vma_write_locked_has_mm_lock_seq_arg
 
 NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present
 NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build
diff --git a/src/common/displayport/inc/dp_connectorimpl2x.h b/src/common/displayport/inc/dp_connectorimpl2x.h
index 7ce63e56b..b2f9af95c 100644
--- a/src/common/displayport/inc/dp_connectorimpl2x.h
+++ b/src/common/displayport/inc/dp_connectorimpl2x.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -110,6 +110,7 @@ namespace DisplayPort
         bool    bStuffDummySymbolsFor128b132b;
         bool    bStuffDummySymbolsFor8b10b;
         bool    bDisableWatermarkCaching;
+        bool    bEnableClearMSAWhenNotUsed;
 
         // Do not enable downspread while link training.
         bool    bDisableDownspread;
diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h
index 94bac99e9..145745ff1 100644
--- a/src/common/displayport/inc/dp_regkeydatabase.h
+++ b/src/common/displayport/inc/dp_regkeydatabase.h
@@ -118,6 +118,9 @@
 
 #define NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT    "DISABLE_NATIVE_DISPLAYID2X_SUPPORT"
 #define NV_DP_REGKEY_FORCE_NLPIGNORE_DDS                   "DP_FORCE_NLPIGNORE_DDS"
+
+#define NV_DP_REGKEY_ENABLE_CLEAR_MSA_WHEN_NOT_USED          "DP_ENABLE_CLEAR_MSA_WHEN_NOT_USED"
+
 //
 // Data Base used to store all the regkey values.
 // The actual data base is declared statically in dp_evoadapter.cpp.
@@ -169,6 +172,7 @@ struct DP_REGKEY_DATABASE
     bool  bDisableNativeDisplayId2xSupport;
     bool  bUseMaxDSCCompressionMST;
     bool  bIgnoreUnplugUnlessRequested;
+    bool  bEnableClearMSAWhenNotUsed;
 };
 
 extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;
diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp
index 28236440d..87cde5be4 100644
--- a/src/common/displayport/src/dp_connectorimpl.cpp
+++ b/src/common/displayport/src/dp_connectorimpl.cpp
@@ -1551,6 +1551,8 @@ bool ConnectorImpl::compoundQueryAttachMSTIsDscPossible
                 ((dev->devDoingDscDecompression == dev) &&
                 (dev->isLogical() && dev->parent)))
             {
+                DP_ASSERT((dev->devDoingDscDecompression != NULL) &&
+                          (dev->parent != NULL));
                 //
                 // If DSC decoding is going to happen at sink's parent or
                 // decoding will be done by sink but sink is a logical port,
@@ -7340,7 +7342,7 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
             return;
         }
 
-        if (existingDev && (existingDev->isPreviouslyFakedMuxDevice() || bIgnoreUnplugUnlessRequested) && !existingDev->isMarkedForDeletion())
+        if (existingDev && existingDev->isPreviouslyFakedMuxDevice() && !existingDev->isMarkedForDeletion())
         {
             DP_PRINTF(DP_NOTICE, "NotifyLongPulse ignored as there is a previously faked device but it is not marked for deletion");
             if (!statusConnected)
@@ -7350,6 +7352,12 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
             }
             return;
         }
+
+		if (existingDev && bIgnoreUnplugUnlessRequested && !statusConnected && !existingDev->isMarkedForDeletion())
+		{
+			sink->notifyDetectComplete();
+			return;
+		}
     }
 
     if (previousPlugged && statusConnected)
diff --git a/src/common/displayport/src/dp_connectorimpl2x.cpp b/src/common/displayport/src/dp_connectorimpl2x.cpp
index a69c10ff8..d4236a65c 100644
--- a/src/common/displayport/src/dp_connectorimpl2x.cpp
+++ b/src/common/displayport/src/dp_connectorimpl2x.cpp
@@ -114,6 +114,7 @@ void ConnectorImpl2x::applyDP2xRegkeyOverrides()
     this->maxLinkRateFromRegkey = dpRegkeyDatabase.applyMaxLinkRateOverrides;
     bSupportInternalUhbrOnFpga  = dpRegkeyDatabase.supportInternalUhbrOnFpga;
     this->bDisableWatermarkCaching = dpRegkeyDatabase.bDisableWatermarkCaching;
+    this->bEnableClearMSAWhenNotUsed = dpRegkeyDatabase.bEnableClearMSAWhenNotUsed;
     if (dpRegkeyDatabase.bIgnoreCableIdCaps)
     {
         hal->setIgnoreCableIdCaps(true);
@@ -935,6 +936,18 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
         main->setDpStereoMSAParameters(!enableInbandStereoSignaling, modesetParams.msaparams);
         main->setDpMSAParameters(!enableInbandStereoSignaling, modesetParams.msaparams);
     }
+    else
+    {
+        // Clear MSA parameters for MST topology
+        if (this->bEnableClearMSAWhenNotUsed)
+        {
+            NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS msaParams = modesetParams.msaparams;
+            msaParams.bEnableMSA        = false;
+
+            main->setDpStereoMSAParameters(false, msaParams);
+            main->setDpMSAParameters(false, msaParams);
+        }
+    }
 
     NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN_STATUS, bLinkTrainingStatus);
 
diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp
index 9df9b1b4f..9d1313e5c 100644
--- a/src/common/displayport/src/dp_deviceimpl.cpp
+++ b/src/common/displayport/src/dp_deviceimpl.cpp
@@ -65,8 +65,10 @@ DeviceImpl::~DeviceImpl()
 
     // Unlink this node from its children
     for (unsigned int i = 0; i < sizeof(children)/sizeof(*children); i++)
-        if (children[i])
-            children[i]->parent = 0;
+        if (children[i]) {
+            children[i]->parent = NULL;
+            children[i]->setDscDecompressionDevice(false /* bDscCapBasedOnParent */);
+        }
 
     // Unlink this node from its parent when it's there
     if (parent && (parent->children[this->address.tail()] == this))
diff --git a/src/common/displayport/src/dp_discovery.cpp b/src/common/displayport/src/dp_discovery.cpp
index c5456d280..e1d732de6 100644
--- a/src/common/displayport/src/dp_discovery.cpp
+++ b/src/common/displayport/src/dp_discovery.cpp
@@ -462,7 +462,7 @@ void DiscoveryManager::BranchDetection::messageFailed(MessageManager::Message *
     if (from == &linkAddressMessage)
     {
         if (retriesLinkAddressMessage < DPCD_LINK_ADDRESS_MESSAGE_RETRIES &&
-            (nakData->reason == NakDefer || nakData->reason == NakTimeout))
+            (nakData->reason == NakDefer || nakData->reason == NakTimeout || nakData->reason == NakLinkFailure))
         {
             retriesLinkAddressMessage++;
             retryLinkAddressMessage = true;
diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp
index 01051f4a7..bad7cee77 100644
--- a/src/common/displayport/src/dp_evoadapter.cpp
+++ b/src/common/displayport/src/dp_evoadapter.cpp
@@ -116,7 +116,8 @@ const struct
     {NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION,  &dpRegkeyDatabase.bEnable128b132bDSCLnkCfgReduction,  DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT,     &dpRegkeyDatabase.bDisableNativeDisplayId2xSupport,   DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST,            &dpRegkeyDatabase.bUseMaxDSCCompressionMST,           DP_REG_VAL_BOOL},
-    {NV_DP_REGKEY_FORCE_NLPIGNORE_DDS,                    &dpRegkeyDatabase.bIgnoreUnplugUnlessRequested,       DP_REG_VAL_BOOL}
+    {NV_DP_REGKEY_FORCE_NLPIGNORE_DDS,                    &dpRegkeyDatabase.bIgnoreUnplugUnlessRequested,       DP_REG_VAL_BOOL},
+    {NV_DP_REGKEY_ENABLE_CLEAR_MSA_WHEN_NOT_USED,         &dpRegkeyDatabase.bEnableClearMSAWhenNotUsed,         DP_REG_VAL_BOOL}
 };
 
 EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h
index 3cac6a582..40045e190 100644
--- a/src/common/inc/nvBldVer.h
+++ b/src/common/inc/nvBldVer.h
@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r595_59
+    #define NV_BUILD_BRANCH             r595_88
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r595_59
+    #define NV_PUBLIC_BRANCH             r595_88
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r595/r595_59-167"
-#define NV_BUILD_CHANGELIST_NUM         (37420354)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r595/r595_88-200"
+#define NV_BUILD_CHANGELIST_NUM         (37651405)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r595/r595_59-167"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37420354)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r595/r595_88-200"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37651405)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r595_59-5"
-#define NV_BUILD_CHANGELIST_NUM         (37420354)
+#define NV_BUILD_BRANCH_VERSION         "r595_88-3"
+#define NV_BUILD_CHANGELIST_NUM         (37651405)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "595.71"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37420354)
+#define NV_BUILD_NAME                   "595.97"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37651405)
 #define NV_BUILD_BRANCH_BASE_VERSION    R595
 #endif
 // End buildmeister python edited section
diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h
index c3a784c10..c1f773943 100644
--- a/src/common/inc/nvUnixVersion.h
+++ b/src/common/inc/nvUnixVersion.h
@@ -5,7 +5,7 @@
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
     defined(NV_DCECORE)
 
-#define NV_VERSION_STRING               "595.45.04"
+#define NV_VERSION_STRING               "595.58.03"
 
 #else
 
diff --git a/src/common/sdk/nvidia/inc/nvtypes.h b/src/common/sdk/nvidia/inc/nvtypes.h
index 25e1ee279..6250de6e8 100644
--- a/src/common/sdk/nvidia/inc/nvtypes.h
+++ b/src/common/sdk/nvidia/inc/nvtypes.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -508,6 +508,14 @@ typedef struct
 #define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) TYPE_VAR __attribute__ ((aligned (ALIGN)))
 #elif defined(__arm)
 #define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __align(ALIGN) TYPE_VAR
+#endif
+
+#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)
+#define NV_ALIGNOF(type) _Alignof(type)
+#elif defined(__cplusplus) && (__cplusplus >= 201103L)
+#define NV_ALIGNOF(type) alignof(type)
+#elif defined(__GNUC__) || defined(__clang__)
+#define NV_ALIGNOF(type) __alignof__(type)
 #endif
 
  /***************************************************************************\
diff --git a/src/common/shared/inc/g_vgpu_chip_flags.h b/src/common/shared/inc/g_vgpu_chip_flags.h
index 870b21d26..c04328dcf 100644
--- a/src/common/shared/inc/g_vgpu_chip_flags.h
+++ b/src/common/shared/inc/g_vgpu_chip_flags.h
@@ -1063,6 +1063,52 @@ ENTRY(0x2BB9, 0x226E, 0x10de, "NVIDIA RTX 6000D-84C"),
 ENTRY(0x2BB9, 0x226F, 0x10de, "NVIDIA RTX 6000D-84"),
 ENTRY(0x2BB9, 0x22EE, 0x10de, "NVIDIA GeForce RTX 3050"),
 ENTRY(0x2BB9, 0x22EF, 0x10de, "NVIDIA GeForce RTX 3060"),
+ENTRY(0x2C3A, 0x2295, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2Q"),
+ENTRY(0x2C3A, 0x2296, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2A"),
+ENTRY(0x2C3A, 0x2297, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2B"),
+ENTRY(0x2C3A, 0x2298, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2"),
+ENTRY(0x2C3A, 0x2299, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-3B"),
+ENTRY(0x2C3A, 0x229A, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4Q"),
+ENTRY(0x2C3A, 0x229B, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4A"),
+ENTRY(0x2C3A, 0x229C, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4"),
+ENTRY(0x2C3A, 0x229D, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8Q"),
+ENTRY(0x2C3A, 0x229E, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8A"),
+ENTRY(0x2C3A, 0x229F, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8C"),
+ENTRY(0x2C3A, 0x22A0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8"),
+ENTRY(0x2C3A, 0x22A1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16Q"),
+ENTRY(0x2C3A, 0x22A2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16A"),
+ENTRY(0x2C3A, 0x22A3, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16C"),
+ENTRY(0x2C3A, 0x22A4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16"),
+ENTRY(0x2C3A, 0x22A5, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8Q"),
+ENTRY(0x2C3A, 0x22A6, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8A"),
+ENTRY(0x2C3A, 0x22A7, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8C"),
+ENTRY(0x2C3A, 0x22A8, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8"),
+ENTRY(0x2C3A, 0x22A9, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16Q"),
+ENTRY(0x2C3A, 0x22AA, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16A"),
+ENTRY(0x2C3A, 0x22AB, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16C"),
+ENTRY(0x2C3A, 0x22AC, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16"),
+ENTRY(0x2C3A, 0x22AD, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32Q"),
+ENTRY(0x2C3A, 0x22AE, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32A"),
+ENTRY(0x2C3A, 0x22AF, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32C"),
+ENTRY(0x2C3A, 0x22B0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32"),
+ENTRY(0x2C3A, 0x22B1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2B"),
+ENTRY(0x2C3A, 0x22B2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2"),
+ENTRY(0x2C3A, 0x22B3, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-3B"),
+ENTRY(0x2C3A, 0x22B4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4Q"),
+ENTRY(0x2C3A, 0x22B5, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4A"),
+ENTRY(0x2C3A, 0x22B6, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4"),
+ENTRY(0x2C3A, 0x22B7, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8Q"),
+ENTRY(0x2C3A, 0x22B8, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8A"),
+ENTRY(0x2C3A, 0x22B9, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8C"),
+ENTRY(0x2C3A, 0x22BA, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8"),
+ENTRY(0x2C3A, 0x22BB, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16Q"),
+ENTRY(0x2C3A, 0x22BC, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16A"),
+ENTRY(0x2C3A, 0x22BD, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16C"),
+ENTRY(0x2C3A, 0x22BE, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16"),
+ENTRY(0x2C3A, 0x22BF, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32Q"),
+ENTRY(0x2C3A, 0x22C0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32A"),
+ENTRY(0x2C3A, 0x22C1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32C"),
+ENTRY(0x2C3A, 0x22C2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32"),
 ENTRY(0x3182, 0x22CB, 0x10de, "NVIDIA B300X-1-34CME"),
 ENTRY(0x3182, 0x22CC, 0x10de, "NVIDIA B300X-1-34C"),
 ENTRY(0x3182, 0x22CD, 0x10de, "NVIDIA B300X-1-67C"),
diff --git a/src/common/shared/inc/g_vgpu_resman_specific.h b/src/common/shared/inc/g_vgpu_resman_specific.h
index 6c0a66f75..3f979b4ea 100644
--- a/src/common/shared/inc/g_vgpu_resman_specific.h
+++ b/src/common/shared/inc/g_vgpu_resman_specific.h
@@ -312,6 +312,34 @@ static const struct {
     {0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2206}, // NVIDIA RTX 6000D-2-84
     {0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF)   , 2266}, // NVIDIA GeForce RTX 3050
     {0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF)   , 2267}, // NVIDIA GeForce RTX 3060
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2229}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2230}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2231}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2B
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2232}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2233}, // NVIDIA RTX PRO 4500 Blackwell DC-1-3B
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2234}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2235}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2236}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2237}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2238}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2239}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2240}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2241}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2242}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2243}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2244}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2245}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2246}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2247}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2248}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2249}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2250}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2251}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2252}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2253}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2254}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2255}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2256}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32
     {0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 2259}, // NVIDIA B300X-1-34CME
     {0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU                                                                     , 2258}, // NVIDIA B300X-1-34C
     {0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU                                                                 , 2260}, // NVIDIA B300X-1-67C
diff --git a/src/nvidia-modeset/Makefile b/src/nvidia-modeset/Makefile
index b54138cc4..2c6ca74c3 100644
--- a/src/nvidia-modeset/Makefile
+++ b/src/nvidia-modeset/Makefile
@@ -112,7 +112,6 @@ endif
 
 CFLAGS += -fno-pic
 CFLAGS += -fno-common
-CFLAGS += -fomit-frame-pointer
 CFLAGS += -fno-strict-aliasing
 CFLAGS += -ffunction-sections
 CFLAGS += -fdata-sections
@@ -130,7 +129,7 @@ ifeq ($(TARGET_ARCH),x86_64)
 
   #
   # GCC flags -fcf-protection=branch and -mindirect-branch=extern-thunk can
-  # be used together after GCC version 9.4.0. See 
+  # be used together after GCC version 9.4.0. See
   # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654 for details.
   # Check if GCC version is appropriate.
   #
@@ -153,8 +152,11 @@ ifeq ($(TARGET_ARCH),x86_64)
     CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fcf-protection=branch)
   endif
   CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fno-jump-tables)
-  CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch=thunk-extern)
+	CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fno-asynchronous-unwind-tables)
   CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch-register)
+  CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch=thunk-extern)
+  CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mharden-sls=all)
+  CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mfunction-return=thunk-extern)
 endif
 
 CFLAGS += $(CONDITIONAL_CFLAGS)
diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h
index c4e8f8f72..fc076226a 100644
--- a/src/nvidia-modeset/include/nvkms-evo.h
+++ b/src/nvidia-modeset/include/nvkms-evo.h
@@ -89,7 +89,8 @@ NvBool nvValidateHwModeTimingsViewPort(const NVDevEvoRec *pDevEvo,
                                        NVHwModeTimingsEvoPtr pTimings,
                                        NVEvoInfoStringPtr pInfoString);
 void nvAssignDefaultUsageBounds(const NVDispEvoRec *pDispEvo,
-                                NVHwModeViewPortEvo *pViewPort);
+                                NVHwModeViewPortEvo *pViewPort,
+                                const struct NvKmsModeValidationParams *pModeValidationParams);
 void nvUnionUsageBounds(const struct NvKmsUsageBounds *a,
                         const struct NvKmsUsageBounds *b,
                         struct NvKmsUsageBounds *ret);
diff --git a/src/nvidia-modeset/interface/nvkms-api.h b/src/nvidia-modeset/interface/nvkms-api.h
index f0f5b9e94..b06086a70 100644
--- a/src/nvidia-modeset/interface/nvkms-api.h
+++ b/src/nvidia-modeset/interface/nvkms-api.h
@@ -472,6 +472,19 @@ struct NvKmsModeValidationParams {
      * When dscOverrideBitsPerPixelX16 is 0, NVKMS compute the rate itself.
      */
     NvU32 dscOverrideBitsPerPixelX16;
+
+    /*!
+     * Maximum pixel depth (in bits) for each layer's usage bounds.
+     * When non-zero, NVKMS filters out surface memory formats with
+     * bpp > this value before performing the gpu extended capability check.
+     *
+     * This allows clients to constrain usage bounds based on the maximum
+     * pixel depth they will actually use, preventing bandwidth allocation
+     * for deeper formats that will never be validated or displayed.
+     *
+     * Value 0 means no constraint (backward compatible).
+     */
+    NvU8 maxUsageBoundPixelDepth[NVKMS_MAX_LAYERS_PER_HEAD];
 };
 
 /*!
diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h
index 96a10061b..34ed6c8e7 100644
--- a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h
+++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h
@@ -604,7 +604,17 @@ struct NvKmsKapiGpuInfo {
     MIGDeviceId   migDevice;
 };
 
+/*
+ * Linux kernel options CONFIG_RANDSTRUCT_* randomize structs that are composed
+ * entirely of function pointers, but can only control struct layout for sources
+ * built by kbuild. NvKmsKapiCallbacks is shared between kbuild-built
+ * nvidia-drm.ko, and the "OS-agnostic" portions of nvidia-modeset.ko (not built
+ * by kbuild). Add a _padding member to disable struct randomization.
+ *
+ * Refer to https://github.com/NVIDIA/open-gpu-kernel-modules/issues/1033
+ */
 struct NvKmsKapiCallbacks {
+    int  _padding;
     void (*suspendResume)(NvBool suspend);
     void (*remove)(NvU32 gpuId);
     void (*probe)(const struct NvKmsKapiGpuInfo *gpu_info);
diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c
index 3ff110bd7..9c14aadab 100644
--- a/src/nvidia-modeset/src/nvkms-evo.c
+++ b/src/nvidia-modeset/src/nvkms-evo.c
@@ -6541,11 +6541,45 @@ static void AssignGuaranteedSOCBounds(const NVDevEvoRec *pDevEvo,
 }
 
 /*
- * Initialize the given NvKmsUsageBounds. Ask for everything supported by the HW
- * by default.  Later, based on what IMP says, we will scale back as needed.
+ * Filter surface memory formats based on maximum pixel depth.
+ * Returns a new bitmask with only formats that have bpp <= maxPixelDepth.
+ * If maxPixelDepth is 0, returns the original mask (no filtering).
+ */
+static NvU64 FilterFormatsByPixelDepth(NvU64 formats, NvU8 maxPixelDepth)
+{
+    NvU64 filtered = 0;
+    enum NvKmsSurfaceMemoryFormat format;
+
+    if (maxPixelDepth == 0) {
+        return formats;
+    }
+
+    for (format = NvKmsSurfaceMemoryFormatMin;
+         format <= NvKmsSurfaceMemoryFormatMax;
+         format++) {
+        const NvKmsSurfaceMemoryFormatInfo *pFormatInfo;
+
+        if (!(formats & NVBIT64(format))) {
+            continue;
+        }
+
+        pFormatInfo = nvKmsGetSurfaceMemoryFormatInfo(format);
+        if (pFormatInfo->depth <= maxPixelDepth) {
+            filtered |= NVBIT64(format);
+        }
+    }
+
+    return filtered;
+}
+
+/*
+ * Initialize the given NvKmsUsageBounds. Ask for everything supported by the HW,
+ * filtered against any client-specified constraints.  Later, based on what IMP says,
+ * we will scale back as needed.
  */
 void nvAssignDefaultUsageBounds(const NVDispEvoRec *pDispEvo,
-                                NVHwModeViewPortEvo *pViewPort)
+                                NVHwModeViewPortEvo *pViewPort,
+                                const struct NvKmsModeValidationParams *pModeValidationParams)
 {
     const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo;
     struct NvKmsUsageBounds *pPossible = &pViewPort->possibleUsage;
@@ -6555,7 +6589,10 @@ void nvAssignDefaultUsageBounds(const NVDispEvoRec *pDispEvo,
         struct NvKmsScalingUsageBounds *pScaling = &pPossible->layer[i].scaling;
 
         pPossible->layer[i].supportedSurfaceMemoryFormats =
-            pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats;
+            FilterFormatsByPixelDepth(
+                pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats,
+                pModeValidationParams->maxUsageBoundPixelDepth[i]);
+
         pPossible->layer[i].usable =
             (pPossible->layer[i].supportedSurfaceMemoryFormats != 0);
         if (!pPossible->layer[i].usable) {
@@ -6609,7 +6646,8 @@ ConstructHwModeTimingsViewPort(const NVDispEvoRec *pDispEvo,
                                NVHwModeTimingsEvoPtr pTimings,
                                NVEvoInfoStringPtr pInfoString,
                                const struct NvKmsSize *pViewPortSizeIn,
-                               const struct NvKmsRect *pViewPortOut)
+                               const struct NvKmsRect *pViewPortOut,
+                               const struct NvKmsModeValidationParams *pParams)
 {
     NVHwModeViewPortEvoPtr pViewPort = &pTimings->viewPort;
     NvU32 outWidth, outHeight;
@@ -6700,7 +6738,7 @@ ConstructHwModeTimingsViewPort(const NVDispEvoRec *pDispEvo,
         }
     }
 
-    nvAssignDefaultUsageBounds(pDispEvo, &pTimings->viewPort);
+    nvAssignDefaultUsageBounds(pDispEvo, &pTimings->viewPort, pParams);
 
     return TRUE;
 }
@@ -6958,7 +6996,7 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo,
 
     ret = ConstructHwModeTimingsViewPort(pDpyEvo->pDispEvo, pTimings,
                                          pInfoString, pViewPortSizeIn,
-                                         pViewPortOut);
+                                         pViewPortOut, pParams);
 
     if (!ret) {
         return ret;
diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c
index 455836e80..13c5b1f07 100644
--- a/src/nvidia-modeset/src/nvkms-evo3.c
+++ b/src/nvidia-modeset/src/nvkms-evo3.c
@@ -3043,7 +3043,8 @@ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead,
                                      const NvBool enableDsc,
                                      const NvBool b2Heads1Or,
                                      const int head,
-                                     const NVEvoScalerCaps *pScalerCaps)
+                                     const NVEvoScalerCaps *pScalerCaps,
+                                     const NvU32 possibleDscSliceCountMask)
 {
     const NVHwModeViewPortEvo *pViewPort = &pTimings->viewPort;
     struct NvKmsScalingUsageBounds scalingUsageBounds = { };
@@ -3094,6 +3095,7 @@ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead,
     pImpHead->cursorSize32p = 256 / 32;
 
     pImpHead->bEnableDsc = enableDsc;
+    pImpHead->possibleDscSliceCountMask = possibleDscSliceCountMask;
 
     pImpHead->bIs2Head1Or = b2Heads1Or;
 
@@ -3228,7 +3230,8 @@ nvEvoSetCtrlIsModePossibleParams3(NVDispEvoPtr pDispEvo,
                                     enableDsc,
                                     b2Heads1Or,
                                     head,
-                                    &pEvoCaps->head[head].scalerCaps)) {
+                                    &pEvoCaps->head[head].scalerCaps,
+                                    pInput->head[head].possibleDscSliceCountMask)) {
             return FALSE;
         }
 
diff --git a/src/nvidia/Makefile b/src/nvidia/Makefile
index bba499c2a..d747ab5dc 100644
--- a/src/nvidia/Makefile
+++ b/src/nvidia/Makefile
@@ -73,6 +73,7 @@ CFLAGS += -Werror-implicit-function-declaration
 CFLAGS += -Wwrite-strings
 CFLAGS += -Wundef
 CFLAGS += -fno-common
+CFLAGS += -fno-strict-aliasing
 CFLAGS += -ffreestanding
 CFLAGS += -fno-stack-protector
 
@@ -159,7 +160,7 @@ ifeq ($(TARGET_ARCH),x86_64)
 
   #
   # GCC flags -fcf-protection=branch and -mindirect-branch=extern-thunk can
-  # be used together after GCC version 9.4.0. See 
+  # be used together after GCC version 9.4.0. See
   # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654 for details.
   # Check if GCC version is appropriate.
   #
@@ -183,7 +184,9 @@ ifeq ($(TARGET_ARCH),x86_64)
   endif
   CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fno-jump-tables)
   CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch-register)
-    CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch=thunk-extern)
+  CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch=thunk-extern)
+  CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mharden-sls=all)
+  CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mfunction-return=thunk-extern)
 endif
 
 CFLAGS += $(CONDITIONAL_CFLAGS)
diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c
index 766f3ba1a..bc784af82 100644
--- a/src/nvidia/arch/nvalloc/unix/src/os.c
+++ b/src/nvidia/arch/nvalloc/unix/src/os.c
@@ -839,6 +839,44 @@ NV_STATUS osQueueSystemWorkItem(
     return status;
 }
 
+NV_STATUS osQueueSystemWorkItemWithFlags(
+    OSSystemWorkItemFunction pFunction,
+    void *pParams,
+    OsQueueWorkItemFlags flags
+)
+{
+    nv_work_item_t *pWi;
+    NV_STATUS status;
+
+    pWi = portMemAllocNonPaged(sizeof(nv_work_item_t));
+
+    if (NULL == pWi)
+    {
+        return NV_ERR_NO_MEMORY;
+    }
+
+    pWi->flags = (OsQueueWorkItemFlags){0};
+    pWi->flags.bDontFreeParams         = flags.bDontFreeParams;
+    pWi->flags.bLockSema               = flags.bLockSema;
+    pWi->flags.apiLock                 = flags.apiLock;
+    pWi->flags.bLockGpus               = flags.bLockGpus;
+    pWi->flags.bLockGpuGroupDevice     = flags.bLockGpuGroupDevice;
+    pWi->flags.bLockGpuGroupSubdevice  = flags.bLockGpuGroupSubdevice;
+    pWi->flags.bFullGpuSanity          = flags.bFullGpuSanity;
+    pWi->flags.bDropOnUnloadQueueFlush = flags.bDropOnUnloadQueueFlush;
+    pWi->func.pSystemFunction = pFunction;
+    pWi->pData = pParams;
+
+    status = os_queue_work_item(NULL, pWi);
+
+    if (NV_OK != status)
+    {
+        portMemFree((void *)pWi);
+    }
+
+    return status;
+}
+
 void osQueueMMUFaultHandler(OBJGPU *pGpu)
 {
     nv_state_t *nv = NV_GET_NV_STATE(pGpu);
@@ -1050,16 +1088,19 @@ NV_STATUS osAllocPagesInternal(
         goto done;
     }
 
+    // Associate pMemData with pMemDesc immediately to ensure cleanup on error
+    memdescSetMemData(pMemDesc, pMemData, NULL);
+
     // Guest allocated memory is already initialized
     if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))
     {
         if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc))
         {
-            NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, osPageCount * os_page_size, os_page_size));
+            NV_ASSERT_OK_OR_GOTO(status, memdescSetAllocSizeFields(pMemDesc, osPageCount * os_page_size, os_page_size), done);
         }
         else
         {
-            NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, rmPageCount * RM_PAGE_SIZE, RM_PAGE_SIZE));
+            NV_ASSERT_OK_OR_GOTO(status, memdescSetAllocSizeFields(pMemDesc, rmPageCount * RM_PAGE_SIZE, RM_PAGE_SIZE), done);
         }
     }
 
@@ -1069,7 +1110,7 @@ NV_STATUS osAllocPagesInternal(
     //
     if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc))
     {
-        NV_ASSERT_OR_RETURN(pMemDesc->pageArrayGranularity == os_page_size, NV_ERR_INVALID_ARGUMENT);
+        NV_ASSERT_TRUE_OR_GOTO(status, pMemDesc->pageArrayGranularity == os_page_size, NV_ERR_INVALID_ARGUMENT, done);
     }
     else if (NV_RM_PAGE_SIZE < os_page_size &&
             !memdescGetContiguity(pMemDesc, AT_CPU))
@@ -1078,10 +1119,8 @@ NV_STATUS osAllocPagesInternal(
                                 pMemDesc->PageCount);
     }
 
-    memdescSetMemData(pMemDesc, pMemData, NULL);
-
     if ((pGpu != NULL) && IS_VIRTUAL(pGpu))
-        NV_ASSERT_OK_OR_RETURN(vgpuUpdateGuestSysmemPfnBitMap(pGpu, pMemDesc, NV_TRUE));
+        NV_ASSERT_OK_OR_GOTO(status, vgpuUpdateGuestSysmemPfnBitMap(pGpu, pMemDesc, NV_TRUE), done);
 done:
     return status;
 }
diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c
index 7a81680c6..4b61bd5d4 100644
--- a/src/nvidia/arch/nvalloc/unix/src/osapi.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1376,7 +1376,11 @@ RmDmabufVerifyMemHandle(
 
     pMemDesc = pSrcMemory->pMemDesc;
 
-    if (pGpuInstanceInfo != NULL)
+    //
+    // We skip the partitionable heap check when the source memory is in
+    // sysmem as there is no valid heap (pHeap will be NULL).
+    //
+    if (pGpuInstanceInfo != NULL && memdescGetAddressSpace(pMemDesc) != ADDR_SYSMEM)
     {
         KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance;
         pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo;
diff --git a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
index 89ee179c4..699345071 100644
--- a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
@@ -758,11 +758,11 @@ osCreateOsDescriptorFromPhysAddr
 
     if (IS_DISCONTIG_AND_DYNGRAN_ENABLED(pMemDesc))
     {
-        NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, size, os_page_size));
+        NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, os_page_size), cleanup_pages);
     }
     else
     {
-        NV_ASSERT_OK_OR_RETURN(memdescSetAllocSizeFields(pMemDesc, size, NV_RM_PAGE_SIZE));
+        NV_ASSERT_OK_OR_GOTO(rmStatus, memdescSetAllocSizeFields(pMemDesc, size, NV_RM_PAGE_SIZE), cleanup_pages);
     }
 
     // If IOMMU skip flag wasn't set earlier, create IOVA mapping.
diff --git a/src/nvidia/arch/nvalloc/unix/src/subdevice_ctrl_os_unix.c b/src/nvidia/arch/nvalloc/unix/src/subdevice_ctrl_os_unix.c
index fdbdb6bfa..899ae610f 100644
--- a/src/nvidia/arch/nvalloc/unix/src/subdevice_ctrl_os_unix.c
+++ b/src/nvidia/arch/nvalloc/unix/src/subdevice_ctrl_os_unix.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,7 +68,8 @@ subdeviceCtrlCmdOsUnixVidmemPersistenceStatus_IMPL
     nv_state_t *nv   = NV_GET_NV_STATE(pGpu);
     nv_priv_t  *nvp  = NV_GET_NV_PRIV(nv);
 
-    pParams->bVidmemPersistent = (nv->preserve_vidmem_allocations || nvp->s0ix_pm_enabled);
+    pParams->bVidmemPersistent = (nv->preserve_vidmem_allocations || nvp->s0ix_pm_enabled ||
+                                  nv->supports_tegra_igpu_rg);
 
     return NV_OK;
 }
diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h
index 7985fde09..eae516840 100644
--- a/src/nvidia/generated/g_kern_bus_nvoc.h
+++ b/src/nvidia/generated/g_kern_bus_nvoc.h
@@ -191,7 +191,8 @@ typedef enum
 #define COHERENT_CPU_MAPPING_REGION_0       0x0
 #define COHERENT_CPU_MAPPING_REGION_1       0x1
 #define COHERENT_CPU_MAPPING_REGION_2       0x2
-#define COHERENT_CPU_MAPPING_TOTAL_REGIONS  0x3   // Should change it when num of regions changed
+#define COHERENT_CPU_MAPPING_REGION_3       0x3
+#define COHERENT_CPU_MAPPING_TOTAL_REGIONS  0x4   // Should change it when num of regions changed
 
 #define ALIGN_64K(addr)                   (NV_ALIGN_DOWN64(addr, 0x10000))
 #define ALIGN_64K_OFFSET(addr)            (addr & 0xFFFF)
@@ -371,10 +372,10 @@ struct __nvoc_inner_struc_KernelBus_3__ {
 struct __nvoc_inner_struc_KernelBus_4__ {
     NvBool bCoherentCpuMapping;
     NvU32 nrMapping;
-    NvP64 pCpuMapping[3];
-    NvU64 size[3];
-    NvU64 refcnt[3];
-    RmPhysAddr physAddr[3];
+    NvP64 pCpuMapping[4];
+    NvU64 size[4];
+    NvU64 refcnt[4];
+    RmPhysAddr physAddr[4];
 };
 
 struct __nvoc_inner_struc_KernelBus_5__ {
diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h
index d3f974b17..06eeaa793 100644
--- a/src/nvidia/generated/g_nv_name_released.h
+++ b/src/nvidia/generated/g_nv_name_released.h
@@ -782,6 +782,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2901, 0x1999, 0x10de, "NVIDIA B200" },
     { 0x2901, 0x199b, 0x10de, "NVIDIA B200" },
     { 0x2901, 0x20da, 0x10de, "NVIDIA B200" },
+    { 0x2909, 0x22eb, 0x10de, "NVIDIA B200" },
     { 0x2941, 0x2046, 0x10de, "NVIDIA GB200" },
     { 0x2941, 0x20ca, 0x10de, "NVIDIA GB200" },
     { 0x2941, 0x20d5, 0x10de, "NVIDIA GB200" },
@@ -810,6 +811,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2BB5, 0x204e, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Server Edition" },
     { 0x2BB5, 0x220b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Server Edition" },
     { 0x2BB9, 0x2091, 0x10de, "NVIDIA RTX 6000D" },
+    { 0x2BB9, 0x2092, 0x10de, "NVIDIA RTX 6000D" },
+    { 0x2BB9, 0x2279, 0x10de, "NVIDIA RTX 6000D" },
     { 0x2C02, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080" },
     { 0x2C05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti" },
     { 0x2C18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
@@ -828,6 +831,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2C34, 0x2052, 0x17aa, "NVIDIA RTX PRO 4000 Blackwell" },
     { 0x2C38, 0x0000, 0x0000, "NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU" },
     { 0x2C39, 0x0000, 0x0000, "NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU" },
+    { 0x2C3A, 0x21f4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell Server Edition" },
     { 0x2C58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
     { 0x2C59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
     { 0x2C77, 0x0000, 0x0000, "NVIDIA RTX PRO 5000 Blackwell Embedded GPU" },
@@ -857,6 +861,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2F58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
     { 0x3182, 0x20e6, 0x10de, "NVIDIA B300 SXM6 AC" },
     { 0x31C2, 0x21f1, 0x10de, "NVIDIA GB300" },
+    { 0x31C3, 0x22f8, 0x10de, "NVIDIA GB300" },
     { 0x1E37, 0x1347, 0x10DE, "GeForce RTX T10x-8" },
     { 0x1E37, 0x1348, 0x10DE, "GeForce RTX T10x-4" },
     { 0x1E37, 0x1349, 0x10DE, "GeForce RTX T10x-2" },
@@ -1899,6 +1904,52 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2BB9, 0x226f, 0x10DE, "NVIDIA RTX 6000D-84" },
     { 0x2BB9, 0x22ee, 0x10DE, "NVIDIA GeForce RTX 3050" },
     { 0x2BB9, 0x22ef, 0x10DE, "NVIDIA GeForce RTX 3060" },
+    { 0x2C3A, 0x2295, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2Q" },
+    { 0x2C3A, 0x2296, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2A" },
+    { 0x2C3A, 0x2297, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2B" },
+    { 0x2C3A, 0x2298, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2" },
+    { 0x2C3A, 0x2299, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-3B" },
+    { 0x2C3A, 0x229a, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-4Q" },
+    { 0x2C3A, 0x229b, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-4A" },
+    { 0x2C3A, 0x229c, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-4" },
+    { 0x2C3A, 0x229d, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8Q" },
+    { 0x2C3A, 0x229e, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8A" },
+    { 0x2C3A, 0x229f, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8C" },
+    { 0x2C3A, 0x22a0, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8" },
+    { 0x2C3A, 0x22a1, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16Q" },
+    { 0x2C3A, 0x22a2, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16A" },
+    { 0x2C3A, 0x22a3, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16C" },
+    { 0x2C3A, 0x22a4, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16" },
+    { 0x2C3A, 0x22a5, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8Q" },
+    { 0x2C3A, 0x22a6, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8A" },
+    { 0x2C3A, 0x22a7, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8C" },
+    { 0x2C3A, 0x22a8, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8" },
+    { 0x2C3A, 0x22a9, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16Q" },
+    { 0x2C3A, 0x22aa, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16A" },
+    { 0x2C3A, 0x22ab, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16C" },
+    { 0x2C3A, 0x22ac, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16" },
+    { 0x2C3A, 0x22ad, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32Q" },
+    { 0x2C3A, 0x22ae, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32A" },
+    { 0x2C3A, 0x22af, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32C" },
+    { 0x2C3A, 0x22b0, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32" },
+    { 0x2C3A, 0x22b1, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2B" },
+    { 0x2C3A, 0x22b2, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2" },
+    { 0x2C3A, 0x22b3, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-3B" },
+    { 0x2C3A, 0x22b4, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-4Q" },
+    { 0x2C3A, 0x22b5, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-4A" },
+    { 0x2C3A, 0x22b6, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-4" },
+    { 0x2C3A, 0x22b7, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8Q" },
+    { 0x2C3A, 0x22b8, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8A" },
+    { 0x2C3A, 0x22b9, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8C" },
+    { 0x2C3A, 0x22ba, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8" },
+    { 0x2C3A, 0x22bb, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16Q" },
+    { 0x2C3A, 0x22bc, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16A" },
+    { 0x2C3A, 0x22bd, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16C" },
+    { 0x2C3A, 0x22be, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16" },
+    { 0x2C3A, 0x22bf, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32Q" },
+    { 0x2C3A, 0x22c0, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32A" },
+    { 0x2C3A, 0x22c1, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32C" },
+    { 0x2C3A, 0x22c2, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32" },
     { 0x3182, 0x22cb, 0x10DE, "NVIDIA B300X-1-34CME" },
     { 0x3182, 0x22cc, 0x10DE, "NVIDIA B300X-1-34C" },
     { 0x3182, 0x22cd, 0x10DE, "NVIDIA B300X-1-67C" },
diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c
index aebf28ccf..37dd7efe1 100644
--- a/src/nvidia/generated/g_subdevice_nvoc.c
+++ b/src/nvidia/generated/g_subdevice_nvoc.c
@@ -5092,12 +5092,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
 #endif
     },
     {               /*  [330] */
-#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40040u)
         /*pFunc=*/      (void (*)(void)) NULL,
 #else
-        /*pFunc=*/      (void (*)(void)) &subdeviceCtrlCmdFifoDisableUsermodeChannels_IMPL,
-#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
-        /*flags=*/      0x40u,
+        /*pFunc=*/      (void (*)(void)) &subdeviceCtrlCmdFifoDisableUsermodeChannels_DISPATCH,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40040u)
+        /*flags=*/      0x40040u,
         /*accessRight=*/0x0u,
         /*methodId=*/   0x20801117u,
         /*paramSize=*/  sizeof(NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS),
@@ -10185,6 +10185,16 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
         pThis->__subdeviceCtrlCmdFifoRotateKeys__ = &subdeviceCtrlCmdFifoRotateKeys_IMPL;
     }
 
+    // subdeviceCtrlCmdFifoDisableUsermodeChannels -- halified (2 hals) exported (id=0x20801117) body
+    if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ 
+    {
+        pThis->__subdeviceCtrlCmdFifoDisableUsermodeChannels__ = &subdeviceCtrlCmdFifoDisableUsermodeChannels_ac1694;
+    }
+    else
+    {
+        pThis->__subdeviceCtrlCmdFifoDisableUsermodeChannels__ = &subdeviceCtrlCmdFifoDisableUsermodeChannels_5baef9;
+    }
+
     // subdeviceCtrlCmdFifoGetUserdLocation -- halified (2 hals) exported (id=0x2080110d) body
     if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 
     {
@@ -10415,13 +10425,13 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
     {
         pThis->__subdeviceCtrlCmdCcuGetSampleInfo__ = &subdeviceCtrlCmdCcuGetSampleInfo_5baef9;
     }
-} // End __nvoc_init_funcTable_Subdevice_1 with approximately 108 basic block(s).
+} // End __nvoc_init_funcTable_Subdevice_1 with approximately 110 basic block(s).
 
 
-// Initialize vtable(s) for 84 virtual method(s).
+// Initialize vtable(s) for 85 virtual method(s).
 void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner, GpuHalspecOwner *pGpuhalspecowner) {
 
-    // Initialize vtable(s) with 54 per-object function pointer(s).
+    // Initialize vtable(s) with 55 per-object function pointer(s).
     __nvoc_init_funcTable_Subdevice_1(pThis, pRmhalspecowner, pGpuhalspecowner);
 }
 
diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h
index 29149d27e..ed704de8a 100644
--- a/src/nvidia/generated/g_subdevice_nvoc.h
+++ b/src/nvidia/generated/g_subdevice_nvoc.h
@@ -135,7 +135,7 @@ struct Subdevice {
     struct Notifier *__nvoc_pbase_Notifier;    // notify super
     struct Subdevice *__nvoc_pbase_Subdevice;    // subdevice
 
-    // Vtable with 54 per-object function pointers
+    // Vtable with 55 per-object function pointers
     NV_STATUS (*__subdeviceCtrlCmdBiosGetInfoV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *);  // halified (2 hals) exported (id=0x20800810) body
     NV_STATUS (*__subdeviceCtrlCmdBiosGetSKUInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *);  // halified (2 hals) exported (id=0x20800808)
     NV_STATUS (*__subdeviceCtrlCmdBiosGetPostTime__)(struct Subdevice * /*this*/, NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS *);  // halified (2 hals) exported (id=0x20800809) body
@@ -167,6 +167,7 @@ struct Subdevice {
     NV_STATUS (*__subdeviceCtrlCmdFifoDisableChannelsForKeyRotation__)(struct Subdevice * /*this*/, NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS *);  // halified (2 hals) exported (id=0x2080111a) body
     NV_STATUS (*__subdeviceCtrlCmdFifoDisableChannelsForKeyRotationV2__)(struct Subdevice * /*this*/, NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS *);  // halified (2 hals) exported (id=0x2080111b) body
     NV_STATUS (*__subdeviceCtrlCmdFifoRotateKeys__)(struct Subdevice * /*this*/, NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS *);  // halified (2 hals) exported (id=0x2080111c) body
+    NV_STATUS (*__subdeviceCtrlCmdFifoDisableUsermodeChannels__)(struct Subdevice * /*this*/, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *);  // halified (2 hals) exported (id=0x20801117) body
     NV_STATUS (*__subdeviceCtrlCmdFifoGetUserdLocation__)(struct Subdevice * /*this*/, NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS *);  // halified (2 hals) exported (id=0x2080110d) body
     NV_STATUS (*__subdeviceCtrlCmdFifoObjschedGetCaps__)(struct Subdevice * /*this*/, NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS *);  // halified (2 hals) exported (id=0x20801122) body
     NV_STATUS (*__subdeviceCtrlCmdFifoConfigCtxswTimeout__)(struct Subdevice * /*this*/, NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS *);  // halified (2 hals) exported (id=0x20801110) body
@@ -1775,16 +1776,6 @@ static inline NV_STATUS subdeviceCtrlCmdFifoDisableChannels(struct Subdevice *pS
 #define subdeviceCtrlCmdFifoDisableChannels(pSubdevice, pDisableChannelParams) subdeviceCtrlCmdFifoDisableChannels_IMPL(pSubdevice, pDisableChannelParams)
 #endif // __nvoc_subdevice_h_disabled
 
-NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams);
-#ifdef __nvoc_subdevice_h_disabled
-static inline NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams) {
-    NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!");
-    return NV_ERR_NOT_SUPPORTED;
-}
-#else // __nvoc_subdevice_h_disabled
-#define subdeviceCtrlCmdFifoDisableUsermodeChannels(pSubdevice, pParams) subdeviceCtrlCmdFifoDisableUsermodeChannels_IMPL(pSubdevice, pParams)
-#endif // __nvoc_subdevice_h_disabled
-
 NV_STATUS subdeviceCtrlCmdFifoGetChannelMemInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS *pChannelMemParams);
 #ifdef __nvoc_subdevice_h_disabled
 static inline NV_STATUS subdeviceCtrlCmdFifoGetChannelMemInfo(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS *pChannelMemParams) {
@@ -6135,6 +6126,9 @@ static inline NV_STATUS subdeviceCtrlCmdBifGetData(struct Subdevice *pSubdevice,
 #define subdeviceCtrlCmdFifoRotateKeys_FNPTR(pSubdevice) pSubdevice->__subdeviceCtrlCmdFifoRotateKeys__
 #define subdeviceCtrlCmdFifoRotateKeys(pSubdevice, pRotateKeyParams) subdeviceCtrlCmdFifoRotateKeys_DISPATCH(pSubdevice, pRotateKeyParams)
 #define subdeviceCtrlCmdFifoRotateKeys_HAL(pSubdevice, pRotateKeyParams) subdeviceCtrlCmdFifoRotateKeys_DISPATCH(pSubdevice, pRotateKeyParams)
+#define subdeviceCtrlCmdFifoDisableUsermodeChannels_FNPTR(pSubdevice) pSubdevice->__subdeviceCtrlCmdFifoDisableUsermodeChannels__
+#define subdeviceCtrlCmdFifoDisableUsermodeChannels(pSubdevice, pParams) subdeviceCtrlCmdFifoDisableUsermodeChannels_DISPATCH(pSubdevice, pParams)
+#define subdeviceCtrlCmdFifoDisableUsermodeChannels_HAL(pSubdevice, pParams) subdeviceCtrlCmdFifoDisableUsermodeChannels_DISPATCH(pSubdevice, pParams)
 #define subdeviceCtrlCmdFifoGetUserdLocation_FNPTR(pSubdevice) pSubdevice->__subdeviceCtrlCmdFifoGetUserdLocation__
 #define subdeviceCtrlCmdFifoGetUserdLocation(pSubdevice, pUserdLocationParams) subdeviceCtrlCmdFifoGetUserdLocation_DISPATCH(pSubdevice, pUserdLocationParams)
 #define subdeviceCtrlCmdFifoGetUserdLocation_HAL(pSubdevice, pUserdLocationParams) subdeviceCtrlCmdFifoGetUserdLocation_DISPATCH(pSubdevice, pUserdLocationParams)
@@ -6396,6 +6390,10 @@ static inline NV_STATUS subdeviceCtrlCmdFifoRotateKeys_DISPATCH(struct Subdevice
     return pSubdevice->__subdeviceCtrlCmdFifoRotateKeys__(pSubdevice, pRotateKeyParams);
 }
 
+static inline NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams) {
+    return pSubdevice->__subdeviceCtrlCmdFifoDisableUsermodeChannels__(pSubdevice, pParams);
+}
+
 static inline NV_STATUS subdeviceCtrlCmdFifoGetUserdLocation_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS *pUserdLocationParams) {
     return pSubdevice->__subdeviceCtrlCmdFifoGetUserdLocation__(pSubdevice, pUserdLocationParams);
 }
@@ -6888,8 +6886,6 @@ NV_STATUS subdeviceCtrlCmdFifoGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_
 
 NV_STATUS subdeviceCtrlCmdFifoDisableChannels_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *pDisableChannelParams);
 
-NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams);
-
 NV_STATUS subdeviceCtrlCmdFifoGetChannelMemInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS *pChannelMemParams);
 
 NV_STATUS subdeviceCtrlCmdFifoObjschedSwGetLog_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS *pParams);
@@ -7998,6 +7994,14 @@ static inline NV_STATUS subdeviceCtrlCmdFifoRotateKeys_395e98(struct Subdevice *
     return NV_ERR_NOT_SUPPORTED;
 }
 
+static inline NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels_ac1694(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams){
+    return NV_OK;
+}
+
+static inline NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels_5baef9(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams){
+    NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED);
+}
+
 static inline NV_STATUS subdeviceCtrlCmdFifoGetUserdLocation_395e98(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS *pUserdLocationParams){
     return NV_ERR_NOT_SUPPORTED;
 }
diff --git a/src/nvidia/inc/kernel/os/workitem.h b/src/nvidia/inc/kernel/os/workitem.h
index 9d53faf7f..ea838675a 100644
--- a/src/nvidia/inc/kernel/os/workitem.h
+++ b/src/nvidia/inc/kernel/os/workitem.h
@@ -79,6 +79,7 @@ typedef void OSSystemWorkItemFunction(void *);
 NV_STATUS  osQueueWorkItem(struct OBJGPU *pGpu, OSWorkItemFunction pFunction, void *pParams, OsQueueWorkItemFlags flags);
 
 NV_STATUS  osQueueSystemWorkItem(OSSystemWorkItemFunction, void *);
+NV_STATUS  osQueueSystemWorkItemWithFlags(OSSystemWorkItemFunction, void *pParams, OsQueueWorkItemFlags flags);
 WorkItemItem * osGetDeferredWorkItems(NvU64 *workitemBegin, NvU64 *workitemEnd);
 NvS32 osExecuteOneDeferredWorkItem(struct OBJGPU *pGpu);
 NvU64 osGetLastDeferredExecutionTime(void);
diff --git a/src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h b/src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
index 631c95e1f..00717cfa6 100644
--- a/src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
+++ b/src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
@@ -3408,7 +3408,7 @@ return_t deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_B
     {
         dest->connectionType    = src->connectionType;
         dest->peerId            = src->peerId;
-        dest->bSpaAccessOnly    = src->bSpaAccessOnly;
+        dest->bSpaAccessOnly    = (NvBool)src->bSpaAccessOnly;
         dest->bUseUuid          = src->bUseUuid;
 
         portMemCopy(dest->remoteGpuUuid,
@@ -3436,7 +3436,7 @@ return_t deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08(NV2080_CTRL_B
         dest->connectionType    = src->connectionType;
         dest->peerId            = src->peerId;
         dest->bEgmPeer          = src->bEgmPeer;
-        dest->bSpaAccessOnly    = src->bSpaAccessOnly;
+        dest->bSpaAccessOnly    = (NvBool)src->bSpaAccessOnly;
         dest->bUseUuid          = src->bUseUuid;
         dest->remoteGpuId       = src->remoteGpuId;
 
diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c
index 6aea7135a..01f08ca71 100644
--- a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c
+++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c
@@ -1072,6 +1072,7 @@ kbusCreateCoherentCpuMapping_GH100
                 reservedRegions, COHERENT_CPU_MAPPING_TOTAL_REGIONS - 1,
                 &numReservedRegions, wprRegions, 2);
         
+            NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_GENERIC);
             NV_ASSERT(numReservedRegions <= COHERENT_CPU_MAPPING_TOTAL_REGIONS - 1);
         }
     
diff --git a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c
index e46007111..be109a9a6 100644
--- a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c
+++ b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -833,10 +833,11 @@ kceMapPceLceForNvlinkPeers_GA100
         portMemSet(pParams, 0, sizeof(*pParams));
         pParams->linkMask = peerLinkMask;
 
-        status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink,
-                                     NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS,
-                                     pParams, sizeof(*pParams));
-        NV_ASSERT_OK_OR_RETURN(status);
+        NV_ASSERT_OK_OR_GOTO(status,
+            knvlinkExecGspRmRpc(pGpu, pKernelNvlink,
+                                NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS,
+                                pParams, sizeof(*pParams)),
+            done);
 
         FOR_EACH_INDEX_IN_MASK(32, linkId, peerLinkMask)
         {
@@ -893,6 +894,7 @@ kceMapPceLceForNvlinkPeers_GA100
         status = NV_WARN_NOTHING_TO_DO;
     }
 
+done:
     portMemFree(pParams);
     return status;
 }
diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c
index 415b1bdad..c82f0a47f 100644
--- a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c
+++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1166,6 +1166,7 @@ NV_STATUS kceGetP2PCes_GH100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32
         FOR_EACH_INDEX_IN_MASK(32, phyLinkId, peerLinkMask)
         {
             NvU32 hshubId = params.hshubIds[phyLinkId];
+            NV_ASSERT_OR_RETURN(hshubId < NV_CE_MAX_HSHUBS, NV_ERR_INVALID_STATE);
             linksPerHshub[hshubId]++;
 
             if (linksPerHshub[hshubId] > maxLinksConnectedHshub)
@@ -1176,6 +1177,12 @@ NV_STATUS kceGetP2PCes_GH100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32
         }
         FOR_EACH_INDEX_IN_MASK_END;
 
+        // If no peer links were found, maxConnectedHshubId is still the sentinel value
+        if (maxConnectedHshubId >= NV_CE_MAX_HSHUBS)
+        {
+            return NV_OK;
+        }
+
         //
         // Iterate through all Async LCEs to track which HSHUB should
         // be using which LCE. This is decided based on the majority. If
diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c
index f0ae0aca7..d2022bc67 100644
--- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c
+++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c
@@ -779,7 +779,10 @@ kfifoChidMgrAllocChid_IMPL
         /* Channel USERD manipuliation only supported without GFID */
         if (bForceUserdPage)
         {
-            NV_ASSERT_OR_RETURN(!bForceInternalIdx, NV_ERR_INVALID_STATE);
+            NV_ASSERT_TRUE_OR_GOTO(status,
+                !bForceInternalIdx,
+                NV_ERR_INVALID_STATE,
+                fail);
             ChID64 = ((NvU64)userdPageIdx) *
                          pChidMgr->pGlobalChIDHeap->ownerGranularity +
                      internalIdx;
@@ -809,8 +812,9 @@ kfifoChidMgrAllocChid_IMPL
             }
         }
 
-        NV_ASSERT_OK_OR_RETURN(
-            pChidMgr->pGlobalChIDHeap->eheapSetAllocRange(pChidMgr->pGlobalChIDHeap, rangeLo, rangeHi));
+        NV_ASSERT_OK_OR_GOTO(status,
+            pChidMgr->pGlobalChIDHeap->eheapSetAllocRange(pChidMgr->pGlobalChIDHeap, rangeLo, rangeHi),
+            fail);
 
         status = pChidMgr->pGlobalChIDHeap->eheapAlloc(
             pChidMgr->pGlobalChIDHeap, // This Heap
@@ -890,7 +894,6 @@ kfifoChidMgrAllocChid_IMPL
     return NV_OK;
 
 fail:
-    // We already know that pIsolationID is non-NULL here.
     portMemFree(pIsolationID);
     return status;
 }
diff --git a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c
index d611f4817..d8ac9c59d 100644
--- a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c
+++ b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2022-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -164,7 +164,7 @@ _gpushareddataUpdateSeqOpen
     NvU64 seqVal;
 
     ct_assert(sizeof(PORT_ATOMIC NvU64) == sizeof(NvU64));
-    ct_assert(_Alignof(PORT_ATOMIC NvU64) == _Alignof(NvU64));
+    ct_assert(NV_ALIGNOF(PORT_ATOMIC NvU64) == NV_ALIGNOF(NvU64));
 
     // Initialize seq to RUSD_SEQ_START at first write. If never written before, seq is treated as an invalid timestamp
     if (MEM_RD64(pSeq) == 0LLU)
diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c
index c14abd38e..a5541cde8 100644
--- a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c
+++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1187,7 +1187,7 @@ kgspIssueNotifyOp_GH100
     RMTIMEOUT timeout;
 
     ct_assert(sizeof(PORT_ATOMIC NvU32) == sizeof(NvU32));
-    ct_assert(_Alignof(PORT_ATOMIC NvU32) == _Alignof(NvU32));
+    ct_assert(NV_ALIGNOF(PORT_ATOMIC NvU32) == NV_ALIGNOF(NvU32));
 
     // 1. Validate the arguments.
     NV_CHECK_OR_RETURN(LEVEL_ERROR, opCode < GSP_NOTIFY_OP_OPCODE_MAX, NV_ERR_INVALID_ARGUMENT);
diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c
index 587b50866..cb59b9e93 100644
--- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c
+++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_falcon_tu102.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -337,6 +337,8 @@ s_prepareHsFalconWithLoader
     ucodePACode = memdescGetPhysAddr(pUcode->pCodeMemDesc, AT_GPU, 0);
     ucodePAData = memdescGetPhysAddr(pUcode->pDataMemDesc, AT_GPU, 0);
 
+    portMemSet(&blDmemDesc, 0, sizeof(RM_FLCN_BL_DMEM_DESC));
+
     blDmemDesc.signature[0] = 0;
     blDmemDesc.signature[1] = 0;
     blDmemDesc.signature[2] = 0;
diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
index e7f5c2afe..2f60474fe 100644
--- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
+++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
@@ -4350,12 +4350,12 @@ _kgspPrepareSystemInfo
 {
     NV_STATUS status;
 
+    NV_ASSERT_OR_RETURN(rmapiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE);
+
     OBJSYS *pSys = SYS_GET_INSTANCE();
     OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys);
     GspSystemInfo *rpcInfo = portMemAllocPaged(sizeof(GspSystemInfo));
 
-    NV_ASSERT_OR_RETURN(rmapiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE);
-
     if (rpcInfo == NULL)
         return NV_ERR_NO_MEMORY;
 
diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c
index fda81e577..b531b8209 100644
--- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c
+++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c
@@ -237,7 +237,7 @@ GspMsgQueuesInit
         memdescCreate(&pMQCollection->pSharedMemDesc, pGpu, sharedBufSize,
             RM_PAGE_SIZE, NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, NV_MEMORY_CACHED,
             flags),
-        done);
+        error_ret);
 
     memdescSetFlag(pMQCollection->pSharedMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE);
 
diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c
index 800edfd0f..3c514acca 100644
--- a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c
+++ b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c
@@ -987,7 +987,8 @@ channelFillSec2Pb
 
     *pMethodLength = 0;
     NvU32 methodSize = (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr);
-    NV_ASSERT_OR_RETURN(methodSize <= pChannel->methodSizePerBlock, NV_ERR_INVALID_STATE);
+    NV_ASSERT_TRUE_OR_GOTO(status, methodSize <= pChannel->methodSizePerBlock,
+        NV_ERR_INVALID_STATE, cleanup);
     *pMethodLength = methodSize;
 
 cleanup:
diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c
index 17e8f7dfc..f731fc48d 100644
--- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c
+++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c
@@ -774,7 +774,7 @@ memmgrVerifyGspDmaOps_IMPL
 {
     KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu);
     NV_STATUS status = NV_OK;
-    MEMORY_DESCRIPTOR *pMemDesc;
+    MEMORY_DESCRIPTOR *pMemDesc = NULL;
     NvU8 *pTestBuffer;
     NvU32 testData = 0xdeadbeef;
     TRANSFER_SURFACE surf = {0};
@@ -793,7 +793,7 @@ memmgrVerifyGspDmaOps_IMPL
 
     status = memdescCreate(&pMemDesc, pGpu, RM_PAGE_SIZE, RM_PAGE_SIZE,
                            NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, 0);
-    NV_ASSERT_OR_RETURN(status == NV_OK, status);
+    NV_ASSERT_OR_GOTO(status == NV_OK, failed);
 
     memdescTagAlloc(status,
                     NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_20, pMemDesc);
diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c
index 2917ba0fb..e87df77ee 100644
--- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c
+++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c
@@ -7081,6 +7081,7 @@ kmigmgrInitGPUInstanceRunlistBufPools_IMPL
     KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance
 )
 {
+    NV_STATUS         status = NV_OK;
     RM_ENGINE_TYPE    rmEngineType;
     KernelFifo       *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu);
     CTX_BUF_INFO     *runlistBufInfo = NULL;
@@ -7136,29 +7137,44 @@ kmigmgrInitGPUInstanceRunlistBufPools_IMPL
         //
         for (i = 0; i < rlCount; i++)
         {
-            NV_ASSERT_OK_OR_RETURN(kfifoGetRunlistBufInfo(pGpu, pKernelFifo, runlistId,
-                                   0, &rlSize, &rlAlign));
+            NV_ASSERT_OK_OR_GOTO(status,
+                kfifoGetRunlistBufInfo(pGpu, pKernelFifo, runlistId,
+                                      0, &rlSize, &rlAlign),
+                cleanup);
+
             runlistBufInfo[i].size = rlSize;
             runlistBufInfo[i].align = rlAlign;
             runlistBufInfo[i].attr = RM_ATTR_PAGE_SIZE_DEFAULT;
             runlistBufInfo[i].bContig = NV_TRUE;
         }
 
-        NV_ASSERT_OK_OR_RETURN(ctxBufPoolInit(pGpu, pHeap, &pKernelFifo->pRunlistBufPool[rmEngineType]));
-        NV_ASSERT_OR_RETURN(pKernelFifo->pRunlistBufPool[rmEngineType] != NULL, NV_ERR_INVALID_STATE);
+        NV_ASSERT_OK_OR_GOTO(status,
+            ctxBufPoolInit(pGpu, pHeap, &pKernelFifo->pRunlistBufPool[rmEngineType]),
+            cleanup);
+
+        NV_ASSERT_TRUE_OR_GOTO(status,
+            pKernelFifo->pRunlistBufPool[rmEngineType] != NULL,
+            NV_ERR_INVALID_STATE, cleanup);
 
         //
         // Skip scrubber for runlist buffer alloctions since gpu instance scrubber is not setup yet
         // and it will be destroyed before deleting the runlist buffer pool.
         //
         ctxBufPoolSetScrubSkip(pKernelFifo->pRunlistBufPool[rmEngineType], NV_TRUE);
-        NV_ASSERT_OK_OR_RETURN(ctxBufPoolReserve(pGpu, pKernelFifo->pRunlistBufPool[rmEngineType], &runlistBufInfo[0], rlCount));
 
+        NV_ASSERT_OK_OR_GOTO(status,
+            ctxBufPoolReserve(pGpu, pKernelFifo->pRunlistBufPool[rmEngineType],
+                              &runlistBufInfo[0], rlCount),
+            cleanup);
+
+cleanup:
         portMemFree(runlistBufInfo);
         runlistBufInfo = NULL;
+        if (status != NV_OK)
+            break;
     }
 
-    return NV_OK;
+    return status;
 }
 
 /*
diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c
index f806b991c..0ccf5ec60 100644
--- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c
+++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c
@@ -1837,6 +1837,10 @@ knvlinkUpdatePostRxDetectLinkMask_IMPL
 
     FOR_EACH_IN_BITVECTOR(&pKernelNvlink->enabledLinks, i)
     {
+        if (i >= pKernelNvlink->maxNumLinks)
+        {
+            break;
+        }
         pKernelNvlink->nvlinkLinks[i].laneRxdetStatusMask = params.laneRxdetStatusMask[i];
     }
     FOR_EACH_IN_BITVECTOR_END();
diff --git a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c
index 3bbbbde41..926fa8fae 100644
--- a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c
+++ b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
diff --git a/src/nvidia/src/kernel/gpu/timer/timer.c b/src/nvidia/src/kernel/gpu/timer/timer.c
index 5a28338c0..360be5b05 100644
--- a/src/nvidia/src/kernel/gpu/timer/timer.c
+++ b/src/nvidia/src/kernel/gpu/timer/timer.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -246,6 +246,8 @@ NV_STATUS tmrEventCreate_IMPL
         if (status != NV_OK)
         {
             NV_PRINTF(LEVEL_ERROR, "Failed to create OS timer \n");
+            portMemFree(*ppEvent);
+            *ppEvent = NULL;
         }
     }
     return status;
diff --git a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c
index dc730a665..cb6b651f9 100644
--- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c
+++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -389,7 +389,7 @@ fabricvaspaceAllocNonContiguous_IMPL
 {
     NV_STATUS status    = NV_OK;
     NvU64     freeSize  = 0;
-    NvU32     pageCount = (size / pageSize);
+    NvU32     pageCount;
     NvU64     addr;
     NvU32     idx;
     NvBool    bDefaultAllocMode;
@@ -410,6 +410,8 @@ fabricvaspaceAllocNonContiguous_IMPL
     NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(align, pageSize), NV_ERR_INVALID_ARGUMENT);
     NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(size, pageSize),  NV_ERR_INVALID_ARGUMENT);
 
+    pageCount = (NvU32)(size / pageSize);
+
     // Check if heap can satisfy the request.
     NV_ASSERT_OK_OR_RETURN(fabricvaspaceGetFreeHeap(pFabricVAS, &freeSize));
     if (freeSize < size)
diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c
index 8ad8fdd66..5fa87eb75 100644
--- a/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c
+++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2024-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
diff --git a/src/nvidia/src/kernel/rmapi/event_api.c b/src/nvidia/src/kernel/rmapi/event_api.c
index 6556b8b79..96aeaa1f9 100644
--- a/src/nvidia/src/kernel/rmapi/event_api.c
+++ b/src/nvidia/src/kernel/rmapi/event_api.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -378,23 +378,23 @@ eventapiInit_IMPL
         pNotifierClient = pRsClient;
     }
 
-    if (pNotifierClient != NULL)
-    {
-        RsResourceRef *pNotifierRef;
-        INotifier *pNotifier;
-        if (clientGetResourceRef(pNotifierClient, hNotifierResource, &pNotifierRef) != NV_OK)
-            return NV_ERR_INVALID_OBJECT;
+    if (pNotifierClient == NULL)
+        return NV_ERR_INVALID_CLIENT;
 
-        pNotifier = dynamicCast(pNotifierRef->pResource, INotifier);
-        if (pNotifier == NULL)
-            return NV_ERR_INVALID_OBJECT;
+    RsResourceRef *pNotifierRef;
+    INotifier *pNotifier;
+    if (clientGetResourceRef(pNotifierClient, hNotifierResource, &pNotifierRef) != NV_OK)
+        return NV_ERR_INVALID_OBJECT;
 
-        rmStatus = inotifyGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, &pNotifierShare);
-        if (rmStatus != NV_OK)
-            return rmStatus;
+    pNotifier = dynamicCast(pNotifierRef->pResource, INotifier);
+    if (pNotifier == NULL)
+        return NV_ERR_INVALID_OBJECT;
 
-        *pppEventNotification = inotifyGetNotificationListPtr(pNotifierShare->pNotifier);
-    }
+    rmStatus = inotifyGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, &pNotifierShare);
+    if (rmStatus != NV_OK)
+        return rmStatus;
+
+    *pppEventNotification = inotifyGetNotificationListPtr(pNotifierShare->pNotifier);
 
     serverRefShare(&g_resServ, staticCast(pNotifierShare, RsShared));
     pEvent->pNotifierShare = pNotifierShare;
diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
index 7cb37174e..88b05fc9b 100644
--- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
+++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
@@ -2545,8 +2545,11 @@ NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device,
     vaParams.flags  = gpuVaSpace->vaSize ?
                       NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT :
                       NV_VASPACE_ALLOCATION_FLAGS_NONE;
-    if (enableAts) {
-        NV_ASSERT_OR_RETURN(vaParams.flags != NV_VASPACE_ALLOCATION_FLAGS_NONE, NV_ERR_INVALID_ARGUMENT);
+    if (enableAts)
+    {
+        NV_ASSERT_TRUE_OR_GOTO(status,
+            vaParams.flags != NV_VASPACE_ALLOCATION_FLAGS_NONE,
+            NV_ERR_INVALID_ARGUMENT, cleanup_struct);
         vaParams.flags |= NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS;
     }
 
@@ -2569,7 +2572,7 @@ NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device,
                             sizeof(vaParams));
     if (status != NV_OK)
     {
-        goto cleanup_struct;
+        goto cleanup_vaspace;
     }
 
     // If base & Size were not provided before, they would have been filled now
diff --git a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c
index 7f5b4a893..e6c259d74 100644
--- a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c
+++ b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1136,18 +1136,20 @@ kernelhostvgpudeviceapiCtrlCmdSetPlacementId_IMPL
 
         portMemSet(&tmpEngineInfo, 0, sizeof(ENGINE_INFO));
 
-        NV_ASSERT_OK_OR_RETURN(kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, &tmpEngineInfo, pMigDevice));
-
-        rmStatus = vgpuMgrReserveSystemChannelIDs(pGpu,
-                                                  vgpuTypeInfo,
-                                                  pKernelHostVgpuDevice->gfid,
-                                                  pKernelHostVgpuDevice->chidOffset,
-                                                  pKernelHostVgpuDevice->channelCount,
-                                                  pMigDevice,
-                                                  pParams->numChannels,
-                                                  pKernelHostVgpuDevice->placementId,
-                                                  tmpEngineInfo.engineInfoListSize,
-                                                  tmpEngineInfo.engineInfoList);
+        rmStatus = kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, &tmpEngineInfo, pMigDevice);
+        if (rmStatus == NV_OK)
+        {
+            rmStatus = vgpuMgrReserveSystemChannelIDs(pGpu,
+                                                      vgpuTypeInfo,
+                                                      pKernelHostVgpuDevice->gfid,
+                                                      pKernelHostVgpuDevice->chidOffset,
+                                                      pKernelHostVgpuDevice->channelCount,
+                                                      pMigDevice,
+                                                      pParams->numChannels,
+                                                      pKernelHostVgpuDevice->placementId,
+                                                      tmpEngineInfo.engineInfoListSize,
+                                                      tmpEngineInfo.engineInfoList);
+        }
 
         portMemFree(tmpEngineInfo.engineInfoList);
         tmpEngineInfo.engineInfoList = NULL;
diff --git a/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c
index fb6de2b9a..b9d5d2b5a 100644
--- a/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c
+++ b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c
@@ -490,6 +490,10 @@ kvgpumgrGetCreatableVgpuTypes(OBJGPU *pGpu, KernelVgpuMgr *pKernelVgpuMgr, NvU32
                         {
                             if (pgpuInfo->vgpuTypes[i] == NULL)
                                 continue;
+
+                            if (!kvgpumgrIsMigTimeslicingModeEnabled(pGpu) && (pgpuInfo->vgpuTypes[i]->maxInstancePerGI != 1))
+                                continue;
+
                             if (pgpuInfo->vgpuTypes[i]->vgpuTypeId == vgpuSmcTypeIdMappings[j].vgpuTypeId)
                             {
                                 _addVgpuTypeToCreatableType(vgpuSmcTypeIdMappings[j].vgpuTypeId,
@@ -5086,10 +5090,13 @@ kvgpuMgrGetPlacementResource(OBJGPU *pGpu, Device *pDevice,
 NV_STATUS
 kvgpuMgrGetHeterogeneousMode(OBJGPU *pGpu, NvU32 swizzId, NvBool *bHeterogeneousModeEnabled)
 {
-    if (IS_MIG_IN_USE(pGpu) && kvgpumgrIsMigTimeslicingModeEnabled(pGpu))
+    if (IS_MIG_IN_USE(pGpu))
     {
-        NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
-            kvgpuMgrGetHeterogeneousModePerGI(pGpu, swizzId, bHeterogeneousModeEnabled));
+        if (pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_TIMESLICING_SUPPORTED) && kvgpumgrIsMigTimeslicingModeEnabled(pGpu))
+            NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
+                kvgpuMgrGetHeterogeneousModePerGI(pGpu, swizzId, bHeterogeneousModeEnabled));
+        else
+            *bHeterogeneousModeEnabled = NV_FALSE;
     }
     else
     {
diff --git a/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c b/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c
index 8d02df503..f40ebea10 100644
--- a/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c
+++ b/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c
@@ -983,7 +983,14 @@ vgpuconfigapiCtrlCmdVgpuConfigGetCapability_IMPL
              * and hence we are turning true always without checking for input device.
              * If we decided not to support any GPU, this needs to be modified.
              */
-            pGetCapabilityParams->state = IS_MIG_ENABLED(pGpu) ? NV_FALSE : NV_TRUE;
+            if (pPhysGpuInfo->numVgpuTypes != 0)
+            {
+                pGetCapabilityParams->state = IS_MIG_ENABLED(pGpu) ? NV_FALSE : NV_TRUE;
+            }
+            else
+            {
+                pGetCapabilityParams->state = NV_FALSE;
+            }
             break;
         }
         case NVA081_CTRL_VGPU_CAPABILITY_DEVICE_STREAMING:
@@ -1010,7 +1017,14 @@ vgpuconfigapiCtrlCmdVgpuConfigGetCapability_IMPL
             /* We are not currently limiting the feature based on the pgpu.
              * Return the system level value here.
              */
-            pGetCapabilityParams->state = kvgpumgrIsHeterogeneousVgpuTypeSupported();
+            if (pPhysGpuInfo->numVgpuTypes != 0)
+            {
+                pGetCapabilityParams->state = kvgpumgrIsHeterogeneousVgpuTypeSupported();
+            }
+            else
+            {
+                pGetCapabilityParams->state = NV_FALSE;
+            }
             break;
         }
         case NVA081_CTRL_VGPU_CAPABILITY_FRACTIONAL_MULTI_VGPU:
@@ -1025,12 +1039,26 @@ vgpuconfigapiCtrlCmdVgpuConfigGetCapability_IMPL
         }
         case NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_SUPPORTED:
         {
-            pGetCapabilityParams->state = pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_TIMESLICING_SUPPORTED);
+            if (pPhysGpuInfo->numVgpuTypes != 0)
+            {
+                pGetCapabilityParams->state = pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_TIMESLICING_SUPPORTED);
+            }
+            else
+            {
+                pGetCapabilityParams->state = NV_FALSE;
+            }
             break;
         }
         case NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_MODE_ENABLED:
         {
-            pGetCapabilityParams->state = kvgpumgrIsMigTimeslicingModeEnabled(pGpu);
+            if (pPhysGpuInfo->numVgpuTypes != 0)
+            {
+                pGetCapabilityParams->state = kvgpumgrIsMigTimeslicingModeEnabled(pGpu);
+            }
+            else
+            {
+                pGetCapabilityParams->state = NV_FALSE;
+            }
             break;
         }
         default:
diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c
index 9d97736ff..b0f56fd44 100644
--- a/src/nvidia/src/libraries/resserv/src/rs_server.c
+++ b/src/nvidia/src/libraries/resserv/src/rs_server.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1698,7 +1698,9 @@ serverCopyResource
 
     status = clientGetResourceRef(pClientSrc, pParams->hResourceSrc, &pResourceRefSrc);
     if (status != NV_OK)
+    {
         goto done;
+    }
 
     if (pResourceRefSrc->bInvalidated)
     {
@@ -1708,7 +1710,9 @@ serverCopyResource
 
     status = clientGetResourceRef(pClientDst, pParams->hParentDst, &pParams->pDstParentRef);
     if (status != NV_OK)
+    {
         return status;
+    }
 
     if (!resCanCopy(pResourceRefSrc->pResource))
     {
diff --git a/version.mk b/version.mk
index 3c97a79d5..311dc0c63 100644
--- a/version.mk
+++ b/version.mk
@@ -1,5 +1,5 @@
-NVIDIA_VERSION = 595.45.04
-NVIDIA_NVID_VERSION = 595.45.04
+NVIDIA_VERSION = 595.58.03
+NVIDIA_NVID_VERSION = 595.58.03
 NVIDIA_NVID_EXTRA = 
 
 # This file.