CITATION

* If these tools were used for your research and you think it was useful, please cite some of the following papers:


@inproceedings{Horowitz:2010:FAM:1837274.1837381,
 author = {Horowitz, Mark and Jeeradit, Metha and Lau, Frances and Liao, Sabrina and Lim, ByongChan and Mao, James},
 title = {Fortifying Analog Models with Equivalence Checking and Coverage Analysis},
 booktitle = {Proceedings of the 47th Design Automation Conference},
 series = {DAC '10},
 year = {2010},
 isbn = {978-1-4503-0002-5},
 location = {Anaheim, California},
 pages = {425--430},
 numpages = {6},
 url = {http://doi.acm.org/10.1145/1837274.1837381},
 doi = {10.1145/1837274.1837381},
 acmid = {1837381},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {analog validation, design methodology, equivalence checking, fault coverage, formal validation, model-first design},
} 

@INPROCEEDINGS{5523251, 
author={B. C. Lim and J. Kim and M. A. Horowitz}, 
booktitle={Design Automation Conference}, 
title={An efficient test vector generation for checking analog/mixed-signal functional models}, 
year={2010}, 
volume={}, 
number={}, 
pages={767-772}, 
keywords={automatic test pattern generation;mixed analogue-digital integrated circuits;analog circuits;analog functional models;analogcircuits;linear abstraction;linear system;mixed-signal circuits;mixed-signal functional models;serial link receiver;test vector generation;Algorithm design and analysis;Analog circuits;Character generation;Circuit testing;Hardware design languages;Integrated circuit modeling;Linear systems;Linearity;Signal design;Vectors;Equivalence checking;Functional model;Linear abstraction;Mixed-signal circuits;Test vector;Validation;Verilog}, 
doi={}, 
ISSN={0738-100X}, 
month={June},}

@ARTICLE{6917049, 
author={B. C. Lim and J. E. Jang and J. Mao and J. Kim and M. Horowitz}, 
journal={IEEE Design Test}, 
title={Digital Analog Design: Enabling Mixed-Signal System Validation}, 
year={2015}, 
volume={32}, 
number={1}, 
pages={44-52}, 
keywords={electronic design automation;integrated circuit design;integrated circuit modelling;integrated circuit testing;mixed analogue-digital integrated circuits;transistor circuits;analog circuit;analog test program content;digital CAD tools;digital analog design;digital model;fault coverage information;mixed-signal circuits;mixed-signal system validation;Analog circuits;Formal verification;Linear systems;Mathematical model;Mixed analog digital integrated circuits;System-on-chip;Testing;Analog validation;SystemVerilog;behavioral modeling;design methodology;equivalence checking;event-driven simulation;linear abstraction;test vector generation}, 
doi={10.1109/MDAT.2014.2361718}, 
ISSN={2168-2356}, 
month={Feb},}

@ARTICLE{7390222, 
author={B. C. Lim and M. Horowitz}, 
journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, 
title={Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models}, 
year={2016}, 
volume={63}, 
number={1}, 
pages={23-33}, 
keywords={analogue circuits;discrete time systems;hardware description languages;piecewise linear techniques;system-on-chip;analog circuits;continuous-time feedback;discrete-time event simulator;error control;event-driven piecewise linear analog functional models;hardware description languages;limit cycle elimination;mixed-signal SoC;Analog circuits;Computational modeling;Error correction;Feedback loop;Limit-cycles;Linear systems;Mathematical model;Feedback;Verilog;limit cycle;linear system;mixed-signal system;modeling;piecewise linear}, 
doi={10.1109/TCSI.2015.2512699}, 
ISSN={1549-8328}, 
month={Jan},}