update; fix pecom32/64.

# Conflicts:
#	docs/source/initialsetup/compilingmame.rst

Author: Robbbert

.github/workflows/ci-windows.yml

@@ -29,16 +29,17 @@ jobs:
         include:
           - compiler: gcc-x64
             os: windows-latest
-            msys: MINGW64
-            slug: mingw-w64-x86_64
+            msys: UCRT64
+            slug: mingw-w64-ucrt-x86_64
             cc: gcc
             cxx: g++
             subtarget: mame
             executable: mame
           - compiler: clang-x64
             os: windows-latest
-            msys: MINGW64
-            slug: mingw-w64-x86_64
+            msys: CLANG64
+            slug: mingw-w64-clang-x86_64
+            extrapkg: mingw-w64-clang-x86_64-gcc-compat
             cc: clang
             cxx: clang++
             subtarget: tiny

makefile

@@ -150,6 +150,8 @@ ifeq ($(MSYSTEM),MINGW32)
 PLATFORM := x86
 else ifeq ($(MSYSTEM),MINGW64)
 PLATFORM := x86
+else ifeq ($(MSYSTEM),UCRT64)
+PLATFORM := x86
 else ifeq ($(MSYSTEM),CLANG64)
 PLATFORM := x86
 else ifeq ($(MSYSTEM),CLANGARM64)
@@ -243,6 +245,8 @@ ifeq ($(MSYSTEM),MINGW32)
 	MINGW32 := $(MINGW_PREFIX)
 else ifeq ($(MSYSTEM),MINGW64)
 	MINGW64 := $(MINGW_PREFIX)
+else ifeq ($(MSYSTEM),UCRT64)
+	MINGW64 := $(MINGW_PREFIX)
 else ifeq ($(MSYSTEM),CLANG64)
 	MINGW64 := $(MINGW_PREFIX)
 else ifeq ($(MSYSTEM),CLANGARM64)
@@ -316,6 +320,8 @@ ifeq ($(MSYSTEM),MINGW32)
 ARCHITECTURE = _x86
 else ifeq ($(MSYSTEM),MINGW64)
 ARCHITECTURE := _x64
+else ifeq ($(MSYSTEM),UCRT64)
+ARCHITECTURE := _x64
 else ifeq ($(MSYSTEM),CLANG64)
 ARCHITECTURE := _x64
 else ifeq ($(MSYSTEM),CLANGARM64)

scripts/src/3rdparty.lua

@@ -101,6 +101,12 @@ if _OPTIONS["gcc"]~=nil then
 		}
 	end
 end
+if _OPTIONS["targetos"]=="windows" then
+		buildoptions_c {
+			"-Wno-error=format", -- GCC with UCRT produces warnings for the non-standard I64 size modifier
+			"-Wno-error=format-extra-args",
+		}
+end
 
 	configuration { }
 

src/devices/bus/rs232/nss_tvinterface.cpp

@@ -171,15 +171,14 @@ u8 nss_tvinterface_device::p2_r()
 void nss_tvinterface_device::p2_w(u8 data)
 {
 	// P24: serial out (blocked by default)
-	if (m_conf->read() & 1)
-		output_rxd(BIT(data, 4));
+	output_rxd(BIT(data, 4) | BIT(m_conf->read(), 0));
 }
 
 void nss_tvinterface_device::main_map(address_map &map)
 {
 	map(0x8000, 0x87ff).ram().share(m_vram);
 
-	map(0xa3bd, 0xa3bd).portr("IN");
+	map(0xa3bd, 0xa3bd).portr("IN"); // actually through TM6310
 	map(0xa3be, 0xa3be).w(FUNC(nss_tvinterface_device::unknown_w));
 
 	map(0xa3d0, 0xa3d0).mirror(0x0006).w(m_crtc, FUNC(mc6845_device::address_w));
@@ -207,9 +206,9 @@ static INPUT_PORTS_START( nss_tvinterface )
 	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_BUTTON2) PORT_NAME("Change")
 
 	PORT_START("CONF")
-	PORT_CONFNAME( 0x01, 0x00, "Serial TxD" )
-	PORT_CONFSETTING(    0x00, DEF_STR( Off ) )
-	PORT_CONFSETTING(    0x01, DEF_STR( On ) )
+	PORT_CONFNAME( 0x01, 0x01, "Serial TxD" )
+	PORT_CONFSETTING(    0x01, DEF_STR( Off ) )
+	PORT_CONFSETTING(    0x00, DEF_STR( On ) )
 INPUT_PORTS_END
 
 ioport_constructor nss_tvinterface_device::device_input_ports() const

src/mame/capcom/bionicc.cpp

@@ -44,7 +44,9 @@
     Timings verified at SYNC pin and BLUE pin (jamma edge),
     using an Agilent DSO9404A scope and two N2873A 500MHz probes.
 
-    MAME is using jotego's timing instead (262*384).
+    The above claims result in 6MHz/(386*260) = ~59.78Hz, not 60.024Hz. MAME
+    is using 384*260 instead like tigeroad, which nearly matches an older
+    Bionic Commando measurement of H=15.625kHz, V=60.093Hz.
 
     BTANB [MT00209] (verified on real PCB):
     - misplaced sprites (see beginning of level 1 or 2 for example)
@@ -78,7 +80,6 @@
       to 128 currently to compensate.
     - The game doesn't set the coin lockout in service mode, so the coin inputs
       can't be tested there if you uncomment and enable it.
-    - Reverify video timing.
 
 ***************************************************************************/
 
@@ -516,7 +517,7 @@ u8 bionicc_state::mcu_dma_r(offs_t offset)
 {
 	u8 data = 0xff;
 
-	if (BIT(m_mcu_p3, 5) == 0)
+	if (!BIT(m_mcu_p3, 5))
 	{
 		// various address bits are pulled high because the mcu doesn't drive them
 		// the 3 upper address bits (p2.0, p2.1, p2.2) are connected to a14 to a16
@@ -529,7 +530,7 @@ u8 bionicc_state::mcu_dma_r(offs_t offset)
 
 void bionicc_state::mcu_dma_w(offs_t offset, u8 data)
 {
-	if (BIT(m_mcu_p3, 5) == 0)
+	if (!BIT(m_mcu_p3, 5))
 	{
 		offs_t address = 0xe3e01 | ((offset & 0x700) << 6) | ((offset & 0xff) << 1);
 		m_maincpu->space(AS_PROGRAM).write_byte(address, data);
@@ -547,16 +548,16 @@ void bionicc_state::mcu_p3_w(u8 data)
 	// ------1-  int0 flip-flop preset
 	// -------0  int0 ack
 
-	if (BIT(m_mcu_p3, 0) == 1 && BIT(data, 0) == 0)
+	if (BIT(m_mcu_p3, 0) && !BIT(data, 0))
 	{
 		m_mcu->set_input_line(MCS51_INT0_LINE, CLEAR_LINE);
 		m_maincpu->resume(SUSPEND_REASON_HALT);
 	}
 
-	if (BIT(m_mcu_p3, 4) == 1 && BIT(data, 4) == 0)
+	if (BIT(m_mcu_p3, 4) && !BIT(data, 4))
 		m_mcu->set_input_line(MCS51_INT1_LINE, CLEAR_LINE);
 
-	if (BIT(m_mcu_p3, 6) == 1 && BIT(data, 6) == 0)
+	if (BIT(m_mcu_p3, 6) && !BIT(data, 6))
 		m_mcu_to_audiocpu = m_mcu_p1;
 
 	m_mcu_p3 = data;
@@ -656,7 +657,7 @@ void bionicc_state::bionicc(machine_config &config)
 
 	// video hardware
 	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
-	m_screen->set_raw(24_MHz_XTAL / 4, 384, 0, 256, 262, 16, 240); // hsync is 306..333 (offset by 128), vsync is 251..253 (offset by 6)
+	m_screen->set_raw(24_MHz_XTAL / 4, 384, 0, 256, 260, 16, 240);
 	m_screen->set_screen_update(FUNC(bionicc_state::screen_update));
 	m_screen->set_palette(m_palette);
 

src/mame/capcom/tigeroad.cpp

@@ -7,18 +7,22 @@ F1 Dream       (C) 1988 Capcom
 
 cloned hardware:
 Pushman        (C) 1990 Comad
-Bouncing Balls (c) 1991 Comad
+Bouncing Balls (C) 1991 Comad
 
 Please contact Phil Stroffolino (phil@maya.com) if there are any questions
 regarding this driver.
 
+Video timing: measured 60.08Hz on Tiger Road, and 60.096Hz with 260 scanlines
+on F1 Dream. Pixel clock is 6MHz like other Capcom games.
+
 TODO:
-- F1 Dream throws an address error if player wins all the races (i.e. when the
-  game is supposed to give an ending):
+- F1 Dream throws an address error if player wins all the races in the highest
+  tier (when the game is supposed to show the ranking and highscore table):
   010C68: 102E 001C      move.b  ($1c,A6), D0       ; reads 0xf from work RAM (misaligned)
   010C6C: 207B 000E      movea.l ($e,PC,D0.w), A0   ; table from 0x10c7c onward
   010C70: 4E90           jsr     (A0)               ; throws address error here
-  None of the available 5 vectors seems to fit here, btanb?
+  None of the available 5 vectors seems to fit here.
+- what's up with the OBJ RAM test going up to 0xfe1807? address mirror?
 
 BTANB:
 - race track fg tiles have priority over minimap in f1dream
@@ -32,7 +36,7 @@ Memory Overview:
     0xfe4002    protection (F1 Dream only)
     0xfe8000    scroll registers
     0xff8200    palette
-    0xffC000    working RAM
+    0xffc000    working RAM
 
 **************************************************************************
 
@@ -71,36 +75,41 @@ void tigeroad_state::msm5205_w(u8 data)
 	m_msm->data_w(data & 0xf);
 }
 
-void f1dream_state::out3_w(u8 data)
+
+// F1 Dream protection
+
+u8 f1dream_state::mcu_shared_r(offs_t offset)
+{
+	if (!BIT(m_mcu_p3, 5))
+		return m_maincpu->space(AS_PROGRAM).read_byte(0xffffe0 | offset << 1 | 1);
+	else
+		return 0xff;
+}
+
+void f1dream_state::mcu_shared_w(offs_t offset, u8 data)
+{
+	if (!BIT(m_mcu_p3, 5))
+		m_maincpu->space(AS_PROGRAM).write_byte(0xffffe0 | offset << 1 | 1, data);
+}
+
+void f1dream_state::mcu_out3_w(u8 data)
 {
-	if ((m_old_p3 & 0x20) != (data & 0x20))
-	{
-		// toggles at the start and end of interrupt
-	}
-
-	if ((m_old_p3 & 0x01) != (data & 0x01))
-	{
-		// toggles at the end of interrupt
-		if (!(data & 0x01))
-		{
-			m_maincpu->resume(SUSPEND_REASON_HALT);
-		}
-	}
-
-	m_old_p3 = data;
+	// toggles at the end of interrupt
+	if (m_mcu_p3 & ~data & 1)
+		m_maincpu->resume(SUSPEND_REASON_HALT);
+
+	m_mcu_p3 = data;
 }
 
 void f1dream_state::to_mcu_w(u16 data)
 {
 	m_mcu->set_input_line(MCS51_INT0_LINE, HOLD_LINE);
 
-	/* after triggering this address there are one or two NOPs in the 68k code, then it expects the response to be ready
-	   the MCU isn't that fast, so either the CPU is suspended on write, or when bit 0x20 of MCU Port 3 toggles in the
-	   MCU interrupt code, however no combination of increasing the clock / boosting interleave etc. allows the MCU code
-	   to get there in time before the 68k is already expecting a result */
+	// after triggering this address there are one or two NOPs in the 68k code, then it expects the response to be ready
 	m_maincpu->suspend(SUSPEND_REASON_HALT, true);
 }
 
+
 /***************************************************************************/
 
 void tigeroad_state::main_map(address_map &map)
@@ -115,37 +124,25 @@ void tigeroad_state::main_map(address_map &map)
 	map(0xfe4002, 0xfe4002).w("soundlatch", FUNC(generic_latch_8_device::write));
 	map(0xfe4004, 0xfe4005).portr("DSW");
 	map(0xfe8000, 0xfe8003).w(FUNC(tigeroad_state::scroll_w));
-	map(0xfe800e, 0xfe800f).nopw();    // fe800e = watchdog or IRQ acknowledge
+	map(0xfe800e, 0xfe800f).nopw();    // fe800e = watchdog or IRQ acknowledge or sprite DMA
 	map(0xfec000, 0xfec7ff).ram().w(FUNC(tigeroad_state::videoram_w)).share("videoram");
 
 	map(0xff8000, 0xff87ff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
-	map(0xffc000, 0xffffff).ram().share("ram16");
-}
-
-
-u8 f1dream_state::mcu_shared_r(offs_t offset)
-{
-	u8 ret = m_ram16[(0x3fe0 / 2) + offset];
-	return ret;
-}
-
-void f1dream_state::mcu_shared_w(offs_t offset, u8 data)
-{
-	m_ram16[(0x3fe0 / 2) + offset] = (m_ram16[(0x3fe0 / 2) + offset] & 0xff00) | data;
+	map(0xffc000, 0xffffff).ram();
 }
 
 void f1dream_state::f1dream_map(address_map &map)
 {
 	main_map(map);
-	map(0xfe4002, 0xfe4003).portr("SYSTEM").w(FUNC(f1dream_state::to_mcu_w));
+	map(0xfe4002, 0xfe4003).w(FUNC(f1dream_state::to_mcu_w));
 }
 
 void f1dream_state::f1dream_mcu_data(address_map &map)
 {
+	// never accesses under 0x7f0
 	map(0x7f0, 0x7ff).rw(FUNC(f1dream_state::mcu_shared_r), FUNC(f1dream_state::mcu_shared_w));
 }
 
-
 void pushman_state::pushman_map(address_map &map)
 {
 	main_map(map);
@@ -172,7 +169,7 @@ void pushman_state::bballs_map(address_map &map)
 	map(0xec000, 0xec7ff).ram().w(FUNC(pushman_state::videoram_w)).share("videoram");
 
 	map(0xf8000, 0xf87ff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
-	map(0xfc000, 0xfffff).ram().share("ram16");
+	map(0xfc000, 0xfffff).ram();
 }
 
 // Capcom games ONLY
@@ -637,9 +634,8 @@ void tigeroad_state::tigeroad(machine_config &config)
 	// video hardware
 	BUFFERED_SPRITERAM16(config, "spriteram");
 
-	// Timings may be different, driver originally had 60.08Hz vblank.
 	screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
-	screen.set_raw(24_MHz_XTAL / 4, 384, 0, 256, 262, 16, 240); // hsync is 306..333 (offset by 128), vsync is 251..253 (offset by 6)
+	screen.set_raw(24_MHz_XTAL / 4, 384, 0, 256, 260, 16, 240);
 	screen.set_screen_update(FUNC(tigeroad_state::screen_update));
 	screen.screen_vblank().set("spriteram", FUNC(buffered_spriteram16_device::vblank_copy_rising));
 	screen.set_palette(m_palette);
@@ -668,7 +664,7 @@ void tigeroad_state::tigeroad(machine_config &config)
 
 void f1dream_state::machine_start()
 {
-	save_item(NAME(m_old_p3));
+	save_item(NAME(m_mcu_p3));
 }
 
 void f1dream_state::f1dream(machine_config &config)
@@ -677,10 +673,10 @@ void f1dream_state::f1dream(machine_config &config)
 
 	m_maincpu->set_addrmap(AS_PROGRAM, &f1dream_state::f1dream_map);
 
-	I8751(config, m_mcu, 10_MHz_XTAL); // 8MHz rated chip, 10MHz or 6MHz(24/4)?
+	I8751(config, m_mcu, 24_MHz_XTAL / 4); // 6MHz
 	m_mcu->set_addrmap(AS_DATA, &f1dream_state::f1dream_mcu_data);
 	m_mcu->port_out_cb<1>().set("soundlatch", FUNC(generic_latch_8_device::write));
-	m_mcu->port_out_cb<3>().set(FUNC(f1dream_state::out3_w));
+	m_mcu->port_out_cb<3>().set(FUNC(f1dream_state::mcu_out3_w));
 }
 
 // same as above but with additional Z80 for samples playback
@@ -717,7 +713,7 @@ void tigeroad_state::f1dream_comad(machine_config &config) // COMAD-01 PCB with
 	BUFFERED_SPRITERAM16(config, "spriteram");
 
 	screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
-	screen.set_raw(24_MHz_XTAL / 4, 384, 0, 256, 262, 16, 240); // hsync is 306..333 (offset by 128), vsync is 251..253 (offset by 6)
+	screen.set_raw(24_MHz_XTAL / 4, 384, 0, 256, 260, 16, 240); // assume same as tigeroad
 	screen.set_screen_update(FUNC(tigeroad_state::screen_update));
 	screen.screen_vblank().set("spriteram", FUNC(buffered_spriteram16_device::vblank_copy_rising));
 	screen.set_palette(m_palette);

src/mame/capcom/tigeroad.h

@@ -129,8 +129,7 @@ class f1dream_state : public tigeroad_state
 	f1dream_state(const machine_config &mconfig, device_type type, const char *tag)
 		: tigeroad_state(mconfig, type, tag)
 		, m_mcu(*this, "mcu")
-		, m_ram16(*this, "ram16")
-		, m_old_p3(0xff)
+		, m_mcu_p3(0xff)
 	{
 	}
 
@@ -143,14 +142,13 @@ class f1dream_state : public tigeroad_state
 	void f1dream_map(address_map &map) ATTR_COLD;
 	void f1dream_mcu_data(address_map &map) ATTR_COLD;
 
-	void out3_w(u8 data);
+	void mcu_out3_w(u8 data);
 
 	u8 mcu_shared_r(offs_t offset);
 	void mcu_shared_w(offs_t offset, u8 data);
 
 	void to_mcu_w(u16 data);
 
 	required_device<i8751_device> m_mcu;
-	required_shared_ptr<u16> m_ram16;
-	u8 m_old_p3;
+	u8 m_mcu_p3;
 };